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S 7084
wn B. Tech. vir. Sem, a) Exam. Feb.-March - 2021
a Electronics &O, ‘ommunication Engineering
7ECsA VLSI Design
Time: 2 Hours Maximum Marks: 48
Min. Passing Marks: 15
Instructions to Candidates: .
Attempt three questions, selecting one question each from any three unit. All
Questions carry equal marks, Schematic diagrams must be shown wherever
necessary, Any data you feel missing suitably be assumed and stated clearly. Units
Of quantities used/ calculated must he stated clearly.
Use of following supporting material is permitted during examination.
(Mentioned in form No.205)
HN . 2, NIL.
UNIT- I
Q.1 (a) Draw and write the working of gnhancement mode PMOS with the help of input-
output and transfer characteristics. [8]
(b) Write'the names and compare the three,technologies used for the fabrication of
{CMOS transistor. (8)
OR
Q.1 (a) What are the different factors affecting the threshold voltage of MOSFET? Derive
the formula used, Also, derive the body effect coefficient. {8]
Draw, MOQS_transistor_circuit, model and explain the origination of each
parameter. ~ [8]
[7E7084) Page 1 of 3 {1220}
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Q2 (a) Draw voltage transfer character VLOMOS fiver an
expression for Bn/Bp ratio.
APOE Miss ier
(b) Write the names of three types OEE Ssipation oo CHIC
et BSD AtiOn
derive the expression for total po*
a
OR
Q2 (a) Design the following logic circuits EN" Cigs, logic pane —
() 3 input NAND gate
(i) S-R Flip-flop
(b) Implement the Boolean expression F =a (bse) y
determine the size of each transistor using egy
UNIT- Tit
jayout diagram for
out diagram for
size/spacing using 2. -rules,
uioo‘ouluonL ay /sday
OR
Q3 ee ran ich-up problem in CMOS? Draw and explain its physical onigin evel
and.
rite the names and explain the techniques used to prevent latch-up proisiem. {i
UNIT- Iv
~
Qa or Compare ORS nd NPCZIPPE:
(b) Explain various circuit techniques used_in domino CMOS circuits for solving
) CMOS logic structures. 18)
charge sharing problem 13]
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i) ions [8}
. lowing operations
a DRAM gl and exp the follo
@ §
) Synchronous read mode
Q4 (a) Draw acircuit diagram of
) Asynchronous read mode
Leakage currents and
Fefresh operation
$2Draw SRAM cell and explain its witeand read operation with appropriate timing
— iteand read one
diagram, {8}
UNIT- V
Q5 (a) Draw VHDLIPLD based ASIC design flow black diagram. Explain each step
z involved. OO aay z
Z involved. Z
$ (6) Write VHDL code for positive edge triggered S-R flip-flop. 1 $
fo “a
2 QS (a) Write VHDL code for,half adder in structural style. 81 a
5 a 5
8 . sot shift regi i input. {8} 8
2 Write VHDL model for left to right shift register using enable inp 5.
5 (by Write model for left to rights =
° o
8 8
3 3
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Send your old paper & get 10/-
ane geet dag sar atte 10 er ors,
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(1220)
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