Lecture 11: Semiconductor memory I
NVM, SRAM, DRAM
Hyeon-Min Bae
Department of Electrical Engineering
KAIST, Daejeon, Korea
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Chapter Overview
q Memory Classification
q Memory Architectures
q The Memory Core
q Periphery
q Reliability
q Case Studies
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Semiconductor Memory Classification
Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory
Random Non-Random
EPROM Mask-Programmed
Access Access
E2PROM Programmable (PROM)
SRAM FIFO FLASH
DRAM LIFO
Shift Register
CAM
Non-random are fast, ex) video memory
CAM: contents addressable memory (or associative
memory), use query style format to access memory
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Memory Timing: Definitions
Read cycle == write cycle in general
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Memory Architecture: Decoders
M bits M bits
S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Nwords
Word 2 Word 2
Decoder
cell A1 cell
AK2 1
SN - 2
Word N - 2 Word N 2 2
SN - 1
Word N - 1 Word N 2 1
K 5 log2N
Input-Output Input-Output
(M bits) (M bits)
Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals:
N words == N select signals
K = log2N
(only one select signal is high) Still HEIGHT >> WIDTH
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Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Solution: Row decoder + Column decoder
Target
Height==Width
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Valid for 64Kb~256Kb memories
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Example
• Memory array of 4000x2000 (4096x2048)
• 2048 = 256 8-bit words
• 12bit row address
• 8bit column address
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Hierarchical Memory Architecture
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
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Block Diagram of 4 Mbit SRAM
Clock Z-address X-address
[Hirose90]
generator buffer buffer
Predecoder and block selector
Bit line load
128 K Array Block 0
Subglobal row decoder
Subglobal row decoder
Global row decoder
Block 1
30
Block 31
Block
Transfer gate
Local row decoder
Column decoder
Sense amplifier and write driver
CS, WE I/O x1/x4 Y-address X-address
buffer buffer controller buffer buffer
32 blocks (each 128K), each block: 1024 row, 128 columns
Row (X): 10 bits, Column (Y): 7 bits, Block (Z): 5 bits
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Read-Only Memory Cells
BL BL BL
VDD
WL
WL WL
1
BL BL BL
WL WL
WL
0
GND
Diode ROM MOS ROM 1 MOS ROM 2
Diode ROM: Bit line resistively grounded. WL supplies current.
MOS ROM: Sourcing/sinking current from/to local VDD/GND.
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MOS OR ROM
BL[0] BL[1] BL[2] BL[3]
WL[0]
VDD
WL[1]
WL[2]
VDD
WL[3]
Vbias
Pull-down loads
Reduction of overhead by sharing VDD btw odd & even WL
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MOS NOR ROM
V DD
Pull-up devices
WL [0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0] BL [1] BL [2] BL [3]
Same as psudo NMOS NOR gates
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MOS NOR ROM Layout
Cell (9.5l x 7l)
GND Programmming using the
Active Layer Only
Polysilicon
GND Metal1 on Diffusion
Metal1
Diffusion
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MOS NOR ROM Layout
Cell (11l x 7l)
Programmming using
the Contact Layer Only
Polysilicon
Diffusion
Metal1
Metal1 on Diffusion
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MOS NAND ROM
V DD
Pull-up devices
BL [0] BL [1] BL [2] BL [3]
WL [0]
WL [1]
WL [2]
WL [3]
All word lines high by default with exception of selected row
BL goes low when selected
Advantage: No GND or VDD
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MOS NAND ROM Layout
Cell (8l x 7l)
Programmming using
the Metal-1 Layer Only
No contact to VDD or GND necessary;
drastically reduced cell size
Loss in performance compared to NOR ROM
Polysilicon
Diffusion
Metal1 on Diffusion
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NAND ROM Layout
Cell (5l x 6l)
Programmming using
Implants Only
Polysilicon
Threshold-altering
Area reduction at the cost of additional processes implant
Creating depletion TR to create short.
Metal1 on Diffusion
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Equivalent Transient Model for MOS NOR ROM
Model for NOR ROM V DD
BL
r word
WL Cbit
cword
• Word line parasitics
– Wire capacitance and gate capacitance
– Wire resistance (polysilicon)
• Bit line parasitics
– Resistance not dominant (metal)
– Drain and Gate-Drain capacitance
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Pseudo-NMOS
Vin=VDDà VOL>0
MP IDP NMOS: Vel. Sat
PMOS: Vel. Sat
vout
MN IDN
vi
𝐼!" + 𝐼!# = 0
(
𝑉!&'$%
𝐾" 𝑉!! − 𝑉$% 𝑉!&'$ − 1 + 𝜆% 𝑉)*
2
(
𝑉!&'$+
+ 𝐾# −𝑉!! − 𝑉$+ 𝑉!&'$+ − 1 + 𝜆% (𝑉)* −𝑉!! )
2
VOL= 1.5V, VDD=2.5V & determine KN, KP
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Equivalent Transient Model for MOS NAND ROM
V DD
Model for NAND ROM
BL
CL
r bit
cbit
r word
WL
cword
q Word line parasitics
§ Similar to NOR ROM
q Bit line parasitics
§ Resistance of cascaded transistors dominates
§ Drain/Source and complete gate capacitance
§ Equivalent to a long TR for large arrays. à Impractical for 8
or 16 row memories
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Decreasing Word Line Delay
Driver
WL Polysilicon word line
Metal word line
(a) Driving the word line from both sides
Metal bypass
WL K cells Polysilicon word line
(b) Using a metal bypass
(c) Use silicides
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Precharged MOS NOR ROM
f pre
V DD
Precharge devices
WL [0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0] BL [1] BL [2] BL [3]
PMOS precharge device can be made as large as necessary,
but clock driver becomes harder to design.
Can be catastrophic in NAND ROM
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Non-Volatile Memories
The Floating-gate transistor (FAMOS)
Floating gate Gate
D
Source Drain
tox G
tox
S
n+ p n+_
Substrate
Device cross-section Schematic symbol
Virtually identical to ROM structure
Reduced transconductance, increased tox
Programmable threshold
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Floating-Gate Transistor Programming
FAMOS (floating gate avalance-injection MOS)
20 V 0V 5V
10 V 5V 20 V -5 V 0V -2.5 V 5V
S D S D S D
Avalanche injection Removing programming Programming results in
voltage leaves charge trapped higher V T .
• Gate voltage >10V à avalanch injection of electron
(traverse through first oxide layer)à trapped on the
floating gateà self limiting (field reduction)
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A “Programmable-Threshold” Transistor
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FLOTOX EEPROM (Electrically erasable programmable read-only memory)
Floating gate Gate I
Source Drain
20–30 nm -10 V V GD
10 V
n1 n1
Substrate
p
10 nm
Fowler-Nordheim
FLOTOX transistor
I-V characteristic
FLOTOX: floating gate tunneling oxide
Electrically erasable programmable read-only memory
Large area and fabrication issues but long lasting.
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EEPROM Cell
BL
Due to process variation à
threshold control is hard
WL
Unprogrammed transistor
might be depletion (hard to turn off)
VDD ð 2 transistor cell
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Flash EEPROM
Control gate
Floating gate
SiO-SiN-SiO (ONO)
erasure Thin tunneling oxide
n + source n + drain
programming
p-substrate
Program mode: High control gate
Erase mode: High Sub voltage
Charge in floating gate: high threshold
No charge in floating gate: reg. threshold
Charge à 0, No charge à 1
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NOR flash memory
𝑄,- = 𝐶,. 𝑉,- − 𝑉.- + 𝐶& 𝑉,- − 𝑉& + 𝐶! (𝑉,- − 𝑉! )+
𝐶/ (𝑉,- − 𝑉/ )
0!" .!$ .% . .
𝑉,- = + 𝑉 + 𝑉& + & 𝑉! + ' 𝑉/
.# .# .- .# .# .#
𝐶$ = 𝐶,. + 𝐶& + 𝐶! +𝐶/
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NOR flash memory
If both source and bulk are grounded,
𝑄,- 𝐶,. 𝐶!
𝑉,- = + 𝑉.- + 𝑉!&
𝐶$ 𝐶$ 𝐶$
Transistor operation is determined by VT(FG) and VFG
VT(CG) is a function of VT(FG)
𝐶$ 𝑄,- 𝐶!
𝑉$ 𝐶𝐺 = 𝑉$ 𝐹𝐺 − − 𝑉!&
𝐶,. 𝐶,. 𝐶,.
Thereshold voltage is affected by QFG
∆𝑄,-
∆𝑉$ 𝐶𝐺 =
𝐶,.
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Basic Operations in a NOR Flash Memory―Erase
Fowler-Nordheim tunneling for erase
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Basic Operations in a NOR Flash Memory―Write
Drain voltage raisedà generation of hot electron à
injected to the floating gate
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Basic Operations in a NOR Flash Memory―Read
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Characteristics of State-of-the-art NVM
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Read-Write Memories (RAM)
q STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
q DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
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6-transistor CMOS SRAM Cell
WL
V DD
M2 M4
Q
M5 Q M6
M1 M3
BL BL
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CMOS SRAM Analysis (Read)
WL
V DD
BL M4
BL
Q= 0
Q= 1 M6
M5
V DD M1 V DD V DD
Cbit Cbit
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CMOS SRAM Analysis (Read)
1.2
1
Voltage Rise (V)
0.8
0.6
0.4
0.2
0
0 0.5 1 1.2 1.5 2 2.5 3
Cell Ratio (CR)
CR has to be greater than 1.2 to prevent rising over VTN
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CMOS SRAM Analysis (Write)
WL
V DD
M4
Q= 0 M6
M5 Q= 1
M1
V DD
BL = 1 BL = 0
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CMOS SRAM Analysis (Write)
Pull up ratio has to be less than 1.8 to make VQ < VTN
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6T-SRAM — Layout
VDD
M2 M4
Q Q
M1 M3
GND
M5 M6 WL
BL BL
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Resistance-load SRAM Cell
WL
V DD
RL RL
Q Q
M3 M4
BL M1 M2 BL
Static power dissipation -- Want RL large
Bit lines precharged to V DD to address t p problem
30% Cell size reduction as compared to 6T
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SRAM Characteristics
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3-Transistor DRAM Cell
BL 1 BL 2
WWL
RWL WWL
M3 RWL
M1 X X VDD 2 VT
M2
VDD
CS BL 1
BL 2 VDD 2 VT DV
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = VWWL-VTN
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1-Transistor DRAM Cell
Write: C S is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
𝐶& + 𝐶/* 𝑉/* = 𝐶& 𝑉/1$ + 𝐶/* 𝑉+23
CS
DV = VBL – V PRE = V BIT – V PRE ------------
C S + CBL
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DRAM Cell Observations
q 1T DRAM requires a sense amplifier for each bit line, due to
charge redistribution read-out.
q DRAM memory cells are single ended in contrast to SRAM
cells.
qThe read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
q Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
q When writing a “1” into a DRAM cell, a threshold voltage is
lost. This charge loss can be circumvented by bootstrapping
the word lines to a higher value than VDD
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Sense Amp Operation
V BL V(1)
V PRE
V(1)
V(0)
Sense amp activated t
Word line activated
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