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FINFET Technology

The document describes the fabrication process for FinFET technology. It details the 7 key steps: 1) starting with a substrate and hard mask, 2) etching fins, 3) depositing oxide for isolation, 4) planarization, 5) recessing the oxide, 6) depositing a gate oxide, and 7) depositing a highly doped poly silicon gate wrapped around the fins.

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Bck Sreedhar
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237 views6 pages

FINFET Technology

The document describes the fabrication process for FinFET technology. It details the 7 key steps: 1) starting with a substrate and hard mask, 2) etching fins, 3) depositing oxide for isolation, 4) planarization, 5) recessing the oxide, 6) depositing a gate oxide, and 7) depositing a highly doped poly silicon gate wrapped around the fins.

Uploaded by

Bck Sreedhar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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PHYSICAL

DESIGN FinFET Technology Fabrication

Chankeerth

Please feel free to reach me out : [email protected]


PHYSICAL DESIGN
FinFET Fabrication
1. Substrate
Basis for a FinFET is a lightly p-doped
substrate with a hard mask on top
(e.g. silicon nitride) as well as a
patterned resist layer.

2. Fin Etch
The fins are formed in a highly
anisotropic etch process. Since there
is no stop layer on a bulk wafer as it is
in SOI, the etch process has to be time
based. In a 22 nm process the width of
the fins might be 10 to 15 nm, the
height would ideally be twice that or
more.
Image source: Google

PHYSICAL DESIGN
FinFET Fabrication
3. Oxide Deposition
To isolate the fins from each other a
oxide deposition with a high aspect
ratio filling behavior is needed

4. Planarization
The oxide is planarized by
chemical mechanical polishing.
The hard mask acts as a stop layer

Image source: Google

PHYSICAL DESIGN
FinFET Fabrication
5. Recess Etch
Another etch process is needed to
recess the oxide film to form a lateral
isolation of the fins

6. Gate Oxide
On top of the fins the gate oxide is
deposited via thermal oxidation to
isolate the channel from the gate
electrode

• Since the fins are still connected


underneath the oxide, a high-dose
angled implant at the base of the fin
creates a dopant junction and
completes the isolation (not
illstrated) Image source: Google

PHYSICAL DESIGN
FinFET Fabrication
7. Deposition of the gate
Finally a highly n+-doped poly silicon layer is deposited on top of the fins,
thus up to three gates are wrapped around the channel: one on each side
of the fin, and - depending on the thickness of the gate oxide on top - a
third gate above.

• The influence of the top gate can also be inhibited by the deposition of
a nitride layer on top of the channel.

Image source: Google

PHYSICAL DESIGN
Thank you

Please feel free to reach me out : [email protected]


PHYSICAL DESIGN

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