BACS1024
INTRODUCTION TO
COMPUTER SYSTEMS
Chapter 4: Computer Memory
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Chapter Outline
4.1 Memory
4.1.1 Operation of a Memory
4.2 Storage size
4.3 Addressing Data in Memory
4.3.1 Data Addressing
4.3.2 Segmented Memory Management
4.3.3 Program Execution Registers
4.4 Memory Enhancement
4.4.1 Wider memory path
4.4.2 Memory Interleaving
4.4.3 Cache Memory
4.5 Memory Management
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4.0 CPU-Memory
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4.1 Memory
4.1 Operation of a Memory
Instruction and data can be
retrieved from memory via an
interface between CPU &
memory.
The two registers used to
retrieve data and instruction
from memory are:
MAR: Holds the address
in memory which is open
for data access.
MDR : Holds the content
of memory that is
currently addressed by
MAR.
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4.1 Memory
4.1 Operation of a Memory
Both MAR and MDR served as the interface between CPU and memory.
The working of MAR and MDR.
Activation line
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4.1 Memory
4.1 Operation of a Memory
Example of MAR and MDR.
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4.2 Storage Size
The smallest and fundamental unit in computer is measure by bit.
Data stored in memory in byte basis.
There are other sizes available to facilitate data storage.
Term Length (bit) Length (Byte)
Nibble 4 -
Byte 8 1 = 20
Word 16 2 = 21
Doubleword 32 4 = 22
Quadword 64 8 = 23
Paragraph 128 16 = 24
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4.3 Addressing Data in Memory
4.3.1 Data Addressing
How data stored in memory?
❑ Computer memory consists of a sequence of storage cells.
❑ Each cell is identified in hardware and software by its memory
addresses of 20 bit basis.
❑ For a memory with n number of storage cells in memory, its addresses
are enumerated from 0 to n-1, to store a consecutive sequence of bytes
that represents a simple data value.
1 0 1 1 1 0 1 1
27 20
MSB LSB
= 8 bits
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4.3 Addressing Data in Memory
4.3.1 Data Addressing
How data stored in memory?
❑ The "value" of a digit is determined its value as a single digit and also
by the position it holds in the complete number, its "significance".
❑ These positions can be mapped to memory mainly in two ways:
increasing numeric significance with increasing memory addresses
(or increasing time), known as little-endian, and
decreasing numeric significance with increasing memory addresses
(or increasing time), known as big-endian.
Activity:
Use DEBUG program to check data stored in memory and registers
respectively.
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4.3 Addressing Data in Memory
4.3.1 Data Addressing
How data stored in memory?
Little endian order Big endian order
• LBS is stored at the first memory address. • MSB is stored at the first memory
• Reverse-byte sequence address
• E.g.: 102416 • Normal-byte sequence
• E.g.: 102416
Register Memory Register Memory
1016 2416 2416 1016 1016 2416 1016 2416
MSB LSB 00000H 00001H MSB LSB 00000H 00001H
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4.3 Addressing Data in Memory
4.3.2 Segmented Memory Management
Memory Segment
Memory segment are the special areas of
memory containing code, data and stack
information.
The operating system keep tracks of the
locations of individual program segment based
on segments.
There are 3 key types of memory segment:
Code segment : Hold machine
instructions.
Data segment : Hold programs’ defined
data and constants.
Stack segment : Hold local function
variables and parameters.
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4.3 Addressing Data in Memory
4.3.2 Segmented Memory Management
Segments and addressing Memory
❑ Real-address mode
The x86 processor can access 1,
048, 576 bytes (1MB) of memory Register
using 20 bit addresses in the
range of 00000H to FFFFFH.
AX
❑ Segmented memory
16 bits
All of the memory is divided into
64KByte units called segment.
20 bits (addresses)
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4.3 Addressing Data in Memory
4.3.2 Segmented Memory Management
Segmented Memory Map
50000H
40000H 1000:FFFF
30000H
20000H 1000:0250
0000-0250
10000H 1000:0000
00000H Segment:Offset address
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4.3 Addressing Data in Memory
4.3.2 Segmented Memory Management
Addressing scheme: How memory address is referred?
Absolute address (physical address)
Uses a 20 bit value that directly references a specific memory
location
Segment:offset address (logical address)
Combines the starting address of a segment with an offset
value
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4.3 Addressing Data in Memory
4.3.2 Segmented Memory Management
Absolute Address
Also known as linear address.
It is a 20 bit value that directly references a specific location in memory.
E.g.: 04A26H
00003H
00002H
00001H Absolute address
00000H
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4.3 Addressing Data in Memory
4.3.2 Segmented Memory Management
Segment Offset Address
Segment address is stored un segment register without last digit.
E.g.: 038E0H 038EH
Absolute address Segment address
Effectively, the 20-bit address is stored n the 16-bit segment register
Offset address is the distance in bytes from the segment address to
another location within the segment.
Offset address ranges from 0000H (010) to FFFFH (65,53510)
Each segment can be up to 64KB in size
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4.3 Addressing Data in Memory
4.3.2 Segmented Memory Management
20-bit Linier Address Calculation
To obtain actual / absolute address of memory location from
segment:offset address, the processors involves:
Step 1: Convert 16-bit segment address into 20-bit address.
Step 2: Add the offset address.
Absolute address = (16-bit segment address x 10H) + Offset address
E.g.: Given segment and offset address at 08F1:0100
Step 1: 08F1H x 10H = 08F10H
Step 2: + 0100H
09010H
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4.3 Addressing Data in Memory
4.3.3 Program Register
Registers are defined as high speed storage located inside the CPU.
It is used to store data temporarily.
In 8086:
All registers are 16-bit registers.
The general purpose registers can be accessed as either 8-bit or 16-bit
registers.
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4.3 Addressing Data in Memory
4.3.3 Program Register
Categories of register
Categories A.k.a Functions Bits registers
General Data registers Handle data 16 AX, BX, CX, DX
purpose movement and
register arithmetic 8 AH, AL, BH, BL, CH, CL,
computation DH, DL
Address Segment:offset Handle addressing 16 CS, DS, ES, SS
registers registers IP, BP, SP, SI, DI
Status Flag register Indicate computer 1 OF, DF, IF, TF, SF, ZF, AF,
registers status PF, CF
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4.3 Addressing Data in Memory
4.3.3 Program Register
General purpose registers
Registers Description
AX Accumulator Used for operations involving input / output and most
register arithmetic
BX Base register Used as an index to extend addressing and computation
Also used as DI and SI as a base register for special
addressing
CX Count Used to control the no. of times a LOOP instruction is
register repeated
Also support computations
DX Data register Input / output operations
Multiplication & division operations that involve large
value
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4.3 Addressing Data in Memory
4.3.3 Program Register
Address registers - Segment registers
Registers Description
CS Code segment register Hold the start address of code segment
DS Data segment register Hold the start address of data segment
ES Extra segment register Hold the start address of extra segment
SS Stack segment register Hold the start address of stack segment
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4.3 Addressing Data in Memory
4.3.3 Program Register
Address registers - Offset Registers
Registers Description
SI Source index Support string (character) handling operations
Associated with DS register
DI Destination index Support string (character) handling operations
Associated with ES register
IP Instruction Holds the address of next instruction that is to execute
pointer Associated with CS register
BP Base pointer Support parameter referencing via the stack
Associated with SS register
SP Stack pointer Holds the address of current word being processed in
the stack
Associated with SS register
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4.3 Addressing Data in Memory
4.3.3 Program Register
Address registers - Segment:Offset Registers
Registers Description
CS IP Provides the address of instruction to be fetched for execution
DS SI Provides the reference to a specific byte location in the data
segment
ES DI Used by some string operations to handle memory addressing
SS SP Provides the current words in the stack being addressed
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4.4 Memory Enhancement
4.3.3 Program Register
Status Registers
Registers Description
OF Overflow flag Indicates overflow of MSB after an arithmetic
operations.
Set when the result of a signed arithmetic operation is
too large / too small to fit into the destination
DF Direction flag Determines left / right direction for moving /
comparing string data
IF Interrupt flag Indicates that all external interrupts, are to be
processed / ignored
TF Trap frag Used for single stepping through a program
SF Sign flag Indicates arithmetic sign of the result after an
arithmetic operation
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4.3 Addressing Data in Memory
4.3.3 Program Register
Status Registers
Registers Description
ZF Zero flag Indicates that the result of an arithmetic / logical
operation is zero
AF Auxiliary flag Set when an arithmetic operation causes a carry
from bit3 to bit4 in an 8-bit operand
PF Parity flag Support error checking
Set when the result contain an even number of 1 bit
CF Carry flag Indicates a carry after an arithmetic operations.
Set when the result of an unsigned arithmetic
operation is too large to fit into the destination
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4.3 Addressing Data in Memory
4.3.3 Program Register
Status Registers
Flag name SET (1) Clear (0)
OF OV NV
DF DN UP
IF EI DI
SF NG PL
ZF ZE NZ
AF AC NA
PF PE PO
CF CY NC
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4.3 Addressing Data in Memory
4.3.3 Program Register
Registers
Categories Bits registers
General purpose 16 AX, BX, CX, DX
register 8 AH, AL, BH, BL, CH, CL, DH, DL
Address registers 16 CS, DS, ES, SS
IP, BP, SP, SI, DI
Status registers 1 OF, DF, IF, TF, SF, ZF, AF, PF, CF
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4.4 Memory Enhancement
Memory Enhancement
There are 3 key approaches that facilitate memory enhancement.
1. Wider path memory access
2. Memory interleaving
3. Cache memory
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4.4 Memory Enhancement
4.4.1 Wider Memory Path
Several bytes / words can be read/written between CPU & memory with
each access
It is widely used.
However, it increases the complexity in locating memory access.
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4.4 Memory Enhancement
4.4.2 Memory Interleaving
Divide memory into parts, for multiple access at the same time.
Each part has its own MAR and MDR.
Each part can be access independently.
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4.4 Memory Enhancement
4.4.3 Cache Memory
A small amount of high speed memory between CPU & main memory
It is invisible to programmer & cannot be directly addressed
Cache memory keeps a reproduction of data of memory
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4.4 Memory Enhancement
4.4.3 Cache Memory
Cache memory is organized into blocks.
Each block holds a tag which acts as directory to identify the
corresponding location of data in memory.
the case operation includes:
Cache controller: hardware that checks tags.
Cache line: Unit of transfer between storage and cache memory.
Hit ratio: Ration of hits out a total requests.
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4.4 Memory Enhancement
4.4.3 Cache Memory
Operation of cache memory. Cache
Hit
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4.4 Memory Enhancement
4.4.3 Cache Memory
Cache
Operation of cache memory. Miss
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4.5 Memory Management
4.5.1 Three Key Models
There are three key models
1. Single-user continuous scheme
2. Static Partition Scheme
3. Dynamic Partition Scheme
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4.5 Memory Management
4.5.1 Three Key Models
4.5.1.1 Single-user Continuous Scheme
Each program is loaded in its entirety into memory and is allocated as
much contiguous memory space as needed.
If program was too large - it couldn’t be executed.
Minimal amount of work done by Memory Manager.
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4.5 Memory Management
4.5.1 Three Key Models
4.5.1.2 Static Partition Scheme
Allows multiprogramming by using fixed partitions where one partition
for each job
The size of each partition remains static once the system is in operation.
Each partition can only be reconfigured when the computer system is
shut down, reconfigured and restarted.
The partition sizes are critical. If the partition sizes are too small,
larger jobs will be rejected. If partition sizes are too big, memory can be
wasted if a job does not occupy the entire partition.
Internal fragmentation is a problem. Internal fragmentation occurs when
there are unused memory spaces within the partition itself.
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4.5 Memory Management
4.5.1 Three Key Models
4.5.1.2 Static Partition Scheme
Job 3 must wait even though 70K of free space is available in Partition 1
where Job 1 only occupies 30K of the 100K available. The jobs are
allocated space on the basis of “first available partition of required size.”
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4.5 Memory Management
4.5.1 Three Key Models
4.5.1.3 Dynamic Partition Scheme
Available memory are kept in contiguous blocks and jobs are given only
as much memory as they request when loaded.
Improves memory use over fixed partitions.
Performance deteriorates as new jobs enter the system
Fragments of free memory are created between blocks of allocated
memory (external fragmentation).
First-fit: Allocate the first partition that is big enough.
Best-fit: Allocate the smallest partition that is big enough
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4.5 Memory Management
4.5.1 Three Key Models
4.5.1.3 Dynamic Partition Scheme
First Fit Best Fit Worst fit
Faster to implement Slower to implement because the entire free list table needs to
be searched before allocation can be made.
Algorithm is simple. Algorithm is complex because it needs to find smallest block of
memory into which the job can fit.
Memory list organized Memory list organized according Memory list organized
according to memory to memory size, smallest to according to memory size,
locations, low-order largest. largest to smallest.
May not be making Produces the smallest leftover Produces the largest
efficient use of memory partition. Make most efficient use leftover partition. Make
space. of memory. worst use of memory
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4.5 Memory Management
4.5.2 Dynamic Partition Scheme - Key Algorithms
4.5.2.1 First Fit
Given: First Fit
Job Memory Partition Partition Job Job Size Internal
requested Size Fragmentation
J1 10K P1 25K J1 10K 25K – 10K = 15K
J2 20K P2 20K J2 20K 20K – 20K = 0K
J3 30K P3 30K J3 30K 30K – 30K = 0K
J4 15K P4 35K J4 15K 35K – 15K = 20K
P5 15K
Total: 35K
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4.5 Memory Management
4.5.2 Dynamic Partition Scheme - Key Algorithms
4.5.2.2 Best Fit
Given: Best Fit
Job Memory Partition Partitio Job Job Internal
requested n Size Size Fragmentation
J1 10K P1 25K J4 15K 25K – 15K = 10K
J2 20K P2 20K J2 20K 20K – 20K = 0K
J3 30K P3 30K J3 30K 30K – 30K = 0K
J4 15K P4 35K
P5 15K J1 10K 15K – 10K = 5K
Total: 15K
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4.5 Memory Management
4.5.2 Dynamic Partition Scheme - Key Algorithms
4.5.2.3 Worst Fit
Given: Worst Fit
Job Memory Partition Partitio Job Job Internal
requested n Size Size Fragmentation
J1 10K P1 25K J4 15K 25K – 15K = 10K
J2 20K P2 20K
J3 30K P3 30K J2 20K 30K – 20K = 10K
J4 15K P4 35K J1 10K 35K – 10K = 25K
P5 15K
Total: 45K
J3 has to wait
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Chapter 4: Computer Memory
Self-review
4.1 Memory 4.5 Memory Management
4.1.1 Operation or Memory 4.5.1 Three Key Models
4.2 Storage size 4.5.1.1 Single User Contiguous Scheme
4.3 Addressing Data in Memory 4.5.1.2 Static Partition Scheme
4.3.1 Data Addressing 4.5.1.3 Dynamic Partition Scheme
4.3.2 Segmented Memory 4.5.2 Dynamic Partition Scheme - Key Algorithms
Management 4.5.2.1 First fit algorithm
4.3.3 Program Execution Registers 4.5.2.2 Best fit algorithm
4.4 Memory Enhancement 4.5.2.3 Worst fit algorithm
4.4.1 Wider memory path
4.4.2 Memory Interleaving
4.4.3 Cache Memory
4.5 Memory Management
4.5.1 Three Key Models
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