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26 March 2018 1439 رجب9
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IC Layout
Lecture 03
CMOS Layout Overview
Dr. Hesham A. Omran
Integrated Circuits Lab (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
This lecture is mainly based on “CMOS VLSI Design”, 4th edition, by N. Weste and D. Harris and
its accompanying lecture notes
CMOS Inverter
Ideally, there is no static (idle) power consumption
03: CMOS Layout 2
Layout vs Cross-Section
GND VDD
nMOS transistor pMOS transistor
substrate tap well tap
A
GND VDD
Y
p+ n+ n+ p+ p+ n+
n well
p substrate
well
03: CMOS Layout substrate tap 3
tap
Detailed Mask Views
Six masks
n well
1. N-well
2. Polysilicon
3. n+ diffusion Polysilicon
4. p+ diffusion
n+ Diffusion
5. Contact
6. Metal p+ Diffusion
The transistor is formed Contact
by the intersection of
polysilicon and diffusion
Metal
03: CMOS Layout 4
Layout Design Rules (DRs)
The contract between the designer and the process engineer
Same layer: min width and min spacing
Different layers: min spacing, min enclosure (overlap), and min
extension
[H. Kaeslin, 2008]
03: CMOS Layout 5
Layout DRs cont'd
Real-life layout DRs are very complicated
– Checked by a software CAD tool
– DRC: Design rule check
– Mentor Calibre is the industry standard DRC tool
– Checks the layout using a “rule file” (a.k.a. rule deck) and
generates a list of DRC errors
03: CMOS Layout 6
Layout DRs cont’d
Generally, the foundry will not accept any design with DRC errors
– All errors must be fixed
– Sometimes the errors are not real and can be ignored (you must
check with the foundry)
– In special cases, minor DRC errors can be accepted by the
foundry (but you must request an official DRC error waiver)
03: CMOS Layout 7
λ-Based Layout DRs
Simplified scalable conservative rules to get you started
Feature size f = 2l =distance between source and drain
– Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize layout design rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process
03: CMOS Layout 8
λ-Based Layout DRs cont'd
Simplified scalable conservative rules to get you started
Real-life DRs are in microns and are much more complex
03: CMOS Layout 9
Inverter Layout
Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
03: CMOS Layout 10
Gate Layout
Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
Line of diffusion style
– Simple and straightforward layout style for standard cells
– Four horizontal strips:
1. metal ground at the bottom
2. n-diffusion
3. p-diffusion
4. metal power at the top
– Polysilicon lines run vertically to form transistor gates
– Metal wires connect the transistors appropriately
03: CMOS Layout 11
Stick Diagrams
Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
Transistor = intersection of poly and diffusion
Note source and drain sharing
VDD VDD
A A B C
metal1
c
poly
ndiff
Y pdiff
Y
contact
GND GND
INV NAND3
03: CMOS Layout 12
Stick Diagrams cont'd
Metal1 GND rail at bottom
Horizontal N-diffusion and p-diffusion strips
Metal1 VDD rail at top
Vertical polysilicon gates
Metal1 makes connections
VDD VDD
A A B C
metal1
c
poly
ndiff
Y pdiff
Y
contact
GND GND
INV NAND3
03: CMOS Layout 13
Area Estimation (Using λ-Based DRs)
A wiring track (WT) is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
Transistors also consume one WT (if W is min)
Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one WT total equivalent to 3 WT (if W is min)
03: CMOS Layout 14
Area Estimation cont'd
Estimate area by counting wiring tracks (WT)
– Multiply by 8 to express in l
For the inverter: 2 WT by 5 WT 16 l by 40 l
For the NAND3: 4 WT by 5 WT 32 l by 40 l
VDD VDD
A A B C
metal1
c
poly
ndiff
Y pdiff
Y
contact
GND GND
INV NAND3
03: CMOS Layout 15
INV and NAND3 Cells
INV area: 16 l by 40 l exactly as estimated!
NAND3 area: 32 l by 40 l exactly as estimated!
Note source and drain sharing
Practically: Use MANY substrate and well taps
03: CMOS Layout 16
Example: O3AI
Estimate the cell width and height of O3AI cell using min size
transistors
VDD
A B C D
GND
03: CMOS Layout 17
Example: O3AI
Estimate the cell width and height of O3AI cell using min size
transistors
VDD
A B C D
6 tracks =
48 l
Y
GND
5 tracks =
40 l
03: CMOS Layout 18
Standard Cell Design
Standard cell design
methodology
– VDD and GND supply rails in
M1 (uniform cell height)
– nMOS at bottom and pMOS
at top (uniform well height)
– Adjacent gates should satisfy
design rules
– All gates include well and
substrate contacts
– Cells connected by abutment
03: CMOS Layout 19
Standard Cell Design cont’d
03: CMOS Layout 20
FinFET Layout
Fin width, height, and pitch
(Pfin) are fixed by technology
The channel width is
quantized
The FinFET orientation can
also be limited by DRs
03: CMOS Layout [King Liu, Berkeley] 21
Antenna Rules
Antenna effect:
– Metal wires charge up when it is plasma-etched
– May damage thin gate oxide (plasma-induced gate-oxide damage)
Antenna rules define max metal area to gate oxide area to avoid
damage
03: CMOS Layout 22
Antenna Rules cont'd
Ways to fix it:
– Jump to upper metal layer just before the gate
– Add a reverse-biased diode (bleeds off the charges during the
high-temperature plasma-etch process)
• D/S diffusion is already a reverse-biased diode (if M1 is used)
03: CMOS Layout 23
Layer Density Rules
Each layer must have adequate density to ensure uniform etching
and proper CMP
A metal layer may have to satisfy minimum density (e.g., 30%) and
maximum density (e.g., 70%)
There are both global (whole chip) and local (e.g., 100µmx100µm
area) density rules
If not already satisfied by the design dummy structures (and holes)
must be added to fix the errors
Foundries usually provide a “metal-fill” script to add dummy
structures (and holes) automatically
– May add parasitic capacitances or cause mismatch
– Should be disabled over sensitive analog circuitry (by using “fill-
stop” layout layer)
03: CMOS Layout 24
Metal Slotting Rules
Wide metal wires are usually used for global
wires (e.g., power routing) to decrease
resistance
Slots must be added parallel to the current flow
to provide stress relief and ensure proper
fabrication
Foundries usually provide a script to automate
this process
03: CMOS Layout 25
Latchup
Ordinarily, both parasitic bipolar transistors are OFF.
If substantial current flows in the substrate:
– Vsub turning ON the npn transistor
– Vwell turning ON the pnp-transistor
A positive feedback loop is triggered with a large current flowing
between VDD and GND
Find the mistake
03: CMOS Layout 26
Latchup
Latchup prevention is easily accomplished
by minimizing Rsub and Rwell
– Use MANY substrate/well taps close to
each transistor
I/O pads are more prone to latchup
because external voltages can ring below
GND or above VDD
– Guard rings should be used (a low
resistance path to collect stray currents)
Latchup is not important for:
– SOI processes (no parasitic BJT)
– DSM nodes with VDD < 1.4 (no enough
voltage to turn on two BJTs)
03: CMOS Layout 27
Transistor Layout
The transistor is formed by the
intersection of polysilicon and
diffusion
Add GOOD contacts to drain
and source
Add GOOD and NEARBY
substrate/well contacts.
OK
BAD
03: CMOS Layout [F. Maloberti, Layout of Analog CMOS IC] 28
Multiple or Single Contact/Via?
Curvature in the metal layer can cause fractures
03: CMOS Layout [F. Maloberti, Layout of Analog CMOS IC] 29
Multi-finger Transistor Layout
Analog transistors often have large W/L ratio
Multi-finger layout is commonly used
– Compact layout
– Smaller parasitic capacitances
– Smaller gate resistance
03: CMOS Layout [F. Maloberti, Layout of Analog CMOS IC] 30
Multi-finger Transistor Layout
03: CMOS Layout [www.eda-utilities.com] 31
Multi-finger Transistor Layout
Analog transistors often have large W/L ratio
Multi-finger layout is commonly used
– Compact layout
– Smaller parasitic capacitances
– Smaller gate resistance
03: CMOS Layout [F. Maloberti, Layout of Analog CMOS IC] 32
Multi-finger Options
Usually use even no. of fingers with source ending
– Decrease drain capacitance
– Also easier if the source is to be connected to bulk (gnd)
But may need different combinations when stacking different
transistors (more on this later)
03: CMOS Layout [F. Maloberti, Layout of Analog CMOS IC] 33
Additional Topics
Design and layout in FD-SOI 22nm technology
– https://www.globalfoundries.com/resources/technical-
webinar-series/analog-design-workshop-22fdx-22nm-fd-soi-
technology-part-one
– https://www.globalfoundries.com/resources/technical-
webinar-series/analog-design-workshop-22fdx-22nm-fd-soi-
technology-part-two
– https://www.globalfoundries.com/resources/technical-
webinar-series/top-5-design-guidelines-successfully-
implement-22fdx-fd-soi-technology
03: CMOS Layout 34
Thank you!
03: CMOS Layout 35
