es EAIRGCHILD ee SEMICONDUCTOR? UC3842/UC3843/UC3844/UC3845 SMPS Controller www airchildsemi.com Features Description + Low Stat up Current ‘The UCSSAZ/UCSB4S/UCSS44/UC38A5 are Sxed + Maxissam Duty C ‘requenycurrentamade PWM controller. They ar specially + UVLO With Hyse designed for Off-Line and DC to DC converter applications + Operating Frequency up to SOOKE with minimum extemal components. These integrated circuits featue a trimmed oscillator for precise duty cycle control, temperature compensated reference, high grin error amplifier, current sensing comparator and a high current totempole output for driving a Power MOSFET. The UC3842 and UC3844 have UVLO thresholds of 16V (on) and 10V (off). The UC3843 and UC3845 are 8.$V(on) and 7.99 (ofl). The UC3842 and UC3843 ean operate within 100% duty eyele. The UC3844 and UC3845 ve duty cycle. er 8SOP fF £ : : 140° Internal Block Diagram ‘oO = oma) Fs a = | 2. {NORMALLY aDIP!SOP PIN NO DIS SOP BING, TOGGLE FLIP FLOP USED ONLY IN C244, UC3E45 Rev. 10.1 (©2002 Farha Semiconductor Coxporatoncseda1ucseesucseasucsees Absolute Maximum Ratings Parameter ‘Symbol Value Unit ‘Supply Voltage Vee 30 Vv Output Current 10 a a “Analog inputs (Pin 2.3) Viana) “031063 Vv Error Amp Output Sink Current TsINK (EA) 10 mA Power Dissipation at Tas25°C (@DIP) PoiNotei,2) 7200 mW Power Dissipation at Taz25°C (8SOP) PoiNotei,2) 460 mi Power Dissipation at Tas25°C (1450P) Po(Notet,2) 680 mi Storage Temperature Range TsT6 65 ~ +160 °c Lead Temperature (Soldering, 10see) TLEAD $300 *C Note: 1. Board Thickness 1.6mm, Soard Dimension 75.2mm -114.3mm, (Reference EIA / JSEDS1-3, 51-7) 2.Do not exceeed Pp and SOA (Safe Operation Ares) Power Dissipation Curve 1200 = 1090 3 700 AGENT TEMPERATURE (©) Thermal Data Characteristic Symbol SDP | 8SOP | 14S0P | Unit Thermal Resistance Junction-ambient | Rtn-amb(ax) | 100 265 180 ecw Pin Array sovpssor =O fe H~ucses2iucssestucsessiucseas Electrical Characteristics (Veo#18V, RT=10k0, C7=3.3nF, Tas 0°C to +70°C, unless otherwise specified) Parameter Symbol Conditions | Min. | Typ. | Max. | Unit REFERENCE SECTION Reference Output Voltage | VaeF_| Tu= 25°C, REF = ima 480 | 500 [S10] V Line Regulation avrer_| 12VsVec 5257 ~ [6 | 20 | wv Load Regulation ‘AVREF | ImA gIner = 20mA = [6 | 28 | nv Short Creuit Output Current | Ise | Tas 25°C = [106 | 186 [ ma OSCILLATOR SECTION Oseilation Frequency t_| t=28e a | 2 | | we vane ‘Change with afiVee | 12V Voc s25V - |oos} 1 | % Oscillator Amplitude vese : [16 |= [Ver ERROR AMPLIFIER SECTION Input Bias Current Teas 5 ~ [ot] 2 pA input Voltage Viera) | Vpn = 250 2az | 250 [258 | V Open Loop Voltage Gain Gio | 2V8V0s4V Noted) e|o|- | sé Power Supply Rejection Ratio| PSRR | 12V/s Voc = 26V (Noted) eo | 70 | - | ® Output Sink Curent TsiN | Vpina = 27V. Vein = 1.17 2 [7 [= [ma Output Souree Current TsouRce | Vpna =2.3. Veit = 5V 8 | a0] - | mA High Output Votage Vow | Vong =23V.RL=16kQtGND | 5 | 6 | - | V Low Output Votage Vou | Vpina=27V.Ri=1&kQtPnd | - | 08 | ii | V ‘CURRENT SENSE SECTION Gain Gy _| (ete 182) ze | 3 [318] VW Maximart Input Signal VawaX) | Vpint = SViNOte 1) os] t [tt] v Power Supply Rejection Ratio] PSRR | 12V Voc #26V (Note 7.3) ~ [70 | - | Input Bias Current Teas 5 ~ [3 | a0 [=A ‘OUTPUT SECTION Vou > [008] 04 | Vv Low Output Voltage Tsink = 200mA 7 | i4 [22 |v High Output Votage Vou LISOURGE = 20ma @ | Bs[ - [Vv TsouRcE = 200mA 2 [0] - |v ise Time i | Ty=25°0, CLs inF Note 3) =| 4 | 180 | as Fall Time te | Tu= 25°C, CL= tn (Note 3) > [38 | 180 | ns UNDER-VOLTAGE LOCKOUT SECTION Start Threshold wer) |UOSeeaCRBAS 748 | 160 | 78] V UcaeasUC3E45 76 | 84 | 90 | Vv Min, Operating eREBE | ona UEBECDUCRBAS as | 100 | 115 | Vv (After Turn On) UC3843/UC3844 70 | 76 | 82 | Vvcsea21ucseeaucseaarucsees Electrical Characteristics (continues) (Veo#18V, RT=10k0, C7=3.3nF, Tas 0°C to +70°C, unless otherwise specified) Parameter Symbol Conditions Min. | Typ. | Max. | Unit PWM SECTION Max Duty Cyele Diwax | UC3842/UC3843 | 7 | 10] % Diwax) | UC3B4aUC3E45 a Min. Duty Cycle Destiny : - -[o[* ‘TOTAL STANDBY CURRENT ‘Start-Up Current st : = [045] 1 | mA ‘Operating Supply Current TecioPR) | Vpina=Vpin2=ON ~ [4 [7 [ma Zener Voltage V2__| lec = 25mA 3 | 3 | - [Vv Adjust Vcc above the stat threshould before setting at 15V Note: 1. Parameter measured at trip point of latch 2 Gain defined as: aN, = Mont 9 < Vpins < a= atl 0s Vpns s0.8v 3. These parameters, although guaranteed, are not 100 tested in production. Figure 1. Open Loop Test circult High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors stiould be connected close to pin $ in a sinale point around, The transistor and KO potentiometer are used to sample the oscillator wavefom and apply an adjustable ramp to pin 3,ucses2iucssestucsessiucseas Figure 2. Under Voltage Lockout During Under-Voltage Lock-Out, the output driver is biased toa high impedance state. Pin 6 should be shunted to ground with 1 bleeder resistor to prevent activating the power switeh with output leakage current. +=h—© = Figure 8. Error Amp Configuration Figure 4, Current Sense Circuit ‘Peak current (Is) is determined by the formula: Ig(Maxy= 19% A small RC filter may be required to suppress switch transients,csea21ucseeaucseaarucsees 6 11+ TLL wre exon Figure 5. Oscillator Waveforms and Maximum Duty Cycle Oscillator timing eapaciter, CT, is charged by VREF through RT and discharged by an internal current source. During the discharge time, the internal clock signal blanks the output to the low state. Selection of RT and Cr therefore determines both oscillator frequency and maximum duty cycle, Charge and discharge times are determined by the formulas 55RrCr, {o.0083R,-27} "C0063; —4 RCA 18 RT» skOt- ge Foret aKa ge 1 8 Figure 6. Oscillator Dead Time & Frequency (Deadtime vs Cr RT > $k) “2 suena Of ‘snurocwn O— | tocumme Figure 8, Shutdown Techniquesucses2iucssestucsessiucseas Shutdown of the UC3842 can be accomplished in 3 above IV or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The ‘PWM latch is reset dominant so thatthe output will remain Tow until the next clock eyele after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally Iatched shutdown may be accomplished by adding an SCR which will be reset by eycling Vcc below the lower UVLO threshold. At this point the reference tums of, allowing the SCR to reset vessaverees Figure 8. Slope Compensation ‘A fraction ofthe oscillator ramp can be resstively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over S0¥, Note that capacitor, CT, forms a filler with R2 to suppress the leading edge switch spikes. “A : i i. “Temperature °C) “Temperature (°C) Figure 10, Temperature Drift (Vref) Figure 11, Temperature Drift (ist) “Temperature (°C) Figure 12, Temperature Drift (lec)cseda1ucseesucseasucsees Mechanical Dimensions Package 8-DIP 1.524 10.10 (0.060 10.008 508 3.30020 0.200 MAX 0130-0012 762 0.300 3.40 033 0.134 -0000 oor MINucses2iucssestucsessiucseas Mechanical Dimensions (continued) Package 8-SOP 01-025 vin tes-0x 1008-0 004 Dt 0005 6.002220 0206 :00%8 or MAK os 3.95 2020 WAKO 0 MAS. 008 32 % | 0.225 | S 0.50 1020 020 90:csea21ucseeaucseaarucsees Mechanical Dimensions (continued) Package 14-SOP 00s __ MIN 9.003 188.010 - 0.061 =0.004 2 1 oe t zB) af eelkg eg cg (idee 5e| Se a § 1 thre 120 ag aor MAX clo 888 ols al|s ge 2|8 ag 0.60 +020 008, 40ucses2iucssestucsessiucseas Ordering Information Product Number Package Operating Temperature UC3842N UC3843N Ucaa4aN UC3845N 80IP UC384201 UC384301 UG3844D1 UC3845D7 SOP uc38420 Uc38430 uo384a0 UC3845D 14-S0P 0~+70°C "cseaaucseesucseasucsees DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY, LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN, NEITHER BOBS IT CONVEY ANY LIGENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS, LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. AS used herein: 1. Lie support cevices or systems are devices or systems 2._Acriieal component in any component of @ if support Wien, (a) are intended for surgical implant into tne Dod, ‘evice or system whose fallure to perform can be. ‘r (b) support or sustain ife, and (c) whose failure to reasonably expected to cause the fallure ofthe Ife support Perform when property used In accordance with vice or system, orto affect its safety or efectiveness Instructions for use provides inthe labeling, can be reasonably expected to resut ina signicantinury ofthe ww orenasemi com