intro to BJT

Bias
•

used in amplification a
switching operations .
Forward : FB

'

Emitter -

Base
-

collector CNPN Or PNP ) Reverse Bias : RB

C C

Transistor
transfers from low to
high
'
:

B B '
,
resistance
E E
Junction 1 → ( E -
B )
NPN PNP Junction 2 → ( C -

B)

Junction 1 Junction 2 mode

FB RB Active C
Amplified )
FB FB saturation 10N )
1 OFF )
RB RB cutoff
RB FB Invented

IE IB 1-
Ic Ic IE ✗ :
Amplification Factor
p=÷
= = ✗

p :
very sensitive to ✗
✗ < I

501131400
common Emitter
configuration 1
.

↳
BJT acts as an
amplifier
current amplifier
↳ EB Forward Bias A CB Reverse Bias

IE =
Ict IB

VB VE And Vc VB
Ic ✗
IE ICBO % > >
= + .
:

/
%
C ( µ,

-
:
Ic = ✗ ( Ict IB ) +
ICBO IB Icizo : Revelle saturation
>

Ulhklht
i.
Ic
=÷✗ {
✗
IB +
ICBO } B.
( p,
, =
! ve ,
IB :

input ueeehent
UBE p£ E IN )
Ic :
Output current
✗
IE
Ic PIB (
Pti ) Icpso VBE voltage
+
Input
= :

±
=
PIB +
Ice'o° ground Vee :
Output voltage

Ic =
PIB . :
p= current amplification factor

input-output characteristics

VCE =
VCB + VBE

IB ( MA ) Ic ( MA )
a a
←
VCE Active
increases Region
÷ IB
a In increasing
÷.
region

ÑBE ( V) .

input than
Output Chan
 model capacitor circuit
small signal Dc open
:
low freq
' .

Ac short circuit
i'
it "
, oe
By
1
Gyro
gmvtt VBE = 0.6

Vt, { MIT t'

UTH =
VB = 1^737

-
1- i.
VE =
?

=
E
VB -
VE = 0.6

0.6 1 139 V
VE =
VB - = .

gm =
trans conductance VCE = 5 Ve -

VE = 5

i.
Vc =
5+1.137 =
6.137 V.

integrated circuit 11C ) contains different components critic ) fabricated on a single

silicon wafer .

Transistor amplifier
•

as an

↳ CE mode
↳
Differential amplifier :
Amplifies the difference between 2 input signals .

i/ P measured
single ended
d
↳ : 0 /P Wrt
ground
↳
Advantage of differential input : -
eliminates common mode noise
-

does not need coupling capacitors

0 VCC
In DC
Analysis ,
Vin , =
Vinz =
0 .

- :
-

UBE -

IEE RE +
VEE = 0

IEzE_
✗
✗ IEE " ✓

2- i.
IEE =
VEE -

VBE
Re
§ { Re RE
V01 V. 02

Vc Vcc
.
:
+ =
Icrc
- -

v0
-

Vcc Rc
IEzE_
=
-
✗

Ñinz
•

Ving > L

( AC ) ( AC )

I¥-
" "

IEE mode signal

•

Rejects common
-2
( OV)
IEE Differential in
''

voltage must be my
'

to use

{•
RE this circuit as an amplifier

VEE
-

Ic ✓
☐ =
Gm ☐
BE

gain in differential mode =

-

9m Re

Amplifier fundamentals COP AMP )

-

high gain direct coupled amplifier ( multi stage

is ) which performs
↳ a
it -

mathematical operations ( :-) on signals +

,
-

,
✗
,
.

↳ it is
very useful in
signal processing
to
↳
can amplify both AC and DC signal .

run •

↳
operating 0 106 He
range
:
to .

↳
it is an example of voltage controlled voltage source .

I
AOLVD

•
 •

symbolic representation
+
Vccl collector Neel =
1- VEE / :
balanced power supply system
if
•

supply
voltage ) else unbalanced
inverting
Terminal
-

•
Output when inverting terminal
input at a non -

Non inverting t
inventing terminal is grounded output has
.

Terminal ,

180° phase shift

-

TEE 1 emitter supply

voltage )

Aoi :
open loop gain .
Vd =

Difference voltage =
UNI -

VI
Vout
Vout
=
AOL '
Vd ^

Vsat -

↳ -

VEE E Vout t Vcc Always

r n >
Vin
Vsat Vsat
Usat
-

is I
ideal AOL 00
Vout
•

For OPAMP = i.
AT
.

,
AOL
Ri = D Ro = 0
,
-

Usat
MM Vout
UNI
•

+ < > { > < >

Ro
T "
linear zone saturation zone

Vd Ri { I Avd

VI.
±

linear region is small add feedback to the AMP

very
•

of Thus OP
Range we
.
.

↳
Negative feedback
:
connect to
inverting terminal

tm%_ Vout =
Aoi Ud

r,
| ( V✗=0) virtual ground
:
Um , =
VI =
0 as Vd is
very small .

Vin >¥m is entering

-

current the
↳ Ut
No
op-amp

It I =
If
.

. .
,

Vin =
Vx -

Vout
R
Rf
inventing
'

op Amp
tout Vout_ RI Acl
Vinny
i. = = - =

Rf Vin Ri

Vin Vino Ri Ri 2in Ri

Input impedance :
= = = . =

Jin Vin -
Vx

±nit_
Ri
| Vx =
Ri
Ri Rt
. Violet

¥m¥0
+
Vin
.
+
-

wont vout
Vx -
-

: Vx = Vin
-1in
• qpy Uout
Vin
•
Vx Vin = Ri .

{ Ri Ri +
Rf
Non -

inventing op-Amp =

woot A"
, ,
= it
Rt =

Vin RT

Vin Practically high )

Input impedance
Vigny
= = =D 1 very
t
This is Why beneficial
 follower )
Amp a
Buffer 1 Voltage
•

op as

Vout . -
Due to virtual ground ,
Vin =
Uout .

+ Volt
Vin 2in =D

inverting summing Amplifier

•

Rt
Vx = O l due to virtual ground )
Mr

Ita
Il t
Iz +
Iz =
If
V, it '
wins
%✗ I +
V1 V1 Volt
-

+ =
-

v2 Fanfan
V0 Ut Rl R2 Rz
v >
Is
mine It Rf
,

RI
R÷z f
Vout V2 +
V3
13¥
+
i. =
V1
-

, R2
- -

changing the ratios

( Rt / Ri ) perform addition scaling &
operation
By averaging
↳ we can .

, .

↳ Provide DC
offset
Digital Analog conversion
↳ to

interference between diff

↳
No .

voltage sources

inventing summing amplifier

'

Non -

Wftu Vout = I +
RI Vt
Ra
mini vt
± To
find superposition
-

we use

wire •V+ + bout

v, •

wrk
V2
• .

1114 Vt + +
+
+
V1 R2 V1 v2 Ri V2 i. V, + V,
V2
=

Taking
= =
-_ 0
,

Rit Rz R +
Rz
,

i. Vt Rzvit Ri V2 Let R , =Rz= R And Ra

Rf
= =

Rit R2

Vout Vit V2
Vout (1+1) I V1 + V2
)
=
then = :

↳ individual voltage sources are not isolated writ each other

↳ As number
of voltage sources increase ,
complexity also increases .

summing amplifier is preferred

i.
inventing .

op
-

Amp as Differential Amplifier

win Vout " V2

R÷ +1¥
= - ' + '

nii
v. -

Vt =
Rz_ .

V2
V2
+ Vout Rzt Ri

Xiu i.
Vout R2_ V2
R÷
= - -
V1 + '

, Ri
Ri
v mm
Vout ( V2 V1 )
12¥
-
=
,
-

Rt
+ Vout
V2
£132
 input impedance : 212 , Culley love ) .
i. we can avoid loading source

by using buffers .

instru .

amplifier has high gain &

high 2in .

5kr
find Vout
Eg .

mm
.

V01 (2) 10 V
-5g
+15W = = -

Ikr

2V MM -

Ikr
+ Vout Vt (3)
3v V02
(+5-1) =/ 6)
( ÷+ )
=

-15W

£8192
,

=
18×8 = 16 V
a-
Vout V0 , V02 ¥
: =
•
= +

resistor d 1=1211
Now
replace 8hr
by 4 Kr
biasing voltage .

Find Vout .

(2)
5g
V0 , = - =
-1011

V02 Vt (6) (
Itsy ) 4¥51 ) (6) (4) 2411
(
= = = =

i.
Nowt =
V01 +
V02 =
14 V Which is 7 12 11 .
i.
Uout =

12¥

Eg .

Ra innit Find Vout .

iii. First
iii. consider 2V 3 U
only
a

1+15
V .

: mm
{
ZV

( 1^2
"° ' + 3 su
f-
"
,
• =
I
-
'
= -

m-É+
Viau
3.
vout

2 { {
"5 "

1119 V02 Vt
( 1)
su man ikr
= +

1- Ra

Ra =
Ikr 11 Ikr =
0.5 KR

? vt =

4V #É →
Vt 4 -
I
,
t
Iz -
5 =D =) Iz =
I
,
+ I

§ -11+1=2 4 Il (1-11-1-2)=0 Iz 4-2-1

' - - =
,
b- V
¥ ,
,
I , +1--4-2-1 31 =3 I =
I
± , , ,

7-2=2 .

4T
-

Vt = I
,tIz =
3 V
I

T~
)
" 9 V
V02 ( (I 1-
it
1- 3 2) 3
= =
=
°

5
0.5

i. V
Vout =
4
=

op Amp as Integrator
•
-

Vi÷
- i
Iin =
Ic =
Vin O =

i
-
-

R
^
Ic

Vin ¥ ;nÑn ;
-

Ic =
educ
F-
( Q = CV ) = C -

A-
d lo -
Vout ) = -

Cdvout

I n
but
It

fvinctldt Ving cdvout Vout

i. = - i. =

It
gain
1dB ) Practical
ft to
.

1-
2¥
=
: =
:
-
Re
RT ! ,
21T
Rfc ,

ti to f
?⃝
 Vin Av l at f=O Au AOL
Vout
¥
✗c =

# ,¥
= = i = -
-
=
,
.

a ,
21T£ .
RC

Practical Integrator using

•

op Amp
-

RF
nm

:
Av at g- =0 =
RI
-
'
-

i -

R
^
Ic
R

¥;nm integration fin 710th fin

10.2¥
Vin "
; For
-

proper ,

,
Vout
It
.

Amp differentiator
•

op as a

Rt
cdvin-rm-c.tn
cd¥ Ic = =

dt
If
11 dvin
%Y÷
Vin g-
-
= -
i . Vout = -

Rg - C -

devout
Vout
It

=
-

R .
Vin Av = -
21T
f. Rf -

C fo = I C
youn
'

= 0 dB )
✗c 21T c
Rp .

↳
very sensitive to
high freq noise 2in = Xc

niner c
-

^
It →
Practical Differentiator Zin = R2 + ✗ i
mtt-
Av Rt ( At high freq )
-

= -

o
✓
in
It Vout Ñ
Cf
1/
Rf ( ti )
fi £2 tz
21¥ Cf
>
1- cutoff freq
=
=
-
nm -

^
If 21T RC
R C

mtt- ± min (f) , fz )

fin
-

0
✓
Vout
in
It 10

Frequency response &

Gain Bandwidth Product

^
-
20dB / decade gain ✗
freq = constant =
unity gain g- req =
fu
: g-
gain Act : closed
"
1dB)
!
" °P
Gain
↳
inventing Ace fu
: ^
Non op-amp fu
=

F
"
t' t
inventing op-amp
:
fu =
11+1 Aul ) ^fu→ cutoff treat
unity gain
frequency
↳ is
gain constant upto cutoff freq
""
fcc.net =

fee ^
12 ) -1 ; n =
no .

of Op amps cascaded

•
slew rate

maximum which CV / µs )
↳ rate at Olp of op-amp can change
↳ For LMTHI -

0.5 V / US
↳ it
depends on how fast the internal compensation capacitor changes on

discharges
 ie due dVc_
÷
i.
=
c. = =
sieve rate
It dt

↳
olp will get distorted if i/ P is changing faster than the slew rate .

Vlt ) =
Um sin ( wt )
du Um
÷ Lwt ) 21T£
i. =
Vmw cos . :
slew rate 3 i. SR 3 .

F-
max

↳ Power Bandwidth = slew rate

21T -

Vm

IOV

Eg .
slew rate =
2 V / µs i/ P =
( 1kHz -
1MHz )
find É
trey such that

Otp is triangulate wane with peak voltage of

4V .

Sol reaches UV in 2µs

-

op amp
T f- 250 kHz
i.
4µs
= =

common mode Rejection Ratio

•

Vt

%÷m
Acm = < 1

Venin + Vout =
Vocm
V
-

A&m
In
general case , Vout =
Ad
-

Vd
+
Acm -

Vem CMRR =
( closed loop )

-
wit -

EG .
R ,
^
If
• ME
n
Ri 1 KR 10 KR
-

O
=
, Rz =

Vd ↳
+ Vout
CMRR 90 dB
-

§
=
,
pn ,
✓
n ±
Rz Vd =
5mV at 1kHz , Un
=
2mV at 50 HZ

Vout V1 ) )
R÷ R¥ )
=
( V2
- =
( Vd =
50mV I 1kHz
,

Rz / Ri
)
31623 Acm 10
Ad_
CMRR
20kg ( AI
= =
= =

a ,m Acm 31623 -31623

Acm VCM
z÷yz
Vocm mV
i. = = 2 =
0.63µV ( 50 H2 )
. •

will not able isupress noise

generally op-amp be to
high fulq .

input offset voltage

•

+
Vcc

-
Vd
↳ Due to
difference b/w biasing voltage of transistors
÷ + ↳
so we apply Vd at input so that Uout = 0 .

V
offset
-

± vd MV
µV
:
to
few .

Vcc ↳
This Leads in Vout When
error
applying
-

to Vin .

we can also use DC

offset voltage
=
Odio µv/°c
offset null
Drift with temp
OT

Uce
 •

input Bias current a

input offset current

1-
Vcc
Bias Ibt Irs
current
10µA )
+
1B = UP = -

C
FA
IBT .
> + 2

V
I
>
IB offset
-

los =
yp offset current =
I IB+ -

IB -

Vcc

For
inverting amp , Vernor =
IB •

Rf general V00
=
Ios ✗
Rf
-

-
,

Rc =
Rill Rf
±
Vio →
input offset voltage

same formula for both

inverting & non -

inverting
configurations .

Vout =
V0 ± V00

op
-

Amp solved Examples

VI
ltg.PE
It
Z2_ It

12¥
= =
=

2
Vin ,

-22 _R3_ _Rz_

Vq÷
= = =

I
(¥ )
Rztlc that

j.io?a.YE-i V0jft-n- (+wR1-,)(j-wRp3Yf-Ji)-

"' =

hut

liwlt Rill -

Rzc ) =
-

rcjwl -
pic = -

j 4) ( jwrzc + 1) Rcjwl + L

Q2 .

considering one
voltage source at a time ,

( V1 ) shorted
3÷
V01 = -

( as 2R
gets )

= -

3 V1

=/ %÷R , } ( 3R✗3_)Y 11¥

+ +
V02 V2 = =

2R

i. Vout =
-34 +
V2
11
 Vt
(
Volt = It
Rf_
vt ✓
+

• •
Rt

3dB freq cutoff

I
freq
= =

21T ✗ 10 Kr ✗
0.1µF
=
159.1 H2

VA = O

-VB_ Ups Vin

Yi÷
= = -

B
•
, LOKI

V¥- VB-Vout_ Yong

+ = -

;
10 Kr

VB 110hr) + VB -
Nowt
= -

UB
-r

Volt
VBp-
LIOKR ) t
2VB =

Vogt
Vout Vout
¥}
Uns 2
{ In
12
2 +
= = + = =

Vin
2+10 12 KR
In
= =
10 R= 1
a-

12211123 =
Rf
"
> is Vout =
_Rf_ = -
( Rzll Rz )
;

Tin Ri Ri
BI >

Q .
GBW =
1MHz .
When
gain =
20dB ,
BW =
?
i.
2010g be = 20 G =
10 o ! BW = 1MHz
To
= 0.1 MHz ( for non -

inverting )

inventing BW

yµ?÷
for op-amp ,
=
.

Q .
Steele rate =

14µs .

gain of 40dB .

fin
=
20kHz without distortion .

Find Max .

acceptable input level .

Sol .
Let Vin =
Um sin ( wt )

106 7 ) Lwt )
dVi¥
SR 7 Um 1W cos

Um .
21T .
(20×103) = 106
Vm =
7.9577 V

Volt =

gain
=
100 i.
Vin =
Um_ Vin =

79.5m£
Vin 100
 R2 11 RL
Vi -
Vt = Vt -
Vout . :
Vi -
Vt =
Ut -
Wont
•V+ Ri Ri Vout + Vin =
2V+
Vt
¥ It Vout
+ -
= 0
Vt
• , RL R2

Vptp
• hut -

Vout = -
Vin = -

IL
Ii
¥ R2
I ,
= -

Vin / R2 .

I
,
=
Iz =
20mA = 10 mA
2-

V0 =
I 1250) (1+8) -
I
,
1250 ) ( 1- 8)
,
20mA
< = I, 1250 )
{1+8-1+8}
Iii ✓ Ia = 10mA .
250 • 28 ( f = 0.05 )
-
Iz MA
20
IV
> •
=
250 mV
?
<

I ,
✓
20mA 20mA
¥
=

Vout =
Aoi ^
IV

=
AOL
short Vout
-

=D
+
,
IV
2hr
But valet limited
° ? =

; Vsat
.

,
by
is Vout =
12 V

+7¥ )
VB
-1,2¥
rout = . Vin + '

= -
Vin +
2UB
A
•

VB
,¥+g
B. = .
Vin

{ at } 10
[ ]
Vin
2¥Y÷
i. rout Vin l
±
+ < <
= =
i =
- -
-

ctr ✗ ✗ et R

a×c¥IR_ =¥÷
✗ c=
_÷c i r
i.
i 1- = = - -

, jwc

¥
+ R

=Ij_+Rr÷
= i -

jwrc ,

I +
jwrc

'
Of '
C- WRC ) tan ( WRC )
-

i.
tan
-

< = -

' '
( WRC ) tan ( WRC )
-

tan
-

- -
=

'
2/0=2 tan ( )
-

i. WRC
 comparator
•

( Vt U ) Vt Vout Usat
- -

Vout Aoi When > v +

^ =
= -
i.
,
.

otherwise Vout = -

Vsat
rise time
↳ it has low
propagation delay a
fast and fall

Instrumentation Amplifier
•

R2

)
(
Vout VA V13
R÷
✓ =
it
2R5_ ( -

B I
R
RG
-

, R ,

vo•ut
12¥ =R÷
Ra ,
+ Assume Rs =
RG And
R3 ,
Ry

wa I
%
=
Vcm will not
get amplified .

comparator
•

input +
In open loop ,

but Vout Aoi ( input Ref )

=
-

^
-

Ref i.
Vout =
± Vsat
non -

inventing
window comparator :
Vout = 2
; Vi Evin £ UH
↳ not immune =
0 otherwise
They are :

to noise

•
schmitt Trigger c
comparator with Hystehis)

VUT :
threshold Vit whelk threshold
upper
:
,

Vin Vout
Vout =
1 ; once Vin > VUT
= 0 : once Vin < Un
} inventing
non

↳ Provides noise immunity in the bandwidth VLT to VUT

↳
Hysteresis voltage
=
VUT VLT
-

→
non -

inventing R2
Voy = -

Ri .
Ur
R2

Ñh VLT = -

RI
.
VH
Vin +
'

R2
-

Vout
1-

R2
Vu, = RI •
VH Vin > VUT :
Uout =
UL
R, R' + R2
MM +
Vin <
VLT :
Vouet =
UH
±
VLT RI VL
Ilysm%
=

VUT VLT
° -

=
-

Volt
Vin pn , + my

inventing schmitt trigger

 Questions on
comparator & Schmitt trigger
•

Q1 .
T = 20ms

Ton for
5ms 25%
duty cycle
=

slope =
51 = IV / Ms
5ms

i.
At 2.5ms ,
Vout =
2.5 V
i. U 2.5 V
ref
=

I V1 )
Riyal
Q2 ULT UH -20 ) 1
Ry
VUT = =
-

=
-
- -
.

i. R, = I KR

→
non
inventing schmitt trigger

03 .
inventing schmitt trigger
when Vout = +15 V
,
Vt =
Voy

Vio Ut
ut -
z t -
15 = 0 Vt =
7 V

IOKR 7 V
b- KI - :
Vu -1 =

ut Vt L ) Vt -3N
When Vollt =
-15N '
-
3 + - -
15 =O = i.
VLT = -

3V
¥ IOKR

Q4 .
→
won inventing Schmitt trigger
UH =
10 V
, VL= -10 V
, Vu -1 =
2 V , VLT =
-3 V

ut -
Vin + Vt -
Vout = 0
It
R, R2
i. Ut =
Rivout + Rz Vin
R, +
R2

At Vvt , Voet transitions from V

,
to Vµ .
cut >
Vref )
Ravin
Vref Ri UL Ravin ( Rit R2 )
Vref
i. > + >
Rivout +

Rtt R2
Vin Vrefl Rit Rz ) UL RI
Vref (1+4-2) vi.
Rig
VUT
> -
-
= - =

Rz

V1 Vt
Vref )
<
At VLT , Vout changes from UH to (

Vet
Rig ¥
i.
UH
(
' +
Vref
= -
-

UL )
=/ UH
Ring 20¥ Rigg Iq
i. Ri IKR
Voy -

Vcr = 5 - =
=
. : =

Rz =
4142

i. -0.4 V
Vyef
=
 instrumentation Amplifier
•

↳
very high gain .
CMRR , input impedance
R2
'

V13 )
'
'
43 V13 Vout
R÷ ( VA RI
R÷
=
=
;
-

± •

Rs R , , R3 ,
•

V13
-

Iq V13 VA
•
=
-

RG i
+
V0 Ut
Rgy
✓
R,
n,
• VA
)
' '
Ro VB -

VA =
IG I Rs t RG t
Rg
I
VA
• =
'

Va =
IG ( 2 Rs + Rbi ) ; Rs =
RG
=
VB -
VA I +
2R5_
RG
( VA VB )
R÷ ( )
"•
Vout
=

HIRI -

, Ra

to current converter
voltage
•

↳ current is less prone to external noise

IL RL
, I =
IL
R
Vin
=
IL
1- É Tin -

•
-12
+
•
Vout
Vin

↳
ground load voltage to current converter

R
I t Iz
=
IL
,

vin-RVA-tvoutp.UA
=
It
÷_m- -

Uout
-

Iz i.
Vin + Vout 2 VA I, R
www.A
- = -

<
•

{ g- i
Vin R R Ii Vout
( (g)
= + VA

Vin + 2 VA -

2VA =
Il -

R IL =
Vin / R

converter
voltage
•

current to

R
Ip Iin Ir
0-vp.int
= =

t
-

volt
Transimpedance
" R
Iin Vout
° =
-1in '

I
It
Amplified )
In
=
.
 And Antilog Amplifiers
•

Log

Isle '%÷
)
I. =
-
l } Fou
antilog amplifier ,

VBE =
VT .
lh
( Icg ) ( "¥ )
Volt = -
r -

Is .

V-ilnr.io?V---KT/q--
vout = -

25.9 mV at
300K .

•
precision Rectifier
Vout → in
considering diode
0
>
ideal
}
when Vin ,

vine 0
, Vouet = 0 .

virtual shout is applicable here also

-

+
It •
Vout
Vin ) will distorted
At
higher freq I 100kHz
output be
IRL
,

↳
modified Precision rectifier I can be used at higher fully alto )

R2

when Vin > 0

,
Di is ON & D2 it OFF .

Vout = O
D'
→ Vin 20 D
, is OFF d
Dz is ON -

Vout = -

R2 Vin
,
r,
um RT
Vin
-

•I Vout

}
+

=
Dz r Full wave =
modified Precision +
Added
=
Rectifier Rectifier 1122/121=-2 ) ( Vin )

Peak Detector
•

RLC 10T IT time period

7
of signal )
=

Rd
Rdc
÷
£
-

+
11 •
Vout
Vin
c=§RL
=

•
circuit
clamper
↳
changes DC level
of the signal to the desired level without changing the

shape of the
signal
Vin =
Vmsinlwt )

I • Vout Vout is DC
shifted upward by Um

Vin
•

¥Be Ri
By reversing direction diode Valet
II =

will be DC
shifted
of
dlllllhlllalld
,

Clipper circuit
diode is reversed it
if ,

will clip bellow Vref

→
M
- - - - - - .

v. g.

input output
I ← Uout

{
•

Vin R
→ ,
chips above
vyq Fret
•
RC Phase shift oscillator

Inventing

IF
OP-AMP
Vin
R n V1 =
- + A
186° → > •
+
+
rout
Vi jxc R -

Vi u,

10
'
tan
(¥ )
<
P
-

' =
-
.

180 - -

1 Apt =L
Attenuation
of
Rt ←

13=-21-9
circuit i. A 29
feedback
-_

I'm
i-ii-ii-I.iq
- -

{ { t.IR
+

t=¥r 1-
=

r r
21T Reran
1- =

t
no .
of RC stages

•
Wien Bridge oscillator

Positive feedback like

↳ acts a notch filter
Ru
run

01=0 VI. Feedback

=p
;
= =
,

-1
um -
Vi fraction
Rz •

+
Vout
f- =
1-

1fi- 21T
Ri Rzcicz

R÷g
i.

R÷g
A =3 = It i. =
2 -

Cz
= R2
sustained RU_ PI
¥
+
for =

1- oscillations R3 R2
,

Analog multipliers
•

✗
Vy •

✗ • V0 =
Vxvy
Vy Ta
.

y
y ,,

↳
Quarter square multiplier

Vout Rt ( 12¥ )
= - • V -
+ It Vt
RT

Eva
( :-, )
= -
+ it V9 I

5T¥
4 (R ) a

v÷+Eg)¥
= -

' '

)
lVy-yV ( sety )
( Ky un
Vogt ¥ Vy
= -
= = =

= IN -

g) 2- Get g) 2

4
 is Vout
Vout ?
÷ Vin Vin
i.
R on :
-
= = = -

x-MR-q-CFfv.at +
y
i.
on

Vout
→

net
Want
= -
=

(
-

Rtg )
Vin

§
,
R =

±
Vin
Inv
-
vo =
-1¥ ,

( ¥,)¥
+
Norlin ✓• =

rout
?÷ Yn÷ +

(1+1%2-1) RI.vn
•
=
- -

Rzt Ry
-

minimum
Divider v1
VOLL
•
: =
.

÷ VOLT
V0 KRI Nz
V¥=
V1
=

Vz
-
= = :
-

. : .
-

R2 B Ta

RC Phase Shift Oscillator : Phase

lag Network f =
e- ; N= no .
Of RC blocks
21T RC

stability
Frequency w1_(d÷)w=w PPM /
•
•
=
C

Twin T Oscillator f- 2T¥

.

: =

Quartz crystal equivalent circuit shuntcapacitance

•

Cp
=

↳ series resonance :
fs
=
1- =

fo ; ↳ = national capacitance
21T Fcs

¥÷cs
↳
Parallel resonance :
fp
=
1- "
↳ =

pg
2ñnTq un

Ri
'

Lc oscillations :
g- =
1-
um -
-

but
LITTLE +

Ci C2 Ci C2
Colpitts -11-111 -11--1--11
-
-

↳-m C =
CI
citcz
P=¥
Av=±
C2
/
1- -1
MY
L

multivibrator
↳
used to implement oscillator ,
timer , flip flop .

' ' ' '

↳
two states : O d 1 .

↳
A stable :
Otp keeps changing in both states
↳
monostable :
one stable & one unstable state
↳
Bistable :
Both states alle stable .
•

A- stable multivibrator
↳
positive feedback
↳ schmitt trigger , replace Vin by RC

R
Time period of
( 1,1-4-3
1- nlh
P
LER
un
= =
212C i
=

square wave ,

Vout
+

c=
{ Ri
-
I
In
=

Mdhdstabll Multivibrator

un
T = Rclh
( +12¥ )
I

Vout
+

c=
{ Ri
a.
-
I
In
=

•
555 Timer

↳ Monostabll multivibrator using 555 timed .

t ""
)
-

Veit ) =
v0 ( 1 e ; V0 =
Vcc
-

"
/ Rt
Vcc Uce l l e- ) Rclh (3) time which Olp will
g-
t, →
for
= -

go in unstable state

↳ A stable multivibrator using 555 timer

changing &
Duty cycle
pyR÷p
ti 0.693 I R R2 ) c
J
= = +
,

, t
,
=
0.693 Rzc discharging time

1- =
tittz
=
0.693 I R , +2 R2 ) C of capacitors
 Phase lock LOOP
•

↳
maintains phase & b/w ilp & Otp
same
frequency
.

Error

input
¥ phase → low Pass voltage control output
ett )
detector filter oscillator
9

capture fo fc to te
↳ to +
range
: -

loop can lock to these

freq . When stalling from the unlocked condition .

↳ Phase detector :

signal 1 has phase ✗

2
P
Error
signal =

fi -

fz