Verilog
Quick Reference Guide
Table of Contents
Data-types .............................................................................................................................................. 6
1.1 Nets: wire ............................................................................................................................... 6
1.1.1 wire ................................................................................................................................. 6
1.2 Registers/Variables: {reg, integer, real, time, string} ........................................................ 6
1.2.1 reg ................................................................................................................................... 6
1.2.2 integer............................................................................................................................. 7
1.2.3 real .................................................................................................................................. 7
1.2.4 time ................................................................................................................................. 8
1.2.5 string............................................................................................................................... 8
1.3 Vectors ................................................................................................................................... 8
1.4 Arrays..................................................................................................................................... 8
1.5 Parameter constants ............................................................................................................. 9
1.5.1 Parameter overriding ................................................................................................... 9
Operators ............................................................................................................................................. 10
2.1 Logical operators ................................................................................................................ 10
2.2 Bitwise operators ................................................................................................................. 10
2.3 Reduction operators............................................................................................................ 11
2.4 Shift operators ..................................................................................................................... 11
2.5 Equality operators .............................................................................................................. 12
2.6 Relational operators............................................................................................................ 12
2.7 Concatenation operators .................................................................................................... 13
2.8 Conditional operators ......................................................................................................... 13
2.9 Arithmetical operators ....................................................................................................... 13
Processes .............................................................................................................................................. 14
3.1 Continuous process ............................................................................................................. 14
3.1.1 Continuous concurrent process ................................................................................. 14
3.2 Procedural process .............................................................................................................. 14
3.2.1 initial, always ............................................................................................................... 14
3.3 Events ................................................................................................................................... 15
Structured procedures ........................................................................................................................ 16
4.1 Blocking assignment ........................................................................................................... 16
4.2 Non-blocking assignment ................................................................................................... 16
4.3 Tasks..................................................................................................................................... 16
4.4 Functions.............................................................................................................................. 17
4.5 Timing control statements .................................................................................................. 17
4.5.1 Delays: {Inertial, Regular, Intra-assignment} .......................................................... 17
4.5.2 Wait .............................................................................................................................. 18
4.5.3 Event based timing ...................................................................................................... 18
4.6 Procedural blocks................................................................................................................ 19
4.6.1 Sequential blocks ......................................................................................................... 19
4.6.2 Parallel blocks ............................................................................................................. 19
4.6.3 Named blocks .............................................................................................................. 19
4.6.4 Disable .......................................................................................................................... 20
4.6.5 Branching constructs: {if else, case} .......................................................................... 20
4.6.6 Looping constructs: {for, while, repeat, forever} ..................................................... 21
System tasks & functions.................................................................................................................... 23
5.1 Display system tasks............................................................................................................ 23
5.1.1 $display, $write, $strobe, $monitor ........................................................................... 23
5.2 File operations ..................................................................................................................... 23
5.2.1 File write ...................................................................................................................... 23
5.2.2 File read ....................................................................................................................... 24
5.3 Simulation control system tasks......................................................................................... 24
5.3.1 $finish ........................................................................................................................... 24
5.3.2 $stop ............................................................................................................................. 24
5.4 Randomizing function......................................................................................................... 25
5.4.1 $random ....................................................................................................................... 25
5.5 Command line input function ............................................................................................ 25
5.5.1 $test$plusargs .............................................................................................................. 25
5.6 Simulation time functions ................................................................................................... 25
5.6.1 $time ............................................................................................................................. 25
5.6.2 $realtime ...................................................................................................................... 26
Compiler directives ............................................................................................................................. 27
6.1 `define ................................................................................................................................... 27
6.2 `include ................................................................................................................................. 27
6.3 `timescale ............................................................................................................................. 28
6.4 `ifdef ..................................................................................................................................... 28
Verilog examples ................................................................................................................................. 29
7.1 One bit full_adder using half_adder ................................................................................. 29
7.2 2:1 Multiplexer .................................................................................................................... 30
7.3 4:1 Multiplexer ................................................................................................................. 30
7.4 4:2 Priority Encoder ........................................................................................................... 31
7.5 2:4 decoder........................................................................................................................... 31
7.6 ALU ...................................................................................................................................... 32
7.7 DFF-Synchronous reset ...................................................................................................... 33
7.8 DFF-Asynchronous clear.................................................................................................... 33
7.9 Modulo 12 – Counter .......................................................................................................... 33
7.10 Dual port synchronous RAM – 256X8 .............................................................................. 34
7.11 Sequence detector-110(Moore overlapping) ..................................................................... 35
Data-types
1.1 Nets: wire
1.1.1 wire
wire is continuously driven by combinational logic. The default value of a wire is “z”.
1.2 Registers/Variables: {reg, integer, real, time, string}
1.2.1 reg
Reg is a variable which retains value till it is updated. The default value of reg is “x”.
1.2.2 integer
Integers are signed values. The default size is 32bits. The default value of an integer is “x”.
1.2.3 real
Real numbers are expressed with a decimal point shall have atleast one digit on each side of
the decimal point. The default value of real is 0.
1.2.3 time
Time variables shall behave same as reg of atleast 64 bits. It is unsigned with default value as
“x”.
1.2.4 string
Strings are sequence of characters which are enclosed within double quotes “ “ and each
character is stored as 8 bits ASCII value. They are stored as reg type variables.
1.3 Vectors
1.4 Arrays
1.5 Parameter constants
1.5.1 Parameter overriding
1st comments -read
Operators z=c&&0; value is 0
otherwise value will be x
z=c||1 value is 1
2.1 Logical operators where is c is x
otherwise value will be x
&& and
|| or
! not
2.2 Bitwise operators
bitwise operator
& and
| or
^ xor
a ~^b exor
~ not
2.3 Reduction operators
and
nand
or
nor
exor
xor
do all this operation internally
2.4 Shift operators
2.5 Equality operators
2.6 Relational operators
2.7 Concatenation operators
2.8 Conditional operators
2.9 Arithmetical operators
Processes
3.1 Continuous process
3.1.1 Continuous concurrent process
3.2 Procedural process
3.2.1 initial, always
3.3 Events
Structured procedures
4.1 Blocking assignment
4.2 Non-blocking assignment
4.3 Tasks
4.4 Functions
4.5 Timing control statements
4.5.1 Delays: {Inertial, Regular, Intra-assignment}
4.5.2 Wait
4.5.3 Event based timing
4.6 Procedural blocks
4.6.1 Sequential blocks
4.6.2 Parallel blocks
4.6.3 Named blocks
4.6.4 Disable
4.6.5 Branching constructs: {if else, case}
4.6.6 Looping constructs: {for, while, repeat, forever}
System tasks & functions
5.1 Display system tasks
5.1.1 $display, $write, $strobe, $monitor
5.2 File operations
5.2.1 File write
5.2.2 File read
init8x8.txt
5.3 Simulation control system tasks
5.3.1 $finish
5.3.2 $stop
5.4 Randomizing function
5.4.1 $random
5.5 Command line input function
5.5.1 $test$plusargs
5.6 Simulation time functions
5.6.1 $time
5.6.2 $realtime
$stime is same as $time but it returns an integer which is 32bits.
Compiler directives
6.1 `define
6.2 `include
6.3 `timescale
6.4 `ifdef
Verilog examples
7.1 One bit full_adder using half_adder
.
7.2 2:1 Multiplexer
7.3 4:1 Multiplexer
7.4 4:2 Priority Encoder
7.5 2:4 decoder
7.6 ALU
7.7 DFF-Synchronous reset
7.8 DFF-Asynchronous clear
7.9 Modulo 12 – Counter
7.10 Dual port synchronous RAM – 256X8
7.11 Sequence detector-110(Moore overlapping)
