Se COMPUTER ORGANIZATION AND ARCHITECTURE (BCS302) Sam Pee Rea ceed Co) aOR id Pea ee i Es Pee eel oe eT Te CO ECL Pee eC eee CS a cen) er eeCr Ted Me ee Re eR re control of set of instructions and generates output. It has the ability to store, retrieve, and process pa —— cela = Cc >A computer is made up of multiple parts and components that facilitate user functionality. A computer has two primary categories: Pe Da ica Mews cl Cn Tee ge ee ed ae Se PES eg eae ct ec Eu: ce eae we -Cau cat id CS cau a Senet ee eet ie co — eee ewe ee kena etal behavior of computer systems. itd adil) De aoe FOU ud Be nee ee ae a | Computer Organization deals with a structural eens 7 Iedeals with bigh-level design issues. Whereas Organization indicates its performance. ee ee co ates isfixed For designing a computer, an organization is cia a Coun ci LtadelalD ade Eo rau ae Pee ea ae PeeTete ae ice uy BULA >We need to first enter the data & instruction in the computer system, before any computation begins. > This task is done by the input devices. (E.g. : keyboard, mouse, scanner, digital camera etc).ae Meee ecu) pee Unis: >The data & instruction that are entered have to be stored in the computer. Similarly, the end results & the intermediate results also have to be stored somewhere before being passed to the output unit. >The storage unit provides solution to all these issues. This storage unit is designed to save the initial data, the intermediate result & the final result.Ginenenca steal cS] Pie NCEE CTU CUES ar Calhed pa <0 es It is also called main memory of computer. It is computer memory that a processor or computer accesses first or directly. It allows a processor to access running execution applications and services. that are temporarily stored in a specific memory location. Itis of two types RAM and ROM. i y Cras) scl PROM Neue meus ig vA RAM EEPRom ee bisae Meee ecu) Doe PRR eg ee ee eco Bou Bi Oo a uc ee ee Au ou ee Ce eed on currently, but needs to process them later. a, iaTete ae ice uy 3) Central Processing Unit: Central Processing Unit (CPU) has two major components: ALU (Arithmetic Logic Unit) and CU (oa) unit, >The CPUis the brain of the computer. In a computer system, all the major calculations & comparisons ee ete Sinesae Meee ecu) ne ah aoe >The actual execution of the instructions (arithmetic or logical operations) takes place over here. >The ALU performs simple addition, subtraction, multiplication, division, and logic operations, such as Es Sido ey ie OR and AND. eR Rae RCL We aR storage, until needed later. Hence, data may move from the primary storage to ALU & back again to storage, many times, before the processing is done. - Par ge rodeo’aie tM aem ice a) (ii) Control Unit: > This unit controls the operations of all parts of the computer but does not carry out any actual data Doce ee Ree Le a ee ee eeu d gee Pea na eel pase sinlad halaTete ae ice uy emer tg ye > Output unit accepts the results produced by the computer in coded form. ee ee > Finally, it displays the converted results to the outside world with the help of output foes De eee sets waaAKTU Full Courses (Paid) — Download Gateway Classes Application From Google Play store All Subjects Link in Descriptiona COMPUTER ORGANIZATION AND ARCHITECTURE (BCS302) a. Uae a ecole) Today's Target ita td Pa kd to Pee ae ence te a a) eee ry wie he oe boas es Pa ain (ery 2Ey g >A bus is a set of electrical wires (lines) that connects the various hardware components of a ula Secu — Ace eu a Re aR en A eS ous rea eke =Key A bus that connects major components (CPU, memory and I/O devices) of a computer system is called as a System Bus. ga >A computer system is made of different components such as memory, ALU, registers etc. eee Ee ack Uta act Careers ils) information flow. re > if we try to implement a nesh topology among different components, it would be really expensive. >So, we use a common component to connect each necessary component Pea) Seren isral Ey TYPES OF BUS MS un ees ean Eu clu So rr ae aCe te aoaDEM en) > OS Co RC Se SP MD eR ug OE he auc ere ces ee Nae > Data bus is a bidirectional bus. 7 pm «epee Prot te i pe eee enna BG ce te eR en Bu a ee UR heEy > Data bus carry commands to an 1/0 device controller or port. a bus carry commands to an I/O device controller or port > Data bus carry data from a device controller or port. > Data bus issue data to a device controller or port.go cd > As the name suggests, control bus is used to transfer the control and timing signals from one Pa es hu mec eucae eau mecca >The CPU uses control bus to communicate with the devices that are connected to the computer Baus >The CPU transmits different types of control signals to the system components. pa er> control signals are generated in the control unit of CPU. > Timing signals are used to synchronize the memory and I/O operations with a CPU clock. Typical control signals hold by control bus- Nie a SR a de > Memory write — Data from data bus to be placed on memory address location. prea aa 1/0 Read — Data from I/O address location to be placed on data bus. fos ga A eh FL eRe Ru eee ce Oe ceed If wea i ETI iCs cy me UE ae SE eee ee ee ae Oe ee ac SE ues — , The type of action taking place on the system bus is indicated by these control signals. EXAMPLE control bus to perform the memory read or write operation from the main memory. Similarly, when the ee RON RE eke Me cn eek ecg ee ae ee RUN aun Run ek ee > tis used to identify the particular location in memory. ee ce Eg Lae datas . where to store or from where to retrieve the pee eee8 facia > When CPU wants to read or write data, it sends the memory read oF Ga Aer ne or Oe on ack a ae nearer Ocoee CIS enue sco IceHEN 5 ea) Pee att ord aEy SU ec ener ua ese a a ee Seen ee e P OU aM a ear sa tater ean Baal SOS ae te CUE oe ae Rec Rec a uke Ue ran am UNISTS) Ey)ral Ey ONE e tee me nly aN eee ERY > Low Cost because a single set of wires is shared in multiple ways ProcessorPRE Te Meee) un Ly PAUSE ake a Un a On acer Lh Pao ee RNA a se SRR UU ee ekAKTU QUESTIONS ( LECTURE 1) ques CWA ree ee rrr Ce ere ra kc cae ae rater rere i — ~~ a teeter) Oe a a Eo) (One (muse) oma comoAKTU QUESTIONS( LECTURE 2) a eS Ce sy ee ee Perec es Reis Vareeey ROeettr ttc Vater ces es Ord aad RN eee lection aetnt OrsAKTU Full Courses (Paid) \—= Download Gateway Classes Application From Google Play store All Subjects Link in Descriptiona COMPUTER ORGANIZATION AND ARCHITECTURE (BCS302) a. Uae a iscelsascola) near Panos van) Arbitration _ Pe ee ect Co OCG Sanat) a CRN Con) —Cy Ey ae cas uM ue Re a ese ee ee ROE ea URC Ae Sl Ae >In order to transfer data between these devices, they need to have access to the bus. pee ect ede eno eC ec a eed BT gr Luo pa ELL NER Sk eee RO aCe ecu ear MO ek tue ec) ecg > To prevent this, a bus arbitration mechanism is used to ensure that only one device has access to the bec OOa BUS ARBITRATION >BUS MASTER ©0943.) RR ee OT ee ees Pay. ae The Bus Arbiter decides who would become the current bus master. pa UPC) IM Bus Arbitration refers to the process by which the current bus master accesses and then leaves the control of the bus and passes it to another bus requesting processor unit.a BUS ARBITRATION ‘Two approaches are followed for the bus Arbitration: _Sentralized Bus Arbitration - In which the necessary arbitration is carried out by lone bus arbitrator. 6 Distributive Bus Arbitration - In which every device takes part in choosing the new bus master. A 4bit identification number is allocated to each device on the bus. The created ID will decide the device's eaeBUS ARBITRATION Centralized Bus Arbitration is of three types-. PaO Rea eo a Re > Rotating or Polling Priority Method “ Pa aa aa AQ Daisy Chaining Method HONEy Pe RE Rm Ro el >If the bus busy line is inactive, the bus controller gives the bus grant signal. eC ee ao ea es ka ue RUE Ti eee eRe pa eevee eam ee RU cue aS AC ake ince > Therefore any other requesting module will not receive the grant signal and can not get the bus access a et: ial alt denhahienbbdalad IS ai shldDaisy Chaining Method Od Meco eA Dre rons P bet = ue a) Priority depends on the physical location of master. b) Propagation delay due to serially granting of bus. c) Failure of one of the devices may fail entire system.Q tele Mem ae easels MUL |Oe ca lene eee ec 1) (O) = g|O=-ao2 = Crone) aae Cee Ree Re nee ce ee ee cu rw ECU nue EE ed Trees Se LES OR ee eu a ee ee eT PC eee etek alo >When requesting master recognizes its address, it activates the bus busylines and takes control of the esa foo man eg This method does not favor any particular device and processor. See ee ne eee Rue raeie Re Decca ‘Adding bus masters is difficult as increases the number of address lines of the circuit.a Independent Request or Fixed Priority Method cS] >All bus masters have their individual bus request and bus grant lines. >The controller thus knows which master has requested, so bus is granted t that master. » Priorities of the masters are predefined so on simultaneous bus requests, the bus is granted based on the priority, provided the bus busy line is not active. Priority us busy line is not active. >The controller consists of encoder and decoder logic for priorities.Independent Request or Fixed Priority Method Pee ce Stee ee ene ad aie DE cod Cee RR Re eR CE eaePras CoStar eet eee Poss Co Simplest os ors Povrcng Not reliable if any | Fully Reliable ooo ecu eal PERFORMANCE —_ | weak, Coreg Excellent oa ey y Pio Reconfiguration | complexity requires ec coe [ Minimum Cc High —AKTU QUESTIONS( LECTURE 3) wea CN Cec aes vase rurocer) pi 4 tered {Ee Ce cn ge en ee eet) ea ia i aAKTU Full Courses (Paid) \—= Download Gateway Classes Application From Google Play store All Subjects Link in Descriptiona COMPUTER ORGANIZATION AND ARCHITECTURE (BCS302) oe Pe a recerellac lola) Se De Peed ised > Memory Transfer and bus og > single shared bus benefits and drawback Eo CUCL ee at erica tens «Mea Pause ey ag® Device Device 2 2 Aca Re om Cuneunicd ot thas Sait eas sea de) , as aaa) pi, ic MT > control unit (CU). Se t a Panaae te pa rr , Fill Cerne . eve poe eee Pa ca NE cee now Avenel le rag er ee So creeile ae eee ues Program counter (PC) is a CPU register in the computer processor which has the address of the next eaten eee ce neta ad > Memory Address Register (MAR): This register holds the address of memory where CPU wants to read or write data. When the CPU wants ee en es eer Rue RR ee RUC Cm ose Rattutes Meter anak pa east ca Bee Og cm en Ce ete ee ne ac) ulator is a registe ehitadigon atedesboeile ae eee > Instruction Register Once an instruction is fetched from main memory, it is stored in the Instruction Register. The control unit ot te eC ee et og Bc Ae OR Re ee Ce ee a Tela Ce ee a a a _ de It decodes the instructions, and controls all the other internal components of the CPU to make it work. taal Une 's major components (CPU, memory and I/O devices) of a computer system is called as a System Bus ———— ‘Three main component of system bus — data bus, control bus , address busile ae eee ped As the name suggests, data bus is used for transmitting the data / instruction from CO tg Oe a — - > address bus As the name suggests, address bus is used to carry address from CPU to memory/IO devices. ca ee The I/O bus is the route used for peripheral devices to interact with the computer processor ute used for peripheral devicile ae eee a cad) A register used for holding information (either program words or data words) that is in the process of lieben Lick —— >General purpose registey~ General purpose registers are extra registers that are present in the CPU and are utilized anytime data or a memory location is required. These registers are used for storing operands and pointers to the central Poe aac) a aey Inputct] Arrangement of Computer Processing Unit with Memory, |/O cS] Pe Meg yaaa) Pa ee R ALA} prom Le > INPUT DEVICES pee EZ aya Ta eee ale ee meee> Memory transfer means to fetch(read) or store( write) data >The transfer of information from a memory unit to the user end is called a Read operatio! — — Mord —— je aU ee Re ee OE RR ad AR Re > A memory word is designated by the letter M. a ee eee eeu a Reco ed Dea Seong ae> Address register is used to store the memory address and data register is used to store the data. > The required information is selected from the memory location by address and that address stored in address register. Se ee eae oie ae Un Cena PaO ean U ec er aan pa aC) >The Read statement causes a transfer of information into the data register (DR) from the memory word OOo tasc) ress register (AR). ~ ee a2) Dea moos ¢ >And the corresponding write operation can be stated as: i ea Rae >The Write statement causes a transfer of information from register R1 into the memory word (M) Reece ae Cac) Memory [¢—— eae £2 *| Unit <— write ll Data Out pata inOe ee ee OO eR Us RR eee ce is collected using bus lines. = pit de >In a digital system of registers, a path must be provided to move information. > Suppose separate lines are used between each register and all other registers in the system. In SOM a Ce eRe CTU ae eee Laas co git li >A bus structure will not require an excessive connection. Thus it is very useful in transferring PaBy >A bus is made up of a collection of common lines, one for each bit of a register, that are used to transfer binary data one by one. ls —— ad pecans Rae > Bus transfer using Three states bus bufferBy Ey SOI RUSS RT yt UM ccc ee a Se a oie eect auctor tee ina plane >The single shared bus is the simplest and least expensive way connecting several components or eae es Au oe a cee Te A ee eee iccSingle shared bus drawback > One of the disadvantages of single bus system, if there is any fault occur, all system affected and the pther feeders pass ae) AOR ET Eis > Single bus structure has disadvantages of limited speed since usually only two units can participate in a Cn ee e ak Ue Ee Cun ie eur hur a geeks teensTeemu eee ey Multiple Bus Organization Improves Efficiency a ee eee eae a ee ee CU) Ce eeu ai ace >When many devices need the bus at the same time, this creates a state of conflict called Dn Raa ee ee A RS Re hs simultaneously, reducing time spent waiting and improving the computer's speed. > Performance improvements are the main reason for having multiple buses in a Aaaem ee eect cy Eee ed Jac Oa ea tee cs ee ec ee a eee Ne Cee ee eee ee eT Ce ch ie ic altel SO ee >A single central processing unit places heavy demands on the bus that carries memory data and peripheral traffic for hard drives, networks and printers. Sec RO kek uc ad >since the mid-2000s, however, most computers have adopted a multi-core model that require additional buses. To keep each core busy and productive, the new bus designs ferry increased amounts of information in and out of the microprocessor, keeping wait times to a minimum.AKTU QUESTIONS( LECTURE 4) a Cem ee er ei) atrocedy daisy chaining bus arbitration schemes mm et or Ernst 23 | Define bus transfer and memory transfer atecres) wa =, CeCe eee et a uch as program | AKTU 2016-17 counter ,accumulator, address and data register, ieee ocr ‘and describe how such an arrangement can work as computer, if connected Sean What is memory transfer? What are the different register needed for memory | AKTU 2013-14 Coins aA —" How memory read and write operation performed in computer system otenres]hg AKTU Full Courses (Paid) _—— Download Gateway Classes Application From Google Play store All Subjects Link in Descriptiona COMPUTER ORGANIZATION AND ARCHITECTURE (BCS302) oe UNIT 1: Introduction De acalhae Pell) decoder Pano e Uae os ie CULT Pa Ce a cng = oa CS ek) as la8 cae Tec a ear Rea eae a ee > Simply, the multiplexer is a multi-input and single-output combinational circuit. >The binary information is received from the input lines and directed to the output line. FR ARC Re os AUR RRC RL RS COR CMs eee aE Ret WHAT DO YOU MEAN BY COMBINATIONAL CIRCUIT? Dera Re Ne cu uk ae Re oeINPUTS Output ad Multiplexerey 44 MultiplexercS] Pyzeelya cS] OCCU eC Ue ae Pept ee = Seeeeeee! an a eS ee! ae ea coat“INPUTS OUTPUTSBus transfer through multiplexer Se oe eae eR Ua from one register to another. sie sti a Ree un Ce tg pathos DD Insel clad, CeCe ee sn em OR eas eee Meee acd Cee aU aS uC es ee ec Le eM each bit of a register, through which binary information is transferred one at a time. Ree can ees ee ee eee as cd Pen >One way of constructing a common bus system is with Pee SUR cee am Td Pee eee eed ae a eae eeu ete a)I Saw Bus transfer through multiplexer >A The two selection lines S1 and S2 are connected to the selection Meme nce Beet Ud uno ee een ee ee Ce . $150 = 00, the 0 data inputs of all four multiplexers >When both of the select lines are at low logic, are selected and applied to the outputs that forms the bus. This, in turn, causes the bus lines to receive NM OCU eR eee eR RR ee ee Similarly, when $150 = 01, register B is selected, and the bus lines will receive the content provided by aot Register Selectedct] Bus transfer through three state gates a Perse >A bus system can be constructed with three-state gates instead of multiplexers eee ee eke ee ecm > Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate. wo of the states are signals equivalent to cy > The third state is a high-impedance state. >The high-impedance state behaves like an open circuit, which means that the output is disconnected PUR Cena ie Nea yt ———_~ =Normal input A —— cst input ¢ a =A, fC High-mpedance it C=0 The graphical symbol of a three-state buffer gate can be represented as: 4® Bus line for bit 0 Ss So .2*4 decoder E iSCe Oc > The construction of a bus system with three-state buffers is demonstrated in Fig. The outputs of four buffers are connected together to form a single bus line. abhi ica hacia) Voted eR Tee Ree eR mM Rea RR ae eR Re eR bus line . No more than one buffer may be in the active state at anygiventime. eee Re Ce Re ee RU RS PCE Ra tee RE ret a Meal oe eTct] Bus transfer through three state bus buffer ee ee CU eee ee as shown in the diagram. eR UE RTS Ue ral ak Rem RC aeRO Ree eo eee eC Ro src aeckah TF EE a > When the enable input Is active, one ofthe three-state buffers wil be active, depending on the binary value in the select inputs of the decoder.ai Draw a diagram of a bus system in which its uses 3 states buffer& a decoder OSs eri a — 3) bc) cord Draw a diagram of a bus system using MUX which has four eka) eee each avySe COMPUTER ORGANIZATION AND ARCHITECTURE (BCS302) a. OTe ea bcos eco) Mc hdd as Pee ST) ee Pee R Eg ee ae ee Rug ie ea a Pee eT Cee Cena}8 Ed >A Stack is a linear data structure that follows the LIFO (Last-In-First-Out) principle. pee a >it contains only one pointer top pointer pointing to the topmost element of the stack. > Whenever an element is added in the stack, it is added on the top of the stack, and the element can ee es On ca Ce Erreur er ntoae a iy ad ay, Med aa aCe trdta. potrth Bie Esa a Amey | ToS st eso)Push2 >| =ey g — Ursbeptowg |e (a+b+c)*(c+d)) infix expression pre CMe) , alll cae ag = a a ee ) a (Coola cera) = aril wre Sor a eer DEGE®) UY € ‘a CD) Per co Olek CT a ee CUNO eos8 Des URE osm OR RUC see CR se Re en There are several types of instruction formats, including zero, one, two, and three-address a eed Seeessione pee OR Ra ce Re eR Se cee ae era multiply, complement, and shift. Se RS CO ced Trcic key CyBy Ey This instruction does not have an operand field, and the location of operands is implicitly represented. OPCODEBe RUC a Stee ea Ur) en) eee ee Urea Ct OEY US alee) LN) aed ea} PUSHC = TOS€C PUSHD TOS€D ADD TOs € (C+D) re oe alee Ea ea) ee a noPoe errata Pee They are simple and can be executed quickly since they do not require any operand fetching or addressing. They also take up/less memory space. De They can be limited in their functionality and do not allow for much flexibility in terms of addressing modes or operand types pada iLLEy Ey > This instruction uses an implied accumulator for data manipulation operations. > An accumulator is a register used by the CPU to perform logical operations. >In one address instruction, the accumulator is implied, and hence, it does not require an explicit ee >For multiplication and division, there is a need for a second register. However, here we will neglect CO eee eer ett geen on ee ut scr MODE OPERANDoT ECM tao) Pe RU cues ea ee ee ee Eee ad >LOADA Xe) > ADDB maar] LoAD paola Roe Eras ~ ue pate) Uke roa) pv aD) Ne NeaN ED) a) >MULT eran ora Ti] Sy Paola DTS ras>All operations are done between the accumulator(AC) register and a memory operand. me ———T, >MI]is any memory location. > MIT] addresses a temporary memory location for storing the intermediate result. > This instruction format has only one operand field. This address field uses two special instructions to lec > namely: / >LOAD: Thisis used to transfer the data tothe accumulator. eS ee Ree ee Rag pork added a! coummator.to the mem> These instructions specify one operand or address, which typically refers to a memory location or ijn! dhtahealiaalinn! Aetoin register. The instruction operates on the contents of that operand, and the result may be stored in ied ail i eee elon Sally Cease <=.CJ Ey Cele ean ETc BeAr SA RL AC eke ee BU Re ee ee ee ae ial SRE acne ee Cc uC eCcy Ey >These instructions specify two operand or address, which typically refers to a memory location or CSC URS ed eee Co CU RU Con AR Ee Cs - | OPCODE OPERAND 1 OPERAND 2By Ey Pea eu Reece Re Pie UE es ee result was stored in the accumulator, here the result can be-stored at different locations rather than Pe ee le ae NRA eee Ue a esBAR Ce alot) Example: The program to evaluate X = (A +B) * (C+ D) is as follows: MOV R,, A Cy} 4 LUT a) eo ea) @ [Veen Pee) a LUT a) Deer] > a Ia ee . j Le ae A Re al The MOV instruction transfers the operands to the memory from the processor registers. R1, R2 neBy are ee ati ONC oe They allow for more complex operations and can be more efficient than one-address instructions since RE e ac add sere PS Rc Be Re addressing modes. nn * a DIE oe Bo Cue RC od Nie alleen te Rahacy Ey These instructions specify three operands or addresses, which may be memory locations or registers. Be ee ee beeing >) ashi. adel in the PT cra a coosBy > This has three address field to specify a register or a memory location. ae eC Eee aged ee Ree eacicnbiahaeiaaihdiitaanie Ce sea eat ee a geo Ce eg Cae ea eC Cog) (changing content of register, loading address in address bus etc.) will be performed in one cycle only Pete etBeto eee ot Cao) RU Cue aut ea ee ea ee ee SU ue sd Oe a Ree ce Lee ce ADDR, A,B Raa) | LT een) R, © M[C]+M[D]} TeaEy ONC oo > They allow for even more complex operations and can be more efficient than two-address instructions since they allow for three operands to be processed in a single instruction. They also allow for a wide range of addressing modes. as > They require even more memory space than two-address instructions and can be slower to execute Penna ci h ui eur etree e ne) >Overall, the choice of instruction format depends on the specific requirements of the computer architecture and the trade-offs between code size, execution time, and flexibility the trade-offs De og