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Xilinx Logic Gate Source Code Examples

The document contains source code and syntax for several logic gates - XNOR, full adder, half adder, and XOR - implemented in Verilog. It includes testbenches to simulate the gates and monitor their outputs under different input conditions. Descriptions are provided for the module declarations and logic assignments for each gate design.

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Ahmed Raza
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105 views3 pages

Xilinx Logic Gate Source Code Examples

The document contains source code and syntax for several logic gates - XNOR, full adder, half adder, and XOR - implemented in Verilog. It includes testbenches to simulate the gates and monitor their outputs under different input conditions. Descriptions are provided for the module declarations and logic assignments for each gate design.

Uploaded by

Ahmed Raza
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Xilinx software (DS LAB)

Aashir Ramzan Dedicated to

For some Special Fellow

Danish, Bawa &Kashmiri & Arfan & Madni Bhai Adnan

Source code of XNOR GATE:


module testbench;
reg t_a,t_b;
wire t_c;
XNOR my_gate(.A(t_a), .B(t_b), .C(t_c));
initial
begin
$monitor(t_a,t_b,t_c);
t_a=1'b0;
t_b=1'b0;
#1
t_a=1'b1;
t_b=1'b0;
#1
t_a=1'b0;
t_b=1'b1;
#1
t_a=1'b1;
t_b=1'b1;
end
endmodule
Syntax of XNOR GATE:
module XNOR(
input A,
input B,
output C
);
assign C=~(A^B);

endmodule
Source code of Full Header:
module testbench;
reg t_a,t_b,t_c;
wire t_s , t_carry;
fullheader my_gate(.A(t_a), .B(t_b), .C(t_c), .S(t_s),.Carry(t_carry));
initial
begin
$monitor(t_a,t_b,t_c,t_s,t_carry);
t_a=1'b0;
t_b=1'b0;
t_c=1'b0;
#1
t_a=1'b0;
t_b=1'b0;
t_c=1'b1;
#1
t_a=1'b0;
t_b=1'b1;
t_c=1'b0;
#1
t_a=1'b0;
t_b=1'b1;
t_c=1'b1;
Xilinx software (DS LAB)
#1
t_a=1'b1;
t_b=1'b0;
t_c=1'b0;
#1
t_a=1'b1;
t_b=1'b0;
t_c=1'b1;
#1
t_a=1'b1;
t_b=1'b1;
t_c=1'b0;
#1
t_a=1'b1;
t_b=1'b1;
t_c=1'b1;
end
endmodule
Syntax of Full Header:
module fullheader(
input A,
input B,
input C,
output S,
output Carry
);
assign S=A^B^C;
assign Carry=A*B|C*(A^B);
endmodule
Source code of Half Header:
module testbench;
reg t_a,t_b;
wire t_s,t_c;
halfheader my_gate(.A(t_a), .B(t_b), .S(t_s), .C(t_c));
initial
begin
$monitor(t_a,t_b,t_s,t_c);
t_a=1'b0;
t_b=1'b0;
#1
t_a=1'b0;
t_b=1'b1;
#1
t_a=1'b1;
t_b=1'b0;
#1
t_a=1'b1;
t_b=1'b1;

end
endmodule
Syntax of Half Header:
module halfheader(
input A,
input B,
output S,
output C
);
assign C=A*B;
assign S=A^B;

endmodule
Source code of XOR GATE:
Xilinx software (DS LAB)
module testbench;
reg t_a,t_b;
wire t_c;

XOR my_gate(.A(t_a), .B(t_b), .C(t_c));


initial
begin
$monitor(t_a,t_b,t_c);
t_a=1'b0;
t_b=1'b0;
#1
t_a=1'b1;
t_b=1'b0;
#1
t_a=1'b0;
t_b=1'b1;
#1
t_a=1'b1;
t_b=1'b1;
end

endmodule

Syntax of XOR GATE:


module XOR(
input A,
input B,
output C
);
assign C=A^B;

endmodule

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