GOVERNMENT COLLEGE OF ENGINEERING, JALGAON
(An Autonomous Institute of Government of Maharashtra)
“Globally Accepted Engineers with Human Skills”
Department of Electronics and Telecommunication Engineering
Very Large Scale Integration Design Lab
(ET 406 UD)
Academic Year: 20 - 20
Course Code & Course Name: Very Large Scale Integration Design Lab (ET 406 UD)
Name:
Year & Programme: Final Year B. Tech
PRN: Batch:
GOVERNMENT COLLEGE OF ENGINEERING,
JALGAON
(An Autonomous Institute of Government of Maharashtra)
Fax – 0257-2281319
Phone No:- 0257-2281522
Web.-http://www.gcoej.ac.in
E-Mail- [email protected]
Year and Programme: B. Tech (E&Tc Engineering) Academic Year: 2022 – 2023
Course Code and Course Name: ET - 406 UD ( Very Large Scale Integration Design Lab)
INDEX
Sr. Date of Date of Signature of
No. Name of The Experiment Performance Completion Teacher
1 Implementation of Basic Logic Gates
2 Implementation Of Binary To Gray Code/
Gray To Binary Code Converter
3 Realization of D FLIP FLOP
4 Implementation of 4:1 & 8:1 Mux
5 Half Adder using Data Flow and Behavioral
6 Full Adder Using Structural, Dataflow And
Behavioral
7 Implementation of Up And Down Counter
8 Realization of SR Flip Flop
9 Realization of JK Flip Flop
10 Realization of T Flip Flop
11 Realization of Sequence Detector
12 Implementation of 3 To 8 Decoder
13 Implementation of BCD Counter
14 Implementation of ALU
15 Study of Simple Processor
CERTIFICATE
This is to certify that Mr./Miss PRN of
Final Year B.Tech E&Tc has satisfactorily completed the experiments/assignments/work specified for
Internal Continious Assesment of VLSI Design Lab. As specified in syllabus of this institute for the
academic year 20 -20 .
Course Teacher Course Co-ordinator Head of Department Principal
GOVERNMENT COLLEGE OF ENGINEERING,
JALGAON
(An Autonomous Institute of Government of Maharashtra)
Phone No:- 0257-2281522 Fax – 0257-2281319
E-Mail-
[email protected] Web.-http://www.gcoej.ac.in
Internal Continuous Assessment of Laboratory Course
Name of Student: PRN:
Year and Programme: B. Tech.(E&Tc Engineering) Academic Year: 2022 - 2023
Course Code and Course Name: ET – 406UD (Very Large Scale Integration Design Lab)
Sr. Marks Obtained Signature of Signature of
Name of Experiment
No. A B C Total Teacher Student
1 Implementation of Basic Logic Gates
2 Implementation Of Binary To Gray
Code/ Gray To Binary Code
Converter
3 Realization of D FLIP FLOP
4 Implementation of 4:1 & 8:1 Mux
5 Half Adder using Data Flow and
Behavioral
6 Full Adder Using Structural,
Dataflow And Behavioral
7 Implementation of Up And Down
Counter
8 Realization of SR Flip Flop
9 Realization of JK Flip Flop
10 Realization of T Flip Flop
11 Realization of Sequence Detector
12 Implementation of 3 To 8 Decoder
13 Implementation of BCD Counter
14 Implementation of ALU
15 Study of Simple Processor
A: 6 or 12 marks for attendance in laboratory (3 or 6 marks for performing experiment at regular term
and 3 or 6 marks for assessment of experiment at regular tern; 1 or 2 mark per tern should be reduced if
experiment is notperformed/assessed at regular tern.
B: 10 or 20 marks for performance in laboratory and depth of understanding (maybe based on oral)
C: 9 or 18 marks for presentation i.e. writing work and result i.e. calculation, graph etc.
Detailed Procedure Starting to Program Debugging
● Implementation :
Start Xilinx 14.7 –> File –> New Project –> New project wizard (Name & Location ie xilinx
from drive c, working directory) –> Type Project Name
Next –> Project Setting (ie project Family Device, package, Speed From the development
board) –> Next –> Finish.
Then go to the Source window –> Right Click on that –> New Source
ET 406 UD | Very Large Scale Integration Design Lab 1 of 81
Select Source type for eg VHDL module –> Give File name –> Next
Define input output module with Variables –> Next –> Finish.
write the Program in VHDL module workspace –> Save –> Then Process The options
(Synthesize, Translate, map, Place & Route From implement Design).
ET 406 UD | Very Large Scale Integration Design Lab 2 of 81
● Behavioral Simulation :
Click on Source window then –> ISim simulator option will appear in the processing window
Check Behavioral Syntax –> Simulate Behavioral model –> Project output window will
appear –> Assign values to input and check the output –> Values are assign by right click
on input variable and select force clock for giving rising and Trailing edge value & Period.
Test Bench Implementation
Source –> New source
ET 406 UD | Very Large Scale Integration Design Lab 3 of 81
Add file name –> Next –> attach to proper project –> Next –> Finish –> Add condition for
test benches –> ISim simulation.
RTL schematic :
Implementation –> Select source file –> Synthesize-XST –> View RTL schematic –>Start
with a schematic of the top level block –> Ok.
Implementation (Debugging in Hardware)
Go to new Source file in Source window –> Right click –> New Source –> Implementation
Constraints File –> Add name –> Next –>Finish
ET 406 UD | Very Large Scale Integration Design Lab 4 of 81
In the source window (---Behavioral file---)click on that –> UCF file will display –> In the .UCF
NET list file for initialize Input & output pin –> save –> Generate Programming file –> VHDL bit
file configure Target device –> One warning window will display –> Ok –> Double click (Boundary
scan) –> Right click for initialize JTAG chain –> Initialize Chain –> Chain will display –> Right
click on first chain port –> Right click –> Program –> Check output.
ET 406 UD | Very Large Scale Integration Design Lab 5 of 81
