Verilog FAQ
Interview
Questions
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Difference between continuous assignment and procedural
assignment
procedural Assignment
I
continuous Assignment
10 Assign values to 1. Assign values to
variables.
nets
reg
2. tred to Used to infer both
infer com- 2.
binational logica storage elements like
flip-flops and latches
and combinational logic.
3. occurs Occurs construct
in
assignments 3. in
to wire, fortand not like always, initial
tybe I task, functions.
-
4. Variables and nets 4. of calculations
Result
continuously drive values
involving
can be
variables and nuts
store into variable.
Onto
parts.
5.
Assignment occurs 3. The value of the furious
whenver the value on the is held
assignment until
RHS of the expulsion another assignment
is made
changes as continuous to the variable.
process. For example:-
For
example:
always 2 (Posedge ((K)
wire out insinc;
leg in1;
or
always I (or bors)
assign nlsinc;
out- y (S =
= =
1)?aib;
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Difference between blocking assignments and non blocking assignment
Blocking
assignments Non-blocking
assignments
1.
the
In a
blocking assignment 1.
Non-blocking
assignment
evaluation of the exp- to LHS is scheduled to
ression on RHS is occur when the next
evalu
updated to the LHS ation
cycle occurs in
variable
autonomously based simulation imme
and not
on the delay value. diately.
There
2. is
possibility
a 2. The race
the
condition are
of race condition. as
avoided updated value
is assigned after evaluation.
3. Recommended to use 3. Recommended to use
within combinational within the sequential
always blocks. always blocks.
4. Can be in proce 4. Can be used
used only in
edural like the proudural blocks like
assignment
initial, always and continue vinitial
and always.
ous assignments to nits continuous assignment to
netlike the
like assign statements. assign statement
permitted.
is not
5. It
isrepresented 5. It represented
is
by
by (=) operatorsign. KI) operator sign.
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For example:- For example: -
I
begin
intial
begin
intial
regl= #152'b 11;
r= #152'bl;
Mega- #521b01;
#52'bol;
regz=
end
Difference between initial and always
initial
always
1 alw
Assignmentin an 1. Assignmentin an
blockbegin
intial to
as
flockalso begin
exete from time
o from time O, and replet
in simulation. forever as a function of
the specif the charges on the blocks
and proud in
icch sequence. sensitivity list.
2.
Non-synthesizable 2. Synthesizable
3.
3. executed
only once exention
continuously
during simulation. repeats from the begin
to the end of the proces
unless hold wait.
by a
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I
Ferample: For example:
reg (100] 41,42; reg ('0] 41,42;
ential
begin always & (bosedgeck)
2'b11;
41= begin
2 2'b01;
# =
y = in1;
end Y y, Sinz;
=
end
Difference between function and task
Functions Tasks
1 function can enable 1. A taskcan enable
another function but other task and junctions.
not other task
2. Function Task
always exe-2. may execute in
time,
cute in
zero simulation nonzero simulation
time.
so function always 30 pask do not return
return with value, but
a
single value a
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I
they can not have output can pass values
multiple
orinout
arguments. through output and inout
arguments.
4. Function must not 4: taskmay contain day
contain any delay, event event
timing
or
or timing contral sta-contral statements.
lements.
5.Function must have 5. Task have
may zero
atleast
one input
argu or more
arguments of
ment. They have more type input, output or
than one
input. smout
Difference between define and parameter/defparam
define parameter/dyparam
I
define
is
basically A 1. Parameter used to
specify
text substitution macro. constantin a
design
2u cannot be overriden 2. Parameter can be
in any mechanism. overriden.
modules can
3.
Only one constant 3.
Multiple
with the given name can have the same parameter
exist in the full scope. is
Name,as it limited
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·minmat
thatscope
to
only.
Difference between asynchronous reset and synchronous reset
Asynchronous reset synchronous rest
2. Doesn'tdepend upon 1. Depends upon the presence
the presence of anactive of the signal
clock far
Clock signal the rest to happen.
2. effectof east can 2. Effect of restwill
happen only on the active
onously. edge of clock.
a
3. Rest Signal not
is 3. Rest signal part
is
the data path path,
a
partof of the data it
ie, not a
of logic
part the D inputof the
D inputof the FF. FF.
for
4. Not For
recommended 4.
internally
for internally generated generated rests, synchro
rusts, due to glitches. nows approach the
is
best mechanism.
5. Asynchronous rest 3. Additional Synchroni
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I
input the
double FF
still
needs sation circuitry isnot
synchronization requiredas part
it is
avoid condition
of the default synchronous
to ran
diving
deassertion. logic requirement.
far sample:-
for example:-
always of (posedge cor always &
(posedgeck)
posedge rest)
begin
begin
if Crelt)
if (rest) begin
end
out =0;
Su 0;
=
and end
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Difference between full case and parallel case
I
full-case parallel case
1. Indicates that the call 1. Indicates that all case
statement has been items be evaluated
fully and to
not
specified, and all onspecified in parallel and infer
case expression can be
any priorityencoding
optimized away. logic.
2. All contral paths are 2. There no
is overlap
explicitly
specified or the case items.
among
by whing default.
3. Helps latches
avoid 30 Results in multiplenar
as all cases are
logic as a parallel logic.
fully specified.
for example:-
for example:
reg b(1.0]; reg b(2:0];
always & (nor yor2) always & (n ory or 2)
begin
case (b) begin
2 b'00: out=v; Cabe(b)
2 b101: out=y; 3b'000: out=x;
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3b'001: out=y;
I
2b'10: out=2, 361010: out=2,
2b'll: out=xsy; endcast
endcase end
end
Difference between mealy machine and Moore machine
Mealy Machine Moore Machine
1 oubuts are a fun I outputs are a function
tionof current state of count state
only.
and input signals.
2. Outputcan change 20
outputs change only
between changes between when the Lurent
State. state charges.
3. Output can
changes any
30 outputisdelayed by
number
clock
during
of times
which
one
is stable.
cycle,
clock but
a
cycle,
may result
inglitches
on the outputs.
frequency
high
4. Lower No can expect
is expected compared to frequency compare
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mealy machine.
I
a moore machiner
Difference between binary encoding and one hot encoding
one-hot
Binary encoding encoding
1. Require fewer number 1. Number of FF
required
of Fris to represent is equal to the number
current state. of states in the ESM.
20 critical path analyses 2. Easy to critical
find
the STA.
requires
combinational
tracking baths during
logic.
3. Since the number of Don't
3. had to opti
is limited good
FF the state
mize encoding
has
optimization is required as each state
for encoding. unique flop anyway.
4. Hard 4. Easy
to
debug. to
defug,
1. What is difference between == and === in verilog ?
2. What is difference between wire and reg?
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