J-11

PROGRAMMER'S REFERENCE

Rev. 2. ~ 4 (J an ua ry, 1982)

COM PAN Y CON F IDE N T I A L

Copyright (c) 1979, 1980, 1981, 1982 by Digital Equipment Corporation

~

The information in this document is subject to change without notice and

s h 0 u 1 d not be con s t rue d a s a c 0 mmit men t by Dig ita 1 Equi pm en t
Corpora tion. Dig i tal Equi pment Corporat ion assumes no respons ib iIi ty
for any errors that may occur in this document.

This sp~cification does not describe any program or product which is

currently available from Digital Equipment Corporation. Nor does
Digital Equipment Corporation commit to implement this specification in
any pro g ram 0 r pro d u ct. Dig ita 1 Equi pm e n t Cor po rat ion ma k e s no
commitment that this document accurately describes any product it might
ever make.
J-ll PROGRAMMER'S REFERENCE Page 2

REVISION HISTORY

REV DATE REASON

2.04 1/82 Minor corrections

2.03 7/81 Revised CPU Error Register and stack trap

description; minor corrections

2.02 12/80 Added floating point instructions

2.01 7/80 Added Table of Contents; revised I/O space, CPU Error
Register, and Memory System Error Register;
reorganized chapters 3, 4, and 5

2.00 1/80 Added PS protection chart, console single step

1.04 12/79 Revised Cache Control Register and Memory System

Error Register; added Hit/Miss Register; cleanup

1.03 8/79 Added comparison to 11/4~; eliminated stack limit;

title change

1.02 7/79 .Eliminated instruction complete; cleanup

1.01 0/79 Added I/O bus time error bit in CPU Error Register;
added CPU abort error bit in Memory System Error
Register; added disable interrupt bit in Cache
Control Register; fixed up original

1.00 5/79 Preliminary

J-11 PROGRAMMER'S REFERENCE Page 3--

TABLE OF CONTENTS-

1.0 INTRODUCTION

1.1 Scope
1.2 Method
1.3 Applicable Documents

2.0 INSTRUCTION SET

3.0 ARCHITECTURAL FEATURES

3.1 General Registers

3.2 Processo r Sta tus Wo rd - _-PS (1 777777F,)
3.3 Program Interrupt Request Register - PIRQ (177 7 7772)
3.4 CPU Error Register (1'77777(:),6)
3.5 Stack Protection
3.6 Kernel Protection

4.0 MEMORY MANAGEMENT

4.1 Page AddresS Registers - PARs

4.2 Page Descriptor Registers - PDRs
4.3 Memory Management Register 0 - MMR0 (177 7 7572)
4.4 Memory Management Register 1 - MMR1 (17777574)
4.5 Memory Management Register 2 - MMR2 (1777757F,)
4.fi Memory Management Register 3 - MMR1 (1777251~)
4.7 I and 0 Space

5.0 MEMORY SYSTEM

5.1 Cache
5.1.1 Cache Control Register (17777746)
5.1.2 Hit/Miss Register (17777752)
5.1.3 Cache Multi-Processor Hooks
5.1.4 Cache Response Matrix
5.2 I-Stream Buffer
5.3 Memory System Error Register (17777744)

6.0 FLOATING POINT INSTRUCTIONS

6.1 Floating Point Status Register - FPS

6.2 Floating Point Exception Code and Address Registers -
FEC, FEA
F,.3 Accuracy
J-ll PROGRAMMER'S REFERENCE Peige 4

TABLE OF-CONTENTS (cdnfinued)

7.0 TRAPS AND INTERRUPTS

8.0 GENERAL PERFORMANCE GOALS

9.0 CONSOLE
10.0 11/44 HARDWARE DIFFERENCES

11.0 11/70 HARDWARE DIFFERENCES

Appendix 1 J-11 Base Instruction Set '-

Appendix 2 - J-11 Floating Point r"nstruct ion Set ~

Appendix 3 J-11 Commercial Instruction Set

Appendix 4 - Console Command s

J-11 PRQGRAMMER'S REFERENCE Page :5"

1.0 INTRODUCTION

1.1 Scope

Th is document spec i f ies the prog rammer-v is i ble function~ 0 f the, J.."...ll, a
high performance, MOS CPU ch~i-p set for the PDP-II family.~, ''''The J-11
implements the important 11/44 and 11/70 features:1see sections 10 and
11 for summary ,di-ffe~ence lists) and achieves 11/7,0 performance', in most
applications.

1.2 Method

The J-11 is in'fended'to replace both the 11/44 <ind the ~1/7,0. £: It will
run RT-11, RSX-11M, RSX-11M+, RSTS/E, DSM-11, UNIX, and KSOS. The 11/44
and 1 1/7 0 a r ~~ not e n t ire 1 y com pat i b 1 e • Wh e n a ~: hO,: ~ e e . bet wee n
4

conflicting impleme'n.ta,tions is necessa,ry,,_ the J-11·, .fo,l;l-o:ws' ,the 11/44

rather than the 11/70. The only exception:s are'f'eatur~s~ which impact
potential software coverage (e.g., dual register set) or which unduly
complicate the MOS implementation.

1.3 Applicable Documents

J-ll Chip System Specification

PDP-ll/70 Processor Handbook
J-11 Control Chip Specification
J-11 Data Chip Specification
J-l1 Microprogrammer's Reference
J-11 PROGRAMMER'S REFERENCE Page' ~.

2.0 INSTRUCTION SET

The J-11 instruction set consists of the following:

11/70 Base, :Ihstruction Set including thee Exte-rided

Instructiort Set (EIS) plus th-e MT-PS, MFPS, MFPT,
TSTSET, WRTLCK,' and CSM instructions. Appendix 1
con t a-ins the com pIe t e l i s t 0 f -J -11 - -b a" s e
instructions.

- Floating Point (FPl1) Instruction Set compatible

with the FP11A/C/E floating point processors.
Appendix 2 contains the complete list of J-11
fJo-at,ipg_ point instruction?

- -. Commercial Instruction Set (CIS) compatible- wi th_

~J1E:S:: -St.§ndar.<t,158. Appendix 3 contains the c6~-plete~
list of :J·-l1:: 'C'IS inst:tuctions.

3.0 ARCHITECTURAL FEATURES

3.1 General Registers

These include:

- Two sets of six working registers (~0-R5)

- Kernel/supervisor/user stack pointers (R~)

- Program counter (R7).

Th i s i s full y com pa t i b 1 e wi t h the 11/7 0 • The 11/44 lacks a second

general register set.
J-ll PROGRAMMER'S REFERENCE page''}'

3.2· Processor ,Status W.ord ~ PS (1 7 777776)

The Processor Status Word (PS) contains information on the sta'tus' o:f the
processor.

15 14 13 12 11 10 ' . 9 8 7 5 4 3 2 1
+-------------------------------------------------------------------+
, -I- 1.1 II-I I I I I I I I I 1 I I
:, oN "
,
I I11111111I
II1111111I
1 T
I
I
, "
,Z I V
,
I
,
C I
,
+- --~ . ,._. . .:...---~--,- -,-.'I ::----.-:.-------------------------------------
I . , ":;..'~;-'...;. .. -~+.
I' "

, I I
Current I
Mode "
f
.,
,/ , I
I
I
I
I
I
I. I I
,
I
Prev iouS'-Mode~.....:.._:J
I ,I I
I
I
,
I
Reg ister Set - I , I
----..--~--
.. I r I
Instruct·ion, Suspen,s ~o'I1' I r I
. .,I ------------- I I
priority___________~~_ _ _~~______~___ I I
I I
Trace \ Trap- .
I --~-------------~------------------------
I
,
I
ConditionCOd~s I J

--------------------------------------~------
BIT NAME' FUNCTION
15:14 'Current Mode' Current processor mode: .~ :'
,(RW., protected)_ 00 = kernel
01 = supervisor
10 = illegal ( traps)
11 = user.

13 :12 'Prev,ious' Mede Previous processor mode, same

{RW,;" pr~t:ec'tedl encoding as current moge:'

11 Reg! ster Set- General register set s~l#ct~'

'(RW,' protec·t-ed) o = reg is te r se t 0 . ,
1 = register set 1.
Instruction Suspension Set to indicate that a CIS instruction
(RW) was suspended to service an interrupt.
7:5 Priority Processor interrupt priority level.
(RW, protected)
4 Trace Trap Set to force a trace trap.
(RW, protected)
3:0 Condition Codes Processor condition codes.
(RW)
J-11 PROGRAMMER'S REFERENCE Page 8

Fo r the protection on the PS unde r va r ious cond i t'ions, see Table 3-1.
Th e PSi s i n i t i ali zed a t po we r up ( de pe nd son po we 'r U pop t i 0 ri s " and is,
cle-ared at console start. The RESET instruct"ion does not affect , ;
the PS.

Table 3-1
PS PROTECTION

I I--~-----/--------I--------I 1--------1--------1--------1 I
, / I . RTI, RTT I I TRAPS & INTERRUPTS I I
PS - ~.i.~lsJ~ _../1 User I Super I Kernel/ I User I Super/-Kerne·lll-
___ -------_1 1--------1---------/--------1 /-----:---.;--.-.~ /_-_ ... ______1_____·. . . .---1 I
Condition 1/ loaded I loaded I loaded I I loaded I loaded I loaded / I
Codes I I from I from I from I I from I from I from I' I·,
PS <3:0> II stack stack I stack II vector I vecto.r I r-
I vector
/ 1-------- --------1--------1 /--------I--------I--,~;;..~·.;...,-....:·r /
I I loaded loaded I loaded / I loaded / loaded r~loaded 1 1
Trap Bit / I from from I from I I from I. ~ rom, ..__ . f' fro m ,11'
PS <4> II stack stack I stack II vector / .v.~ctor ',\7Eic,tor"'I';L
I 1---:..---- --------1--------1 I------.:-~J. -.::- ....:.·~.:..:...:'r=·~--~- . . ~ I I
Processor I I un- un- I loaded -,~ I-.loaded L. loaded .- ~.' loaded 1 t .
Pr ior i ty I I changed changed 1 from / / from L from . L from I /-
PS <7: 5> 11 ./ s t ac k I / "ve.c to'--.J .'y.~c.to.L _I vecto r 'I I,
. I 1-------- --------1--------11--------1--------1-----.;...--1 I
CIS 1 I loaded loaded I loaded I_load~d I loaded 1- lo~ded 1 I.
Suspend Bi t I I from from I from I from 1- from'-- I' fioin , I.
PS <8> ~.+- stack stack I stack J vector. I vector I 'vector II--
I 1-------- --------1-------- I--------I---:..--:-I----.. ---~ I I
Register I I ORed ORed I loaded 1 loaded I loaded I lo~(feif I I
Select 1 I from from I from from I from I fr6~~~1 1
PS <11> I I sta6k stack 1 sta6k vector I vectbr'I·-vector I I_
I 1--------1--------1-------- ________ I ___ .;..._...:.;;..~·I·~...;. __ ·... i... __ 1 /
Previous I I ORed I ORed I loaded copied 1 copied I copied I I
Mode I I from I from I from from I from I from I I
PS <13: 12> I I s tac k I s tac k I s tac k PS I PS 1 PS I I
J .J ~ I I <1 5: 1 4 > I <1 5 : 1 4-> I <1 5: 1 4 > I I
Il~-------I--------I-------- --------I------~-f-~------I I
Cur rent I / ORed I ORed / loaded loaded I lo'aded~ I ~ loaded I I
Mode 11 from I from / from from I from I from,;. I /
PS <15: 14> :/ I~···:=sta.·ck I stack / stack I vecto,( t vector I I
vecto r·
I I-------- / -------- I-------- -------- I-------- I---~;- ... -- I I
J-ll ,PROGRAMMER'S REFERENCE

T-a'ble 3-1 (continued)

PS PROTECTION
r.

I 1-:....;...;...;..--1---.... ----1--------1 1------- I --------1-------- bt. ....~-.'-:'-.-;-----I I

11 ~XPLICIT PS ACCESS I I MTPS II POWER UP 1 I
PS~Bi t(~) ·11 ,User I! Super f Kernel II User I Super I Kerne_l.L:I~,."'f;~· I I
--:7---"'!":-~-·- I J~..;.-~..;...;..,.;;. ,--------...;. - ... - - - - - - I 1------- I -------- I ----~~ Ll-~-------- I I
Conq.i;t,ion :JI loaded I . loaded loaded I 1 loaded I loaded I loade-& ·,k:.l ", I I
Cod~s ) I from I from from I I from I from I from 1 1 ~leared I I
PS'. <3: 0>. ,JI so~~rc~l sO,ur{ce source I I sourcel source I sour~e I :t.: II
~ " ·1 I------T~:l-.;..-~-.;...;..- --------1 I-------I-----.:...--I-'"-~ .... ~...;;--I t·_.J...;.:...':'-_l..---1 I
TraP'Bit, .II un7' .l,'un-: un- II un- 1 un- I Un":'::.i ~q,1::'~,':·~'· II
PS <4> Ilchangedl changed changed I Ichangedl changed I changedl I cleared I I
11---.;..-..:.-1-.;..------ --------1 I-------I--------I~----~~-I I~~--------l I
Processor;~~~.loadedl~leaded loaded I I un- I un- I loa~ed 11-depends I I
~riority I I from 1 from from Ilchangedl changedl frbm "on power I I
P$' <7 : 5> I I so u r ~ e I so u r c e so u r c e I I I I so u r c e l l up 0 P t ion I I
. I 1---~-.;.:.·-1--------1--------1 1-------1--------1--------1 1--'--------1 I
CIS.,;< .. · ~ ,:,1 L loaded.,l_-loaded I .. loaded II not I not '"- , ~I - net:,· ·,,·-i,i·· ... · I I
Suspend Bit' from ftom 1 from I I acces-l acces- , acces~ 1 I· cleared I I
PS <8> 1 source source 1 source II sible I sible 1 sible II ,'~ ; I I
: I -----.;....;. -~------I--------I 1-------1--------1--------1 I-~--------I 1
Register 1 I loaded loaded , loaded I not I not I not II -,.... II
Select 1 from from I from I acces-I· acces- I acces-~~-I ('··cleared I I
PS <11> I source source I source I sible I sible I sible II -, I I
1 - - - - - - - -----7"--1--------1 -------I----- .... --I--:.-==-.:...~-i T::.-:..--------I I
Previous . I loaded loaded I loaded I not I not I not II
Mode 1 from from 1 from 1 acces-I acces':'" I 'acces~ . . -I-I·-cleared
PS <13: 12>' 1 source source I source I sible I sible I sible II. I I
1 ------- ;..-------1--------1 ------- I -------- (:~-..:-=-..:-- f ----------I I r. .
Current 1 loaded loaded I loaded I not I not I not t I cleared
I I
MO'de I from from I from I acces-I acces- I ac'ces-' 1r~f.e. ,
I I
PS <15: 14> I source source I source I sible I sible I sible II
II kernel
1 I 1 I I' ""·-rr'
I I
mode
I ------- --------1--------1 -------I--------I------~-I I,~~--------I I
 J-ll PROGRAMMER I S REFERENCE

3.3 program Interrupt Request Register - ~IRQ (1777777~)

The Program Interrupt Request Register (PIRQ) implements q software

. ,i nte-r-r·. upt· fac i lity.

A request is queued by setting one of the bits <IS: 9> 'wh1ch corresponds
- ··to a~'prog-r'am -interrupt request at levels 7-1. Bits <T·:5)~·':'"and '("3-11') '~a.r-e
set by hardware to the encoded value of the highes~'pendin~ re~ue~~sai. .. • "# .• ~

When the ~prog~am interrupt request is granted~ ~the :~rbcessortra~s~

t h t..o~ug. h . 1 Q c;; a t ion ' 2 4 0 • It i s the i n t err up t: sa rv iCe r 0 uti n e ' s
responsibility·' to clear the appropriate bit in PIRQ_b~f~re' e~iting'•.
. .15 14 .. -13,12 11 10 9 8 7 -5- . ~ 4' • '3 1
+~--------------------------------------------~~~-~~~----~----~~-~~~~~
,I ~: ' J. . I/ / / 1 - 1//11 ; Jf I 1: J
1~ I 1~,~ 'I , I , I/ / / I i / (1 ~t '. " - I / / l"
,.J .... '" '. .. -, '. , ,.,,' I I 1// / I ; ~ .J 1//1 . r/ /1 J
~ I f· ~ J ,
+--------~-~----------------------------------~~~~~~~~----~-------~~;+
, .1
,,
1 I
PIR 7 I t .
- . ,~,I -- - oJI ~ . _.J- . II I
PIR n , I
I
I
I
I.
' 1
I
I
I ,
PIR 5 .1 t. I t I
PIR 4 , l
I
I I
l
I
I
:~" :.,; ':
~

PIR 3
- .' ::-
, I I'
I
I,
I I
PIR 2:- -I I
I I
PIR 1 I I
I I
Priority encoded value of bits <15:9> -I I
PIRQ bits <15:9> are read/write; bits <7:5,3:1> are read only; the
remaining bits always read as zeroes. PIRQ is cleared at power up, by a
console start, and by a RESET instruction.
J-11 PROG~AMMER'S REFERENCE Page 11.: "

3.4 CPU Error Register (17777765)

This register identifif,!s the source of any abort or trap that cal!sed a'"
trap through location 4~
15 8 7 0 5 4 3 -.2 1 0'
~~~--~-----~------------------------------------------------~---+
'- - II) 11 I I I // 1/ / / / / I / / I / / / / /1 / I / /1/ I . I , 1-1// II I / J"
1//11/1//1/////1/111/1/1/1/111111 I il/ili/iit
I1111111111111111111111111111111I I 11/111/11
+-------~---~-------~--------------------------------------~~-~~~
I
IJ.l¢g,al~ ~Hl\,L.! ___
. , '___".-"....'...;.,'
-+-'!_ _ _ _ _ _ _ __ I
I
Add ress Er [-0 r .I
I
Non-exi?tent~Memp~y~ __________________ ·1
" I
I/O Bus, Timeo,u:t ,-.: I,
~------------------------------------
I
Yellow Stack Violation I
----------------------------------- I
Red Stack Violation ~ ~ I
----------------------------------------- ," <

BIT NAME FUNCTION

-'-'- \'. ." ~-

7 Illegal HALT Set when execution of a HALT instruction

(RO) is attempted in user or ~upervisor mode.
Address Error Set when word access to an odd byte
(RO) address or an instruction fetch from an
internal register is attempted.
5 Non-existent Me~ory Se t when a reference to rna i'n, memory.
(RO) times out.
4 IIO Bus Timeout Set when a reference to the IIO page
(RG) times out.
3 Yellow Stack Trap (RO) Set on a yellow stack trap.

2 Red Sta~k-Trep (RO) Set on a red stack trap.

The CPU Error Register is cleared by any write reference. It is also

c lea red a t po we r up 0 r b y co n so 1 est art. It i s una f f e c ted by aRE SET
instruction.
NOTE: This register is identical to the 11/70. The 11/44 includes
several additional transient status bits. Note that the
defi,niti.on.of addr~_s.s trap has been expanded to inc=l,,!~e
instruction fetcnes from an internal reg ister, and that, the
definition of stack trap has also been changed.
 J-II-PROGRAMMER'S REFERENCE Page 12

3.5 Stack Protection

The' J':"11 checks ke rnel stack references aga inst a 'f i xed 1 iin i t /) f 400 (8.) ._,
If the virtual address of a kernel stack reference is less th~n 4'A(8),
a yellow stack trap occurs at the end of the current instruction (except
for CIS instructions, which abort at the start of instruction
I execotion). A' ~stack trap can occur only on a kernel sta-ck' ref~rence, ,.
which is' defined as a kernel mode 4 or 5 reference through R6, a CIS ppj'
stac~ push, or a JSR, trap, or interrupt stack push. ' ~

IIn add i" t i on , the J -11 c h ec k s for k ern e 1 s t a c k a bo I" t s" d'di'log' ' i rt t err u pt ,
trap, or abort sequences. If a kernel stack push during an .!:in1;:errupt,
trap, or abort causes an abort, the J-ll initiates a r"ed-.".-'z,one· stack~ t'rap--
by creat ing an emergency stack at loca tions 2 and 0 , setting bi t <2,> "qf,
the CPU Error Register, and vectoring through 10cat.iQn 4~.,.-.. '

NOTE: The J-ll treatment of yellow stack t I" ap.i s',-c-iden t ieai . to fhe'
11/44. The 11/70 includes a stack limit register, and a.mor~
inclusive definition of a stack reference. Tl1-g.c~-;.lI's'd'efinition
of a red stack trap is unique.

3.fi Kernel Protection

In order to protect the kernel operating system against interference','

the J-l1 inco~porates a number of protection mechanisms:

- Ink ern elm 0 de, HA LT , RES ET , and S P Lex e cut e as

specified. In supervisor or user mode, HALT causes
'-a trap through location 4, while RESET and SPL'are
tre'a ted as Naps.

- In kernel mode, RTI and RTT can al ter PS <15: 11>

and PS <7:5> freely. In supervisor or user mode,'
RTI and RTT can only set PS <15: 11> and cannot
alter PS <7:5>.

- In kernel mode, MTPS can alter PS <7:5>. In

supervisor or user mode, MTPS cannot alter PS
<7 : 5>.

- All trap and interrupt vector references' are'

classified as kernel data space references,
irrespective of the memory management mode at the
time of the trap or i n t e r r u p t . - .
· c., .'~

- Kernel stack references are checked for stack

overflow. Supervisor and user stack references are
not checked.

Th es e . pro t e c t ion me c han i sm s a I" e f u 11 yeo mpa t ih1 e _wit h t De 11/4 4 and
11170. :'.,
J-l1 PR:OGR"AMMER' S REFERENCE Page 13

4.0 MEMORY MANAGEMENT

Th e -, J -11 " imp 1 em e n t s 11 I 4 4 -11 I 70 com pat i b 1 e mem 0 r y man a gem e n t • "Th i s'
features:

- 22 bit physical address translation.

- In~truction and data (liD) address spaces.

- Kernel, supervisor, and user (K/S/U) processor modes.

NOTE: No I/O map is, supplied with the J-ll chip set. It is _coupled
with t~e UNIBUS adapter module, if any.

Th e vis i b Ie' me rn 0 r y man age rn en t s tat e con sis t s 0 f 4 8 ~ P g' e ~'Ad d ~':s s~ a
Registers (P~Rs), 48 Page Descriptor Registers (PDRs), and four Memory
Management Re9isters (MMR0-3).

4.1 Page Address Registers - PARs

The page Address Registers (PAR?) contain the In-bit Page Address Field
(PAF) ~

+__
15 ____ ___ ______ .-_ . . __________________________________________ '...:.J.+
~ ~- ~

~ .. , -, I
PAF I
I
+----~--~~~~-?~-~-----~-----------------------------------~------+
All bits- are reao/wrlte. These registers are not affected by console
star"t -or-. . . ....a'RE"SE't'<'in-tst-ruction.
c:-
Their state at power up is UNDEFINED •
,-' i .~
J-ll PROGRAMMER'S REFERENCE Pa·ge 1.4·

4.2 Page Descriptor Registers - PDRs

The Page Descriptor Registers (PDRs) contain information relative to

page expansion, page length, and access control.
15 14 8 7 5 4 3 2 :' 1 o_
+---------------------------------------------------------~~---~-+
I I 11111 111111111 I :1//11
I I PLF I111I W IIIIIIIIIED I 11111
ACF
I I I1111 I1111111I 11/1/1
+~---------------------------------------------------------------+
~.J.'"': ': .' I I
Bypass Cache .1 -I-
I r
Pag··~ .:Length, Field _ _ I I
~ (,.: 'j -:. .... - ~ I 'I
Page Written I L
I I'
Expansion Direction .I I
----------------------------------~
Access Control Field
----------------------------------------~-
BIT NAME FUNCTION
15 Bypass Cache This bit implements a conditional cache
- (RW.) bypass mechanism. If set, re~~rence~_t~
the selected virtual page will bypass the
cache.

14:8 Page Length Field This field specifies.th~_b19Gk numb~r. ~

(RW) which defines the boundary of the current
page. The block number of th.e virtual;.
address is compared" agains~ the -Page. LerigtJi
Field to detect length errors. An err"or' .
occurs when expanding upwards if the block
number is greater than the Page Length
Field, and when expandfng downwards if the
block number is less than the Page Length
Field.
Page Written This bit indicates whether or not this
(RO) page has been modified (i.e. written into)
since either the PAR or PDR was loaded (1
is affi rmative). It is useful in
applications which involve disk swapping
and memory overlays. It is used to
determine which pages have been modified
'and hence must be saved in their new form
and which pages have not been modified and
can simply be overlaid.
This bit is reset to 0 whenever either the
PDR or the associated PAR is written into.
J-ll PR-OG~AMMER' S REFERENCE Page 15

3 Expansion Direction' This bit specifies in which direction'

(RW) the page expands. If ED=0 the page expands
upwards from block number 0 to include
blocks with higher addresses i if ED=!:, the,
page expands downwards from block number
127 to include blocks with lower addresses.
Upward expansion is usually used for ---~
program space while downward expansion is
used for stack space.

2.:...1 ... '.....·Ac c e,s s· _,-(:·0 n tr·,Q I This field contains the access rights-tQ:
Field (RW) to this particular page. The access codes
or "keys" specify the manner in which a j:
page may be accessed and whether or not a,
given access should result in an abort'of.
the current operation. The access codes'
are:

00 Non-resident - abort all accesses

01 Read only - abort on writes
10 Not used - abort all accesses,
11 Read/write ~

Th e s e r e g is t e r s are not a f f e c ted by conso Ie s ta rt 0 r a ·RESET-

instruction. Thei r state at power up is UNDEFINED. All un'used bi ts
re~d as zero arid cannot be written.

NOTE: The J-l1 PDR's are identical to the 11/44 PDR's. The--,J-ll,:,-cJ
eli min a t: e~~:r "t h e II/70's "A" (any access) status bit, 'adds the
~ypas.s ca'che bit, and only supports 11/70 access modes ':0, ,2., ',ana r.

'1): --":1:n' -addit16n, "the J-l1 sets the W (page written) bit on writes
which cause aborts or modify internal registers, while th~ 11/44
and 11/70 do not.
J-ll PROGRAMMER'S REFERENCE

4.3 Memory Management Register 0 - MMR0 (17777572)

:., ") "

MMR0 con'tains error flags, the page number whose reference caused the
abort~ and various other status flags.

15,::' - 14 13 12 4 3 7 1 5
+-~--~----------------------------------------------------~-~~---~---+
·I~ - I I 1111111111111111111111111111 I 1 1 1
I I I 1111111111111111111111111111 I 1 I 1
I I 1 II I I I I I I I I I I I I I I I I I I I I I I I I I I 1 I. "I I,
+;.;.. ,;.-;;,..~ ------ -- -- -- -- - -- -- - - ---- ---- -- -- -- -- - - -- -----.,--- --- -- --- ---- --~
1- -' J
+
Abort I I'
Non-<:; -t'.:, - I
Res.~I,' - f
::. - '. t.
Abort-Page I
Length I
Er ro rc:, ,': ' I,

Abort-Read'
Only Error
---
Process'o r Mode
--------------------------------------
Page Space ________________________________________________

page,Number________________________________________________~~~~
::""',"

BIT NA-ME

15 Abort - Non Resident Bit 15 is set by attempting to access

(RW) a page with an Access Control Field key
equal to 0 or 2. It is also set by
attempting to use memory relocation with a
processor mode (PS<15:14» of 2.

14 Abort - Page Length Bit 14 is set by attempting to access a

(RW) location in a page with a block number
(virtual address bits <12:~» that is
outside the area authorized by the Page
Leng th Fi eld of the Page Descr i ptor
Register for that page.

13 Abort - Read Only Bit 13 is set by attempting to write in a

(RW) "Read Only" page. "Read Only" pages have
access keys of 1.

Note that bits <15:13> can be set by an explicit write; however such an
action does not cause an abort. Whether set explicitly or by an abort,
bits <15: 13> cause memory management to freeze the contents of
MMR0<15: 13, /): 1>, MMRl, and MMR2. The status registers remain frozen
until MMR0<15:13> are cleared by an explicit write or any initialization
sequence.
J-11 PROGRAMMER'S REFERENCE Page -1'7

6:5 Processor Mode Bits <~:5> indicate the processor mode

(RO) (kernel/supervisor/user/illegal)
assoc i a ted wi th the page ca us i ng the abo'rt"-
(kernel = 00, supervisor = OJ1, user ='-11,': .,
illegal = 10). If the illegal mode is - ..
specified, an abort is generated and bit
<15> is set.
4 Page Space Bit 4 indicates the address space (I or D)
(RO) associated with the page causing the abort
(0 = I space, 1 = D space) •
3:1' .Page Number Bits <3:1> contain the page number- of " the
(RO) page causing the abort.
o "Enable Relocation Bit OJ en a b 1 e s reI 0 cat ion. Wh e nit is" set
,( RW) . " ,. " - to 1, all addresses are relocated. -.- When
bit 0 is se t to OJ, memo ry managemen't' is:'
inoperative and addresses are not '" '
relocated.

I lnstructlon.
~MR0<15:~3,0> is cleared at power up, by a console start, and by a RESET
MMROJ<f1: 1> is UNDEFINED at power up. .....
NOTE: The J-l1 eliminates the 11/44-11/70 maintenance mode feature, and
the 11/70 memory management trap and instruction complete
features. The J -11 and 11/44 upda te MMROJ< n: 1> on references .. to
: in t e rna I pro c e s so r reg i s t e r s i t he 11/7 0 doe s no t • Th e 11/4 4
'sets onlY_f:':1.MR0<15> on an abort due to the illegal processor mode;
the 11/70 sets MMR0<15:14>; the J-11 sets MMROJ<15>, but the state
of MMR~<~1:~3> is unpredictable •

•- • .>-

4.4 Memory Management Register 1 - MMRI (177777574)

MMR1 records any auto increment or decrement of the general purpose

registers; ·This register supplies necessary information needed to
recover f~om a:memory management abort.
15 11 10 8 7 3 2 -"
+----'-:'~-~~~-~. ~~{~.'T~--~-~-~------------------------- -----------.-:...::.------+

+- - ---~-.... ------~ ... ~-~-...;---- ------------ -- -- - -- - - - -- - -- -- --------- -- -- - --+

I I I
Amount:Changed . -- ~ / '/
(in 2 '.9 complement I I I
Inotation) I I I
/
Register Number I
MMRI is read only. Its state at power up is UNDEFINED.
J-ll PROGRAMMER'S REFERENCE Page 18

4.5 Memory Management Register 2 - MMR2 (17777576)

MMR2-is loaded with the virtual address at the beginning of each

inst-ruction fetch. MMR2 is read only. Its state at power up is
UNDEFINED.

NOTE: The 11/70 also loads MMR2 with the vector during an interrupt or
trap.

4.6 Memory Management Register 3 - MMR3 (17772516)

MMR3 enabl'es or disables D space, 22-bi t mapping, the C9M '·.inst ruction,
and the I/O map (when applicable) •

.::.15 4 3 _25
+-----~------------------------------------------------------~-~--+
1///111//////////////////////////////////1 I I I I I I
1////////////////////////////////////////1 I I I I I I
1////////////////////////////////////////1 I , , 1 , 1
+----------------------------------------------------------------+
I 1 It'
Enable I/O Map_________________________________ , , , I I
I I I I
Enable 22-bit Mapping _______________________________ , , I I
, I I ,
Enable ,CSM Instruction , , I
-------------------------------- I I
Enable '.Kernel Data Space , I
I
Enable Supervisor Data Space
------------------------------------- ,
Enable User Data Space
-----------------------------------------------
BIT NAME FUNCTION

5 Enable I/O Map This bit enables the I/O map on an

(RW) ex,ternal UNIBUS adapter:"if any.

4 Enable 22-bit Mapping This bit enables 22-bit memory

,., (RW) addressing (the defaule~is_ '18--bi t
addressing) •

3 Enable CSM Instruction This bit enables recognition of the

(RW) Call Supervisor Mode -instruc~iert~

2:0 Enable Data Space These bi ts enable Data Space_ m~ppingt .,.'
(RW) for kernel, supervisori and user modej
respectively.

MMR3 is cleared at power up, by a console start, and by a RESET

instruction.

NOTE: No I/O map is supplied with the J-ll. It is coupl ed wi th the

UNIBUS adapter module, if any.
J-ll PROGRAMMER'S REFERENCE Page 19

4.7 I and D Space

When the data space feature is enabled, the J-ll classifies memory
references into instruction (I) and data (D) space references and uses
the cor res po n din g ma pp i ng reg i s t e r s • In g e n era 1 , the follow i ng are
classified as I space references:

- instruction fetches

- immediate operands (mode 27)

absolute addresses (mode 37)

-index w¢>rds
-' inline operands (CIS instructions)

- first references in modes 17, 47, and 57

and all -,-ot-her ~l""eferences are classified as D space. However, MTPI,

MFPI, MTPD, and MFPD behave differently than normal instructions. In
particular, MFPI (if PS<15:12> = 1111), MTPD, and MFPD always force the
last memory reference to D space; while MFPI (if PS<15:12> ~ 1111) and
MTPI always' -for-ce the last memory reference to I space'; Table 4-1
provides an exact description of the interaction of I and D space with
the addressing modes.

Table 4-1
I AND D SPACE OPERATION
(first/second/third memory references)

Address Mode Normal MTPI, MTPO,MFPD,

and Reg Select Instruction MFPI MFPI
(PS <15: 12 > (PS<15:12>
-F 1111) = 1111)

00 - 0; na na na
10 - 16 D I D
17 I I D
20 - 26 D I o
27 I I D
30 36 D/D D/I D/D
37 I/D 1/1 I/D
40 - 46 D I o
- 47 I I o
50 - 56 D/D D/I D/D
57 I/D I/I I/O
60 - 67 I/D I/I I/D
70 - 77 I/D/D I/D/I I/D/D
J-ll PROGRAMMER'S REFERENCE Page 20

5.0 MEMORY SYSTEM

The following highlights the J-ll memory system:

- It can contain a cache.
- It incorporates an instruction stream buffer which'.-
implements a prefetch/predecode scheme.

5.1 Cache

The J-ll supports a physical cache subsystem. Many di'ffe'r::ent~ cache

organizations are possible. The example used here isan,8KB di~ect map
cache with a block size of two bytes. The organi zati6n:of ,- eci'ch' cache
entry (exclusive of parity or other protection mechanism) is:
25 24 In 15 8 7
-+-----------------------------------------"":'
, I
~~--- - -:~.-.~. . . ~:"'--+:-

, V,
I I
~+---~--------------------------------------------~----~--+
I-
Valid
Bit
-----
,
I
I
Tag Field
,,,
----------- I
Data Block - Byte 1
-------------------------
Data Block - Byte 0___________________________________________ ,

The physical address is logically subdivided as follows:

21 12 11 1 0
+----------------------------------------------+
, , , ,
I , I ,
, , , I
+----------------------------------------------+
I ' I
Cache Tag I I '
, I
Cache Index I 'I
Byte Wi thin Block I
J-ll PROGRAMMER'S REFERENCE Page 21

5.1.1 ~a~he_Control Register (1777774~)

The Cac~~,~ontrol Register controls the operation of the cache. Of its

f eat u res;, ' 9 ~ ~ y. byp ass and for cern iss are arc hit e c t u raIl y pa r t 0 f the
J -11 chi P ..:6 e t •. Tag par i t Y , d a tap a r i t y, and c a c h e flu s h , if
impl~:men,t.ed; .. ar~e the responsibility of the control logic around the chlp
set. _

15 11 10 9 8 7 (, 5 4 3 2 1 0
+ ---;...'-....-.------ ---- -- ---------- --- -- - - --- - - -- - - -- - ---- ---- - -- - - - -- -- ---+
11/1/ II;; I 11/;'1 I I I I I I I I I I I I I I I I I I ' I I 1 1
1IIIIIllltll!!!111111111111 1 I I I I I I I 1
111//111//1111/111111111111 I I I I 1 I 1 1 I
+~,:"':';'~:--'';';'~'':'---;...-.-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ------+
~ ~.,
.,.' I I I I I 1 I I I
Write Wrong Tag Parity I I I I I I I I I
I I I I I I I I
Byp-a~'s. Cac~le- . ~" ,_, I I I I I I I I
-~.;.;....;...~------ I I I I I I I
Flush ·'Cach~' I 1 I I I I I
I I I I I I
Enable P~rity Error Abort I I I I I I
-------- I I I I I
Write Wrong Data Parity I I I I I
-------------------------- I I I I
Force Replacement I I I 1
~---------------------------------- III
Force Mis$ 1 I 1
----------------------------------------------- 1 1
Disable Bus Traps I 1
------------------------------------------------- I
Disabie Cache Traps' I

BIT NAME FUNCTION

Write Wrong Tag This bit, when set, causes the cache tags
Parity (f~W) to be written with wrong parity an all
update cycles. This will cause a cache
tag parity error to occur on the next
access to that location.

9 Bypass Cache This bit, when set, forces all CPU memory
(RW) references to go directly to main memory.
Read or write hits will result in
invalidation of accessed locations in the
cache.

8 FI ush Cache Setting this bit causes the entire

(WO) contents of the cache to be declared
invalid. Writing a "0" into this bit will
have no effect.
J-11 PROGRAMMER'S REFERENCE Page 22

7 Enable parity Error This bit controln the response of the

Abort (RW) to a parity error. When set a cache
parity error will cause a forc~ miss_and
an abort to occur. When clear this bit
inhibits the abort and enables an
interrupt to parity error veGtor--,l,l-4'it-' All;
cache parity errors result in force
misses.
6 Write Wrong Data Th is bi t, when set, causes high 'and' -low
Par i ty (RW) pa r i ty bytes to be wr i t ten wi th w.ro~g
parity on all update cycles-' (CPU read
misses and write hits). This will cause a
cache parity error to occur-'on' the next
access to that location. , -

5:4 Force Replacement In a set associative cache, these bi~s,

(RW) when set, force data repla_cemen.t- from mi:lin
memory within one or both cache groups.

3:2 Force Miss (RW) These bits, when either_ i$ set, force all
CPU mem 0 r y ref ere n c est 0 god i r e-c t I Y to
main memory. The cache tag and data
stores are not changed.

1 Disable Bus Traps In a system with separate I/O and memory

(RW) busses, this bit, when set, disables
recognition of parity errors -on the 1/0
bus.
Disable Cache Traps This bit disables cache parity interrupts.
(RW) When set, no interrupt to locatiori 114
will occur when a parity error is
encountered.
If the control logic around the chip set implements cache data parity,
then words read from the cache will be checked for parity. A parity
error in the accessed word causes the following CPU responses:
Bit 7 Bit 0 Action

o o Interrupt to 114 and force miss.

o 1 Force miss only.
1 X Abort and force miss.
Th i 5 reg i s t e r i scI ear e don po we r up 0 r by a con sol e s t art. It is
unaffected by a RESET instruction.
NOTE: The organization of this register reflects the operating system
groups' requests. It differs in some details from both the 11/44
and the 11/70.
J-ll PROGRAMMER'S REFERENCE Page 23

5.1.2 HitlMiss Register (17777752)

This register indicates whether the six most recent CPU memory
references resulted in cache hits or cache misses:

15 5
+--~-----------------------------------------------------------+
1111111111111111111111111111111111111111 I
I111111111111111111111111111111111111111 <---FLOW I
11/111/(1/111111111/11111111111111111111 I
+--------------------------------------------------------------+
Bits ente~·f~om ~~e right (at bit <0» and are shifted leftward. A one
indicates a cache,hit, a zero indicates a cache miss.

The Hi t/Miss Register is read only. Its value at power up is UNDEFINED.

The· Hit/M.iss Register is not affected by console start or a RESET
instruction.

NOTE: The HitlMiss Register is compatible with both the 11144 and the
11/70.

5.1.3 Cache Multi-Processor Hooks

The following multi-processor cache "hooks" exist in the J-ll:

- Conditional cache bypass - selected virtual pages

can be made to bypass the cache. Bit <15> in the
PDRs sets this condition.

- Unconditional cache bypass - all CPU references can

be made to bypass the cache. Bit <9> in the Cache
Control Register sets this condition.

Fl ush cache all valid bits in the cache are

cleared.

- Lock instructions (ASRB, TSTSET, WRTLCK) - these

instructions guarantee a cache bypass reference.
J-11 PROGRAMMER'S REFERENCE Page 24

5.1.4 Cache Response Matrix

The cache response matrix is:

1 CPU 1 1 DMA 1
1-----------------------1
1 Hit 1 Miss 1
1-------------------.;..-.;..-1-
I Hit 1 Miss 1
Read
1-----------------------1
IRead cachedlRead memoryl
1-----------------------1
1 Re a d i R e ad' 1
1 data 1 & allocatel 1 memory 1 memory 1
1 1 cache 1 1 "I _ 1
1-----------------------1 I------~----~-~~-----~--I
Write IWrite thru 1 Write 1 IInvalidate ,'Write ,
I cache to i memory t I cache & I , mem~ry _1
1 memory 1 1 1 wr i tern em " ,- ,
1-----------------------1 I------------~~---------,
Read bypass IInvalidate 1 Read 1 1 na 1 na 1
1 cache & 1 memory 1 1 1 I
1 read mem 1 1 1 I 1
1-----------------------1 1-----------------------1
Write bypass IInvalidate 1 Write 1 1 na 1 na 1
1 cache & 1 memory 1 1 1 1
I write mem 1 1 1 1 1

Read forced
1-----------------------1
I Read 1 Read 1
1-----------------------1
1 na 1 na 1
miss 1 memory 1 memory 1 1 1 1
1-----------------------1 1-----------------------1
Write forced 1 Wr i te 1 Wr i te 1 1 na 1 na 1
miss 1 memory 1 memory 1 1 I 1

5.2 I-Stream Buffer

The J-11 gets much of its performance from a prefetching mechan·ism.
Basically, sequential instruction stream words are prefetched under
microcode control. The J-11 Data Chip Specification details the precise
prefetch mechanism.
J-ll PROGRAMMER'S REFERENCE Page 25

5.3 Memory System Error Register (17777744)

The Memory System Error register details the memory system failure mode.
The Memo~y System Error Register is not part of the J-ll chip set; its
implementat~ion is the responsibility of the control logic surrounding
the ch i p set. -rf implemented, it wo uld have the followi ng fo rma t, 0 r a
subset th"e"reof:

15 14 13 12 11 10 9 8 7 5 4 3 2 1
+--------------------------------------------------------------------+
I -11111/1111111111111111111111111111 I I I III/I
I 111I111111111111111111111111111111 I I I 11I11
-I lllllllllllllllllllllllllllllllill I I I 11111
+-------------------------------------------------------------------~+
I
CPU Abort

Cache Data Parity Error

-----------------------
Cache Tag Parity Error
---------------------------------
Main Memory Data Parity Error
----------------------------------
Main Memory Address Parity Error
--------------------------------------
BIT NAME FUNCTION
15 CPU Abort Set if any of bits <3:1> are set, or
(RO) if any of bits <7:4> are set and Cache
Control Register bit <7> is also set.
7:0 Cache Data Parity Error One or both set if there is a cache
(RO) d a t a p'a r i t Y err 0 r •
5:4 Cache Tag Parity Error One or both set if there is a cache
(RO) tag parity error.
3:2 Main Memory Data One or bo~n set if there is a main
Parity Error (RO) memory data parity error.

1 Main Memory Address Set if there is a main memory address

Parity Error (RO) parity error.

This register is cleared by any write reference. It is also cleared on

power up or by console start. It is unaffected by a RESET instruction.
NOTE: Due to
hardware dependencies, this register differs from the
11/44 Cache Memory Error Register and the 11/70 Memory System
Error Register.
J-ll PROGRAMMER'S REFERENCE Page 26

6.0 FLOATING POINT INSTRUCTIONS

Th e flo a t i ng po i n t i n s t r uc t ion set ( F P-ll ) in the J -11 i s com pIe tel y

software compatible with the FPl1-A used on the PDP-ll/34, the YPll~F 6n
the PDP -11 / 4 4 , the F P 11-Eon the PD P -11/ fi 0 , and the F P ll:-C - on - the.
PDP-ll/70. Both single and double precision floating point ,capability
are available together with other features including floating-to-integer
and integer-to-floating conversion.

The floa t ing po i nt instruc t ion set is impl emen ted e i the r in microcode
res id ing in the base Cont rol ch i p, 0 r ina sepa rate coprocessor. The
coprocessor acts as a floating po int accelerator (FPA) and provides
a p p r ox i mat ely f i v e t i me s the per for man c e o f th e m ic roc 0 d e
implementation.

6.1 Floati~g Point Status Register - FPS

This register provides mode and interrupt control for floating point
instructions and records conditions resulting from the execution of the
previous instruction. Three bits of the FPS register control the modes
of operation:

Single/Double: Floating point numbers can be either single or

double precision.

Long/Short: Integer numbers can be In bits or 32 bits.

Chop/Round: The result of a floating point operation can be either

chopped or rounded. The term "chop" is used instead of "truncate"
in order to avoid confusion with truncation of series used in
approximations for function subroutines.

Th e F PS reg i s t e r con t a ins an err 0 r f 1 a g and f 0 U r con d i t ion cod e s ( 5

bits): carry, overflow, zero, and negative, which are analogous to the
processor status condition codes.

The FP-l1 recognizes six floating point exceptions:

Detection of the presence of the undefined variable in memory

Floating overflow
Floating underflow
Failure of floating to integer conversion
Attempt to divide by 0
Illegal floating opcode.

For the first four of these exceptions, bits in the FPS register are
available to individually enable and disable interrupts. An interrupt
on the occurrence of either of the last two exceptions can be disabled
only by setting a bit which disables interrupts on all six of the
exceptions, as a group.
J-ll PROGRAMMER'S REFERENCE Page 27

Of the thirteen FPS bits, five are set by the FP-ll as part of the
out put 0 f a flo at in g po in t i n s t r u c t ion: the err 0 r f 1 a g and con d i t ion
codes. Any of the mode and interrupt control bi ts may be set by the
user; the LDFPS instruct ion is ava i lable fo r th i s purpose. The FPS
register is formatted as follows:

15 14 13 12 11 10 9 8 7 5 4 3 2 1
+---------------------------------------------------------------+
IF F I111I111I F I F I F I F I F I F I F I111I F I F I F I F ,
J
-I' E I I I111I111I I I I I I I I I D I LIT I111I N I Z I V I C I
IRI D I111I111I
U I U I V I C I I I I111I I I I I
I I I111I111I
V I I I I I I I111I I I I I
+--~------------------------------------------------------------+

BIT NAME FUNCTION

IS, Floating Error The FER bit is set by the FP-ll if

(FER)
l~ Division by zero occurs
2. Illegal opcode occurs
3. Anyone of the remaining occurs and the
corresponding interrupt is enabled.

Note that the above action is independent

of whether the FID bit is set or clear.

Note also that the FP-ll never resets the

FER bi t. Once the FER bi t is set by the
FP-l1, it can be cleared only by an LDFPS
instruction (note the RESET instruction
doe s not c 1 ear the FER bit). Th ism e an s
that the FER bit is up to date only if the
most recent floating point instruction
produced a floating point exception.

14 Interrupt Disable If the FID bit is set, all floating

(FID) point interrupts are disabled.

NOTES
1. The FID bit is primarily a maintenance
f eat u r e • I t s h 0 u I d no rm a 11 y be c 1 ear.
In particular, it must be clear if one
wishes to assure that storage of -0 by
the FP-ll is always accompanied by an
interrupt.

2. Th r 0 ug h 0 u t the res t 0 f t his c hap t e r, i t

is assumed that the FID bit is clear in
all discussions involving overflow,
underflow, occurrence of -0, and integer
conversion errors.
J-ll PROGRAMMER'S REFERENCE Page 28

13 Reserved for future use.

12 Reserved for future use.

11 Interrupt on An in t err up t 0 c cur s i f F I UV i s s e t a n d a

Undefined Variable -0 is obtained from memory as an operand
(FIUV) of ADD, SUB, MUL, DIV, CMP, MOD, NEG,
ABS, TST, or any LOAD instruction. The
interrupt occurs before execution on all
instruct ions. When FIUV is reset, -0 can
be loaded and used in any FP-ll operation.
Note that the interrupt is not activated by
the presence of -0 in an AC operand of an
arithmetic instruction; in particular, trap,
on -0 never occurs in mode 0.

A result of -0 will not be stored without

the simultaneous occurrence of an
interrupt.

10 Interrupt on When the FlU bit is set, floating

Underflow underflow will cause an interrupt. The
(FlU) fractional part of the result of the
operation causing the interropt will be
co r rect. The bi ased exponent wi 11 be too
large by 400 , except for the special case
8
of (/I , wh i c h i s cor r e ct. An ex c e p t ion is
discussed later in the detailed description
of the LDEXP instruction.

If the FlU bi t is reset and if underflow

occurs, no interrupt occurs and the result
is set to exact 0.

9 Interrupt on When the FIV bit is set, floating overflow

Overflow will cause an interrupt. The fractional
(FIV) part of the result of the operation causing
the overflow will be correct. The biased
exponent will be too small by 400 •
8
If the FIV is reset and overflow occurs,
there is no interrupt. The FP-ll returns
exact 0.
J-ll PROGRAMMER'S REFERENCE Page 29

8 Interrupt on Integer When the FIC bit is set and a conversion

Conversion Error to integer instruction fails, an interrupt
(FIC) will occur. If the interrupt occurs,
the destination is set to 0, and all other
registers are left untouched.

If the FIC bit is reset, the result of the

operation will be the same as detailed
above, but no interrupt will occur.

Th e con v e r s ion ins t r u c t ion f ail s i f i t

generates an integer wi th more bi ts than
can fit in the short or long integer word
specified by the FL bit (bit 6).

7 Floating Double The FD bit determines the precision that

Precision Mode is used for floating point calculations.
(FD) Wh ens e t, do ubI e pre cis ion is ass urn e d ;
when reset, single precision is used.

6 Floating Long The FL bit is active in conversion between

Integer Mode integer and floating point format. When
( FL) set, the intege r fo rma t assumed is double
precision 2's complement (i.e., 32 bits).
When reset, the integer format is assumed
to be single precision 2's complement
(i.e., 16 bits).

5 Floating Chop Mode Wh e nth eFT bit i s s e t, the res u 1 t 0 fan y

(FT) arithmetic operation is chopped (or
truncated): When reset, the result is
rounded.

4 Reserved for future use.

3 Floating Negative FN is set if the result of the last (FN)

operation was negative, otherwise it is
reset.

2 Floating Zero FZ is set if the result of the last

(FZ) operation was 0, otherwise it is reset.

1 Floating Overflow FV is set if the last operat ion resul ted

(FV) in an exponent over flow, otherwi se it is
reset.

Floating Carry FC is set if the last operation resulted

(FC) in a carry of the most significant bit.
This can only occur in floating or double
to integer conversions.
J-ll PROGRAMMER'S REFERENCE Page 30

6.2 Floating Exception Code and Address Registers - FEC, FEA

One interrupt vector is assigned to take care of all floating point

ex c e p t ion s ( I 0 cat ion 2 4 4 8) • Th e six po s sib l e e r r 0 r s are cod e din the
4-bit floating exception code (FEC) register as follows:

2 Floating opcode error

4 Floating divide by 0
6 Floating to integer conversion error
8. Floating overflow
10. Floating underflow
12. Floating undefined variable.

The address of the instruction producing the exception is stored in the

floating exception address (FEA) register.

The FEC and FEA registers are updated only when one of the following
occurs:

1. Divide by 0

2. Illegal opcode

3. Any of the other four exceptions with the corresponding

interrupt enabled.

This implies that when and only when the FER bit is set by the FP-ll are
the FEC and FEA registers updated.

NOTES

1. If one of the last four exceptions

occurs with the corresponding
interrupt disabled, the FEC and FEA
are not updated.

2. Inhibi tion of interrupts by the FlO

bit does not inhibit updating of the
FEe and FEA, if an exception occurs.

3. The FEC and FEA do not get updated if

no exception occurs. This means that
the STST (sto re s ta tus) ins t ruct ion
will return current information only
if the most recent floating point
instruction produced an exception.

4. Unlike the FPS register, no

instructions are provided for storage
into the FEC and FEA registers.
J-ll PROGRAMMER'S REFERENCE Page 31

6.3 Accuracy

General comments on the accuracy of the FP-ll are presented here. An

instruction or operation is regarded as "exact" if the result is
identical to an infinite precislon calculation involving the same
operands. The a priori accuracy of the operands is thus ignored. All
arithmetic instructions treat an operand whose biased exponent is 0 as
an exact 0 (unless FIUV is enabled and the operand is -0, in which case
an interrupt occurs). For all arithmetic operations, except DIV, a 0
operand implies that the instruction is exact. The same statement holds
for DIV if the 0 operand is the dividend. But if it is the divisor,
division is undefined, and an interrupt occurs.
For nonvanishing floating point operands, the fractional part is binary
normalized. It contains 24 bits or 56 bits for floating mode and double
mode, respectively. For ADD, SUB, MUL, and DIV, two guard bits are
necessary and sufficient for the general case to guarantee return of a
chopped or rounded result identical to the corresponding infinite
precision operation chopped or rounded to the specified word length.
Thus, wi th two guard bi ts, a chopped resul t has an error bound of one
least significant bit (LSB); a rounded result has an error bound of 1/2
LSB. These error bounds are realized by the J-ll on all instructions.
Both the FPl1-A and the FPl1-E have an error bound greater than 1/2 LSB
for ADD and SUB.

In the rest of this specification, an arithmetic result is called exact

if no nonvanishing bits would be lost by chopping. The first bit lost
inc h 0 pp i ng i s ref err edt 0 as the " r 0 un ding" bit. Th e val u e 0 f a
rounded result is related to the chopped result as follows.

1. If the rounding bit is 1, the rounded result is the chopped

result incremented by an LSB.
2. If the rounding bit is 0, the rounded and chopped results are
identical.
It follows that:

1. If the result is exact,

rounded value = chopped value = exact value

2. If the result is not exact, its magnitude

a. is always decreased by chopping

b. is decreased by rounding if the rounding bit is 0
c. is increased by rounding if the rounding bit is 1.
J-ll PROGRAMMER'S REFERENCE Page 32

Occurrence of floating point overflow and underflow is an error

condition: the result of the calculation cannot be correctly stored
be c au s e t h e e x po n e n t i s too 1 a r get 0 fit in t o t he e i g h t bit s res e r v e d
for it. However, the internal hardware has produced the correct answer.
For the case of underflow, replacement of the correct answer by 0 is a
reasonable resolution of the problem for many applications. This is
done by the J-ll if the underflow interrupt is disabled. The error
incurred by this action is an absolute rather than a relative error; it
is bounded (in absolute value) by 2** (-128). There is no such simple
resolution for the case of overflow. The action taken, if the overflow
interrupt is disabled, is described under FIV (bit 9).

The FIV and FIU bits (of the floating point status word) provide the
user with an opportunity to implement his own correction of an overflow
or underflow condition. If such a condition occurs and the
corresponding interrupt is enabled, the microcode stores the fractional'
part and the low eight bits of the biased exponent. The interrupt will-
take place and the user can identify the cause by examination of the FV
( flo at i n g 0 v e r flo w) bit 0 f th e FE C ( flo at in 9 ex c e p t ion) reg i s t e r • Th e
reader can readily verify that (for the standard arithmetic operations
ADD, SUB, MUL, and DIV) the biased exponent returned by the instruction
be a r s the folIo wi ng reI a t ion t o t he cor r e c t e x po n e n t g e n era ted by the
microcode.
1. On overflow, it is too small by 400 8 •

2. On underflow, if the biased exponent is 0, it is correct. If

it is not 0, it is too large by 400 •
8
Th us , wit h the i n t err up ten a b 1 e , enough information is available to
dete rmine the co r rect answer. The user may, for example, rescale his
variables (via STEXP and LDEXP) to continue a calculation. Note that
the accuracy of the fractional part is unaffected by the occurrence of
underflow or overflow.
J-II PROGRAMMER'S REFERENCE Page 33

7.0 TRAPS AND INTERRUPTS

In both traps and interrupts, the currently executing program is

interrupted and a new program, the starting address of which is
s p e c i fie d by the t rap 0 r in t err up t ve c tor, i sex e cut e d • Th e h a r d wa r e
process for traps and interrupts through a vector V is identical:

PS --> temp 1 !save PS, PC in temporaries

PC --> temp 2
o --> PS <15:14> !force kernel mode
M(V] --> PC !fetch PC from vector, data space
M(V+2] --> PS !fetch PS from vector, data space
templ<15:14> --> PS<13:12> !set previous mode
SP-2 --> SP !selected by new PS
tempI --> M(SPl !push old PS on stack, data space
SP-2 --> SP
temp2 --> M[SP] !push old PC on stack, data space
!go execute next instruction

Note that if an abort occurs during either the vector fetch or the stack
pushes, the PS and PC are restored to their original values prior to
recognition of the abort.

The priority order for traps and interrupts is as follows:

address error
memory management violation
timeout/non-existent memory
parity error
trace (T-bit) trap
yellow stack trap
power fa i 1
floating point trap
PIRQ 7
interrupt level 7
PIRQ 6
interrupt level r)r
PIRQ 5
interrupt level 5
PIRQ 4
interrupt level 4
PIRQ 3
PIRQ 2
PIRQ I
Halt line
J-ll PROGRAMMER'S REFERENCE Page 34

8.0 GENERAL PERFORMANCE GOALS

The overall performance goals of the J-ll are:

- J-ll base instruction performance equivalent to the

11/70.

- J-ll floa t ing po int perfo rmance equal to ha I f of

the 11/44. With an optional floating point
accelerator, the performance will be boosted to
11/70 speeds.

- J-ll CIS performance equal to the 11/44.

9.0 CONSOLE

The J-ll contains console microcode. This will enable a user to access
mo s t 0 f the J -11 s tat e, run d i a g nos tic s, and mo nit 0 r the s y stem. Th e
J-ll console replaces the "lights and switches" programmer's console
with microcode that interprets ASCII characters to perform equivalent
panel functions.

The J-ll console microcode provides the minimum functionality needed to

control the chip set. A more elaborate console protocol can be
implemented using an external console processor. The console processor
would then simulate an external console in order to gain access to the
console microcode and the chip set.

Appendix 4 details the operation of the console.

J-11 PROGRAMMER'S REFERENCE Page 35

10.0 11/44 HARDWARE DIFFERENCES

Th e J -11 i s de s i g ned to replace the 11/44 in existing and future

applications; however, it does not contain the following PDP-11/44
hardware features:

- Cache data and maintenance registers (17777750, 17777754)

- Switch register (17777570).

The J-11 does contain additional functionality not present in the 11/44:

- Dual general register set

- SPL, MTPS, MFPS, TSTSET, WRTLCK instructions.

The following list summarizes the hardware differences between the 11/44
and the J-1l:

Address Function Differences

17 777 776 PS Added register set select bit<11>

17 777 772 PIRQ No difference.

17 777 7'16 CPU Error Unibus monitoring bits

unimplemented.

17 777 754 Cache Data Unimplemented.

17 777 752 Hit/Miss No difference.

17 777 750 Maintenance Unimplemented.

17 777 74h Cache Control Hardware specific changes

(see section 5.1.1).

17 777 744 Memory Error Hardware specific changes

(see section 5.3).

17 777 f)7fl
to User Da ta PAR No difference.
17 777 660

17 777 656
to User Instruction PAR No difference.
17 777 640

17 777 636
to User Data PDR No difference.
17 777 620
J-11 PROGRAMMER'S REFERENCE Page 30

17 777 1116
to User Instruction PDR No difference.
17 777 1100

17 777 576 MMR2 No difference.

17 777 574 MMR1 No difference.

17 777 572 MMR0 Eliminated maintenance mode.

17 777 570 Switch Register Unimplemented.

17 772 5111 MMR3 No difference.

17 772 37fi
to Kernel Data PAR No difference.
17 772 360

17 77.2 356
to Kernel Instruction PAR No difference.
17 772 340

17 772 336
to Kernel Data PDR No difference.
17 772 320

17 772 316
to Kernel Instruction PDR No difference.
17 772 300

17 772 276
to Supervisor Data PAR No difference.
17 772 260

17 772 256
to Supervisor Instruction No difference.
17 772 240 PAR

17 772 236
to Supervisor Data PDR No difference.
17 772 220

17 772 216
to Supervisor Instruction No difference.
17 772 200 PDR
J-11 PROGRAMMER'S REFERENCE Page 37

11.0 11/70 HARDWARE DIFFERENCES

The J -11 is des ig ned to repl ace the PDP-11/70 in existing and future
applications; however it does not contain the following PDP-l1/70
hardware features:

- Stack Limit Register (17777774)

- Micro Break Register (17777770)

- System ID Register (17777704)

- System Size Registers (177777~0, 17777702)

- Maintenance Register (17777750)

- Physical Error Ad?ress Registers (17777740, 17777742)

- Switch Register (17777570).

The J-11 does contain additional functionality not present in the 11/70:

- MTPS, MFPS, MFPT, CSM, TSTSET, WRTLCK instructions

- CIS instructions

Bypass cache bit in PDRs.

The following list summarizes the hardware differences between the 11/70
and the J-11:

Address Function Differences

17 777 770 PS Added suspended instruction

bit <8>.

"'1" "7, 777 774 Stack T':

LI.Lm.L.: L.
~
Unimplemented.

17 777 772 PIRQ No difference.

17 777 770 Micro Break Unimplemented.

17 777 766 CPU Error No difference.

17 777 704 System ID Unimplemented.

17 777 762 System Size Unimplemented.

17 777 760 System Size Unimplemented.

17 777 752 Hit/Miss No difference.

J-ll PROGRAMMER'S REFERENCE Page 38

17 777 750 Maintenance Unimplemented.

17 777 746 Cache Control Hardware specific changes

(see section 5.1.1).

17 777 744 Memory Error Hardware specific changes

(see section 5.3).

17 777 742 High Error Address Unimplemented.

17 777 740 Low Error Address Unimplemented.

17 777 676
to User Data PAR No difference.
17 777 660

17 777 656
to User Instruction PAR No difference.
17 777 ()40

17 777 ()3()
to User Data PDR Added bypass cache, eliminated
17 777 n20 access flags and access modes
other than 0, 2, and ~.

17 777 616
to User Instruction PDR Added bypass cache, eliminated
17 777 ()00 access flags and access modes
other than 0, 2, and 6.

17 777 576 MMR2 No difference.

17 777 574 MMR1 No difference.

17 777 572 MMR0 Eliminated traps, maintenance

mode, and instruction complete.

17 777 570 Switch Register Unimplemented.

17 772 SIt') MMR3 Added CSM enable bit <3>.

17 772 376
to Kernel Data PAR No difference.
17 772 360

17 772 356
to Kernel Instruction PAR No difference.
17 772 340
J-11 PROGRAMMER'S REFERENCE Page 39

17 772 33h
to Kernel Data PDR Added bypass cache, eliminated
17 '7'7')
, 'L- 320 access flag and access modes
other than 0, 2, and h.

17 772 316
to Kernel Instruction PDR Added bypass cache, eliminated
17 772 300 access flag and access modes
other than Cil, 2, and n.

17 772 270
to Supervisor Data PAR No difference.
17 772 2h0

17 772 256
to Supervisor Instruction No difference.
17 772 240 PAR

17 772 23n
to Supervisor Data PDR Added bypass cache, eliminated
17 772 220 access flag and access modes
other than 0, 2, and n.

17 772 21n
to Supervisor Instruction Added bypass cache, eliminated
17 772 200 PDR access flag and access modes
other than Cil, 2, and fie
J-II PROGRAMMER'S REFERENCE Page A-I

Appendix I - J-II Base Instruction Set

Double Operand ADD BISB MOV

Instructions ASH BIT MOVB
ASHC BITB MUL
BIC CMP SUB
BICB CMPB XOR
BIS DIV

Single Operand ADC DEC ROR

Instructions ADCB DECB RORB
ASL INC SBC
ASLB INCB SBCB
ASR MFPS SWAB
ASRB MTPS SXT
CLR NEG TST
CLRB NEGB TSTB
COM ROL
COMB ROLB

Branch Instructions BCC/BHIS BHI BNE

BCS/BLO BLE BPL
BEQ BLOS BR
BGE BLT BVC
BGT BMI BVS

Jump and Subroutine CSM JSR RTS

Instructions JMP MARK SOB

Trap and Interrupt BPT lOT RTT

Instructions EMT RTI TRAP

Miscellaneous HALT MTPD TSTSET

Instructions MFPD MTPI WAIT
MFPI RESET WRTLCK
MFPT SPL

Cond i tion Code CCC CLZ SEN

Operators CLC NOP SEV
CLN. SCC SEZ
CLV SEC
J-ll PROGRAMMER'S REFERENCE Page A-2

Appendix 2 - J-ll Floating Point Instruction Set

Floating Point ABSD LDCLF STCDI

Instructions ABSF LDD STCDL
ADDD LDEXP STCFD
ADDF LDF STCFI
CFCC LDFPS STCFL
CLRD MODO STD
CLRF MODF STEXP
CMPD MULD STF
CMPF MULF STFPS
DIVD NEGD STST
DIVF NEGF SUBD
LDCDF SETD SUBF
LDCFD SETF TSTD
LDCID SETI TSTF
LDCIF SETL
LDCLD STCDF
J-ll PROGRAMMER'S REFERENCE Page A-3

Appendix 3 - J-ll Commercial Instruction Set

Character String CMPC MOVC SCANC

Instructions CMPCI MOVCI SCANCI
LOCC MOVRC SKPC
LOCCI MOVRCI SKPCI
MATC MOVTC SPANC
MATCI MOVTCI SPANCI

Numer ic Str ing ADDN CMPN

Instructions ADDNI CMPNI
ASHN SUBN
ASHNI SUBNI

Packed String ADDP CMPP MULP

Instructions ADDPI CMPPI MULPI
ASHP DIVP SUBP
ASHPI DIVPI SUBPI

Convert Instructions CVTLN CVTNL CVTPL

CVTLP CVTNP CVTPN

Load Descr i ptor L2D0 L3D0

Instructions L2Dl L3Dl
L2D2 L3D2
L2D3 L3D3
L2D4 L3D4
L2D5 L3D5
L2Dh L3Df)
L2D7 L3D7
J-ll PROGRAMMER'S REFERENCE Page A-4

Appendix 4 - Console Commands

4.1 INTRODUCTION

The console microcode (console ODT) is a portion of the processor

mic rocode tha t allows the processor to respond to command sand
information entered via the terminal. The terminal addresses are
1 7 777500 8 through 177775~68. They are generated in microcode and
cannot oe changed. Console aDT is very useful as an a id in
running and debugging programs. Communication between the user
and processor is via a stream of ASCII characters interpreted by
the processor as console commands. These commands are a subset of
ODT-ll.

4.2 TERMINAL INTERFACE

The minimum hardware requirements for a serial line interface

permitting a terminal to communicate with console ODT are
contained in the following paragraphs. The intent is to describe
the min i murn h a r d war e r eq u ire d; t his i s a sub set 0 f the h a r d war e
needed to operate system software. For system softwarelhardware
requirements refer to the DLVll hardware specification.

4.2.1 Receiver Control and Status Register (RCSR)

Th e RCS R ( Fig u r e 4 - 1 ) mu s t e xis t a t add res s 1 7 7 7 7 5 ?) 0 8 for

character input to console ODT. Console ODT does not execute
output bus cycles to this address; therefore, the RCSR only needs
to respond to input bus cycles. However, system software causes
output cycles in order to affect certain bits, such as Interrupt
Enable (bit 6), which console ODT does not use.

15 8 7
+-----~-~======================================-----+

I111111111111111111111111 1111111111111111111111111
1111111111111111111//1//1 D 1111111111111//1/1////1/1
1111111111111111111111111 111111111111111/111111111
+---------------------------------------------------+
Figure 4-1 Receiver Status Register

Bit Description

<7> Done flag. After a character is assembled and exists in

the receiver buffer register (RBUF), the Done flag must
be set to a 1. When an input cycle is performed to the
RB UF ( top i c k up the c h a r act e r), the Do n e f 1 a g mu s t be
c 1 ear e d by h a r d wa r e • Th e s y stem in i t i ali z a t ion s i g n a 1
must also clear this bit.
J-ll PROGRAMMER'S REFERENCE Page A-5

Bit Description

<n:0> Un use d • Th e s e bit s are don' t car e san d can be ina n y

<15:8> state since console aDT does not use them. In DIGITAL
interfaces, these bits may be defined.

4.2.2 Receiver Buffer Register (RBUF)

The RBUF (Figure 4-2) must exist at address 17777Sr..,2 for

character input to console ODT. This register only nee§s to
respond to input bus cycles since console aDT does not execute
output bus cycles to this address. System software interfaces
s im i 1 a r 1 y, . but DIGITAL d i agnost i cs may cause an output cyc 1 e and
not operate properly.

15 8 7
+-------------------------------------------------------+
11111111111111111111111111111 I
I1111111111111111111111111111 DATA I
I1111111111111111111111111111 I
+-------------------------------------------------------+
Figure 4-2 Receiver Buffer Register

Bit Description

<7:0> ASCII character. These eight bi ts are read by the

processor and interpreted as a console aDT command. When
bit 7 of RCSR is a 1, the processor does a input cycle to
the RBUF. After the input cycle, the hardware must clear
bit 7 of RCSR to 0.

<15:8> Unused. These bi ts are don't cares and can be in any

state since console ODT does not use them. In DIGITAL
interfaces, these bits may be defined.

4.2.3 Transmitter Control and Status Register (XCSR)

The XCSR (Figure 4-3) must exist at address 17777Sn4p. for

character output from console ODT. aDT does not execute output
bus cycles to this address; therefore, the XCSR only needs to
respond to input bus cycles. However, system software causes
output cycles to affect certain bits, such as Interrupt Enable,
which console ODT does not use.
J-11 PROGRAMMER'S REFERENCE Page A-t:.,

15 8 7
+--------------------------------------------------------+
11111111111111111111111111 111111111111111111111111111
11111111111111111111111111 D 111111111111111111111111111
11111111111111111111111111 111111111111111111111111111
+--------------------------------------------------------+
Figure 4-3 Transmitter Control and Status Register

Bit Description

<7> Done flag. In the idle state, this bit is a 1 indicating

that the hardware is ready to print a character. After
an output cycle to the transmitter buffer register by the
processor (i.e., a character loaded), thi s bi t must be
cleared to 0 by the hardware. After the character is
p r in ted, the h a r d war e set s t his bit to 1 • Po we r up and
the system bus initialization signal must also set this
bit to a 1.

<~:0> Un use d • Th e s e bit s are don I t car e san d can be i n a n y

<15:8> state since console ODT does not use them. In DIGITAL
interfaces, these bits may be defined.

4.2.4 Transmitter Buffer Register (XBUF)

The XBUF (Figure 4-4) must exist at address 17777S{)t)8 for

characte r output f rom console ODT. Thi s reg i ster onl y neeas to
respond to output bus cycles since console aDT does not execute
input bus cycles to this address. System software interfaces
similarly but DIGITAL diagnostic may cause an input cycle and not
operate properly.

15 8 7 o
+-------------------------------------------------------+
1111111111111111111111111111 I
1111111111111111111111111111 DATA ,
I111111111111111111111111111 1
+-------------------------------------------------------+
Figure 4-4 Transmitter Buffer Register

Bit Description

<7:0> AS C I I c h a r act e r • Th e see i g h t bit s are wr itt en by the

processor with the ASCII character to be printed. When
bit 7 of XCSR is a 1, the processor does an output cycle
to the XBUF. After the output cycle the hardware must
clear bit 7 of XCSR to 0.

<15:8> Unused. These bits are don It ca res and can be in any
state since console ODT does not use them. In DIGITAL
interfaces, these bits may be defined.
J-ll PROGRAMMER'S REFERENCE Page A-7

4.3 CONSOLE ODT OPERATION

The processor's microcode operates the serial line interface in

half-duplex mode. Program I/O techniques are used rather than
interrupts. When the console aDT microcode is printing characters
us ing the transmi t s ide of the in terface, the mic rocode is not
monitoring the receive side for incoming characters. Any
characters coming in at this time are lost. The interface may
post overrun errors, but the microcode does not check for error
bi ts in the interface. Therefore users should not type ahead to
ODT because those characters are not recognized. In addition, if
another processor is at the other end of the interface, it must
obey half-duplex operation. No input characters should be sent
until console ODT has finished outputting.

4.3.1 Console aDT Entry Conditions

aDT is entered under the following conditions:

1. Execution of a HALT instruction in kernel mode.

2. Assert ion of the HALT signal on the system bus. The

signal must be asserted long enough so that it is seen at
the end of a macroinstruction by the service state in the
processor.

3. At power up, if the appropriate power up option is

selected.

4.3.2 Console ODT Input Sequence

Upon entry to console ODT, the RBUF register is read and the
character present in the buffer is ignored. This is done so that
erroneous characters or user program characters are not
interpreted by console ODT as a command, especially when a program
is halted.

The input sequence for console aDT is as follows.

1. Output <CR><LF> to terminal.

2. Output contents of PC (R7) in six digits to terminal.

3. Read and ignore character in RBUF.

4. Output <CR><LF> to terminal.

5. Output the prompt character, @, to terminal.

fi. Enter a wait loop for terminal input. The Done flag, bit
<7> in RCSR, is tested •. If it is 0, the test continues.

7. If RCSR bit <7> is a 1, then low byte of RBUF is read.

J-11 PROGRAMMER'S REFERENCE Page A-8

4.3. 3 Console ODT Output Sequence

The output sequence for ODT is as follows.

1. Test XCSR bit <7> (Done flag) and if a 0, continue

testing.

2. If XCSR bit <7> is a 1, write character to low byte of

XBUF (high byte is ignored by interface).

4.4 CONSOLE ODT COMMAND SET

The console ODT command set, listed in Table 4-1, is described in

the following paragraphs. The commands are a subset of ODT-11 and
use the same command character. Only specific characters are
recognized as valid inputs; other inputs invoke a "?" response.

Table 4-1 Console ODT Commands

Command Symbol Use

Slash / Pr ints the contents of a

specified location.

Ca rr i age Return <CR> Closes an open location.

Li ne Feed <LF> Closes an open location and

then opens the next
contiguous location.

Internal Register $ or R Opens a specific processor

Designator register.

Processor Status S Opens the PS must follow

Word Designator an S or R command.

Go G Starts program execution.

Proceed P Resumes execution of a

program.

Binary Dump Control-Shift-S Manufacturing use only.

The parity bit (bit <7» on all input characters is ignored (i.e.,
not stripped) by console ODT. If the input character is echoed,
the state of the parity bit is copied to the output buffer (XBUF).
Output characters internally generated (e.g., <CR» by ODT have
the parity bit equal to 0. All commands are echoed except for
ASCI I codes in the range 0-17 • Where appl icable, upper- and
8
lowercase of command characters are recognized.
J-11 PROGRAMMER'S REFERENCE Page A-9

Th e wo r d "10 cat ion," as use din the follow i n g sec t ion s, ref e r s to
a memory location, an I/O device register, an internal processor
register, or the processor status word (PS).

NOTE

In the examples the response from the

processor is underlined, while the
user's entry is not.

4.4.1 / (ASCII 057) Slash

This command is used to open a memory location, I/O device

reg i ster, in ternal processo r reg is ter, 0 r processo r sta tus wo rd
and must be preceded by other characters which specify a location.
In response to /, console ODT prints the contents of the location
(i.e., six chara~ters) and then a space (ASCII 40). After printing
is complete, console ODT waits for either new data for that
location or a valid close command.

Example: ~001000/012525<SPACE>

where:

@ = console ODT prompt character.

001000 = octal location desired by the user

(leading 0s are not required).

/ = command to open and pr int contents of

location.

012525 = contents of octal location 1000.

<SPACE> = space character generated by console

ODT.

4.4.2 <CR> (ASCII 015) Carriage Return

This command is used to close an open location. If a location's

contents are to be changed, the user should precede the <CR> with
the new data. If no change is desired, <CR> closes the location
without altering its contents.

Example: @R1/004321<SPACE> <CR> <CR><LF>

@

Processor register R1 was opened and no change was desired so the

user i ssued<CR>. In response to the <CR>, console aDT pr in ted
<CR><LF>@.

Example: @R1/004321<SPACE> 1234 <CR> <CR><LF>

@
J-II PROGRAMMER'S REFERENCE Page A-10

In this case the user desired to change RI, so new data, 1234, was
entered before issuing the <CR>. Console aDT deposited the new
data in the open location and then printed <CR><LF>@.

Console aDT does not directly echo the <CR> entered by the user
but instead prints a <CR>, followed by a <LF>, and @.

4.4.3 <LF> (ASCII 012) Line Feed

This command is used to close an open location and then open the
next contiguous location. Memory locations and processor
registers are incremented by 2 and 1 respectively. If the PS is
open when a <LF> is issued, it is closed and a <CR><LF>@ is
printed; no new location is opened. If the open location's
contents are to be changed, the new data should precede the <LF>.
If no data is entered, the location is closed without being
altered.

Example: @R2/12345h<SPACE> <LF> <CR><LF>

R3/054321<SPACE>

In this case, the user entered <LF> with no data preceding it. In
response, console ODT closed R2 and then opened R3. When a user
has the last register, R7, open, and issues <LF>, console aDT
opens the beginning register, R0.

Example: @R7/000000<SPACE> <LF> <CR><LF>

R0/12345n<SPACE>

Unl ike wi th most other commands, console ODT does not

echo the <LF>. Instead it pr ints <CR>, then <LF>, so
that terminal printers operate properly. In order to
make this easier to decode, console ODT does not echo
ASCII characters in the range 0 - 17 8 .

4.4 .. 4 $ (ASCII 044) or R (ASCII Internal Register

Designator

Either character when followed by a register number, 0 to 7, or PS

designator, S, will open that specific processor register.

The $ character is recognized to be compatible with ODT-11. The R

character was introduced for the convenience of one key stroke and
because it is representative of what it does.

Example: fS0/000123<SPACE>

or

@R7/000123<SPACE> <LF>
R0/054321<SPACE>
J-ll PROGRAMMER'S REFERENCE Page A-II

If more than one character is typed (digit or S) after the R or S,

console ODT uses the last character as the register designator.

4.4. 5 S (ASCII 123) Processor Status Word

This designator is for opening the PS (processor status word) and

may be employed only after the user has entered an R or S register
designator.

Example: fRS/100377<SPACE> 0 <CR> <CR><LF>

Note the trace bit (bit <4» of the PS cannot be modified by the
user. This is done so that PDP-II program debug utilities (e.g.,
ODT-ll), which use the T bit for single-stepping, are not
accidentally harmed by the user.

If the user issues a <LF> while the PS is open, the PS is closed

and ODT prints <CR><LF>~. No new location is opened in this case.

4.4.6 G (ASCII 107) Go

Th i s command is used to sta r t prog ram execut ion a t a locat ion

entered immediately before the G. This function is equivalent to
the LOAD ADDRESS and START switch sequence on other PDP-II
consoles.

Example: @200G<NULL><NULL>

The console ODT sequence for a G, after echoing the command

character, is as follows.

1. Print two nulls (ASCII 0) so the bus initialize that

follows does not flush the G character from the
double-buffered UART chip in the serial line interface.

2• Lo a d R7 ( PC) wit h the en t ere d d a t a • If nod a t a i s

entered, 0 is used. (In the above example, R7 is set to
200, and that is where program execution begins.)

3. The PS, MMR0<15:13,0>, MMR3, PIRQ, CPU Error Register,

Memory System Error Register, Cache Control Register, and
Floating Point Status Register are cleared to zero.

4. The cache, if present, is fl ushed.

5. The system bus is initialized by the processor.

6. The service state is entered by the processor. If there

is anything to be serviced, it is processed. If the bus
HALT signal is asserted, the processor reenters the
console ODT state. This feature is used to initialize a
system without starting a program (R7 is altered).
J-ll PROGRAMMER'S REFERENCE Page A-12

4.4.7 P (ASCII 120) Proceed

This command is used to resume execution of a program and

corresponds to the CONTINUE swi tch on other PDP-II consoles. No
programmer-visible machine state is altered using this command.

Example: @P

Program execution resumes at the address pointed to by R'. After

the P i s e c hoe d, the pro c e s so r i mm e d i ate 1 yen t e r s the s tat e to
fetch the next instruction. After the instruction is executed,
outstanding interrupts, if any, are serviced. If the HALT bus
signal is asserted, it is recognized at the end of the
instruction, and the processor enters the console ODT state. Upon
entry, the content of the PC (R7) is printed. In this fashion,
the user can single-instruction step through a program and obtain
a PC "trace" on the terminal.

4.4.8 Control-Shift-S (ASCII 023) Binary Dump

This command is used for manufacturing test purposes and is not a

normal user command. It is described here to explain the
pro c e s s 0 r' s res po n s e i f a c c i d en tall yin v 0 ked. It i s i n ten de d to
more efficiently display a portion of memory compared to using the
"I" and <LF> commands. The protocol is as follows.
1. After a prompt character, console ODT receives a
control-shift-S command and echoes it.

2. The host system at the other end of the serial line must
send two 8-bit bytes which console ODT interprets as a
starting address. These two bytes are not echoed.

The first byte specifies starting address <15:08> and the

second byte specifies starting address <07:00>. Address
bits <21:16> are always forced to be 0; the dump command
is restricted to the first 32K words of address space.

3. After the second address byte has been received, console

ODT outputs ten bytes to the serial line starting at the
add res s pre v i 0 us 1 Y s P e c i fie d • Wh e n t h e 0 u t put i s
finished, console ODT prints <CR><LF>@.

If a user accidentally enters this command, it is

recommended, in order to exit from the command, that two
@ characters (ASCII 100) be entered as a starting
address. After the binary dump, an @ prompt character is
printed.
 J-11 PROGRAM~ERrs REFERENCE Page A-13

4.5 ADDRESS SPECIFICATION

All I/O addresses (17 7~0 000 to 17 777 777) must be entered by
users with all 22 bits specified. For example, if a user desires
to open the RCSR of the console serial interface he must enter
177775~0, not 1775~0, or 777Sfi0 •
•
4. S. 1 General Registers

Accessing the general reg ister sets 'is accompl ished in the
following way. Whenever R0-RS are referenced in console ODT, they
access the general register set specified by the PS register set
bit (PS<ll». If a program operating in general register set zero
(PS<ll> = 0) is halted and a general register is opened, register
set zero is accessed. Similarily, if a program is operating in
register set one, "R0-R5" accesses register set one.

If a specific register set is desired, PS<ll> must be set by the

user to the appropriate value, and then the "R0"-"RS" commands can
be used. If an operating program has been hal ted, the or ig inal
value of PS<ll> must be restored in order to continue execution.

Example: PS = 000000

!R4/05252S<SPACE> <CR> <CR><LF>

R4 in register set zero has been opened.

@RS/000000<SPACE> 4000 <CR> <CR><LF>

@R4/177777<SPACE> <CR> <CR><LF>
!RS/004000<SPACE> 0 <CR> <CR><LF>
@P

In th i s cas e, R4 i n reg i s t e r set 0 n e wa s des ire d • Th e PS wa s

opened, and PS<ll> was set to 1 (register set one). Then R4 was
examined and closed. The original value of PS<ll> was restored,
and then the program was continued using the P command.
J-ll PROGRAMMER'S REFERENCE Page A-14

4.5. 2 Stack Pointers

Accessing kernel, supervisor, and user stack pointer registers is

accompl i shed in the followi ng way. Whenever Rt) is re f e renced in
console ODT, it accesses the stack pointer specified by the PS
current mode bits (PS<15:14». If a program operating in kernel
mode (PS<15:14> = 00) is halted and R6 is opened, the kernel stack
pointer is accessed. Similarly, if a program is operating in
supervisor or user mode, "Rn" accesses the supervisor or user
s t a c k po in t e r s •

If a specific stack pointer is desired, PS<15:14> must be set by

the user to the appropriate value and then the "Rn" command can be
used. If an operating program has been halted, the original value
of PS<15:14> must be restored in order to continue execution.

Example: PS = 140000

fR6/123456<SPACE> <CR> <CR><LF>

The user mode stack pointer has been opened.

@RS/140000<SPACE> 0 <CR> <CR><LF>

@Rn/123456<SPACE> <CR> <CR><LF>
!RS/000000<SPACE> 140000<CR> <CR><LF>
@P

In this case, the kernel mode stack po inter was desi red. The PS
was 0 pe ned, and PS <1 5 : 14 > we r e s e t to 00 ( k ern elm 0 de). Th en R n
wa sex ami ned and c los e d • Th e 0 rig ina 1 val ue 0 f PS < 1 5: 1 4 > wa s
restored, and then the program was continued using the P command.

4.5.3 Floating Point Accumulators

The flo at i ng po in t a c c urn u 1 a tor s can not be a c c e sse d fro m con sol e
ODT. Only floating point instructions can access these registers.

4.'1 ENTERING OCTAL DIGITS

When the user is specifying an address, console ODT will use the
last eight octal digits if more than eight have been entered.
When the user is specifying data, console ODT will use the last
six 0 c tal dig its i f m0 r e t han six h a v e bee n en t ere d • Th e use r
need not enter leading 0s for either address or data; console aDT
forces 0s as the default. If an odd address is entered, console
ODT responds to the error by printing ?<CR><LF>@.
J-ll PROGRAMMER'S REFERENCE Page A-IS

4.7 ODT TIMEOUT

If the user specifies a nonexistent address or causes a parity

error, console ODT responds to the error by printing ?<CR><LF>~.

4.8 INVALID CHARACTERS

Console ODT will recognize upper- and lowercase characters as

commands. Any character that console ODT does not recogni ze
during a particular sequence is echoed (except for ASCII
characters in the range 0 17 8 ), and console ODT prints
?<CR><LF>@. Console ODT has sever'al internal states, each of
which has its own set of val id input characters. When in a
particular state, only commands specific to that state are valid.
This is done to lower the probability of a user unintentionally
destroying a program by pressing the wrong key.