CHAPTER FOUR
MEMORY SYSTEMS
Computer Components
At a top level, a computer consists of CPU (central processing unit), memory, and I/O
components, with one or more modules of each type. These components are
interconnected in some fashion to achieve the basic function of the computer, which is to
execute programs. Thus, at a top level, we can characterize a computer system by
describing (1) the external behavior of each component, that is, the data and control
signals that it exchanges with other components and (2) the interconnection structure
and the controls required to manage the use of the interconnection structure.
All contemporary computer designs are based on concepts developed by John von
Neumann at the Institute for Advanced Studies, Princeton. Such a design is referred to as
the von Neumann architecture and is based on three key concepts:
• Data and instructions are stored in a single read–write memory.
• The contents of this memory are addressable by location, without regard to the
type of data contained there.
• Execution occurs in a sequential fashion (unless explicitly modified) from one
instruction to the next.
Computer Components
Computer Components
An input device will bring instructions and data in sequentially. But a program is not
invariably executed sequentially; it may jump around (e.g., the jump instruction).
Similarly, operations on data may require access to more than just one element at a
time in a predetermined sequence.
Thus, there must be a place to store temporarily both instructions and data. That
module is called memory, or main memory, to distinguish it from external storage or
peripheral devices. Von Neumann pointed out that the same memory could be used to
store both instructions and data.
computer memory exhibits perhaps the widest range of type, technology,
organization, performance, and cost of any feature of a computer system. No single
technology is optimal in satisfying the memory requirements for a computer system. As
a consequence, the typical computer system is equipped with a hierarchy of memory
subsystems, some internal to the system (directly accessible by the processor) and
some external (accessible by the processor via an I/O module).
Characteristics of Memory Systems
The complex subject of computer memory is made more manageable if we
classify memory systems according to their key characteristics. The most
important of these are listed in Table
Method of Accessing
Three performance parameters are used:
organization refers to the physical arrangement of
bits to form words.
The Memory Hierarchy
The Memory Hierarchy
The way out of this dilemma is not to rely on a single memory component or technology, but
to employ a memory hierarchy. As one goes down the hierarchy, the following occur:
a. Decreasing cost per bit
b. Increasing capacity
c. Increasing access time
d. Decreasing frequency of access of the memory by the processor
Thus, smaller, more expensive, faster memories are supplemented by larger, cheaper, slower
memories. The key to the success of this organization is item (d): decreasing frequency of
access. The use of two levels of memory to reduce average access time works in principle, but
only if conditions (a) through (d) apply. By employing a variety of technologies, a spectrum of
memory systems exists that satisfies conditions (a) through (c). Fortunately, condition (d) is
also generally valid.
Semiconductor Main Memory
Organization
The basic element of a semiconductor memory is the memory cell. Although a variety of
electronic technologies are used, all semiconductor memory cells share certain properties:
• They exhibit two stable (or semistable) states, which can be used to represent
binary 1 and 0.
• They are capable of being written into (at least once), to set the state.
• They are capable of being read to sense the state.
In the operation of a memory cell. Most commonly, the cell has three functional
terminals capable of carrying an electrical signal. The select terminal, as the name
suggests, selects a memory cell for a read or write operation. The control terminal
indicates read or write. For writing, the other terminal provides an electrical signal that
sets the state of the cell to 1 or 0. For reading, that terminal is used for output of the
cell’s state. The details of the internal organization, functioning, and timing of the
memory cell depend on the specific integrated circuit technology used. For our
purposes, we will take it as given that individual cells can be selected for reading and
writing operations.
Semiconductor Main Memory
DRAM and SRAM
One distinguishing characteristic of memory that is designated as RAM is that it is
possible both to read data from the memory and to write new data into the memory
easily and rapidly. Both the reading and writing are accomplished through the use of
electrical signals. The other distinguishing characteristic of RAM is that it is volatile. A
RAM must be provided with a constant power supply. If the power is interrupted, then
the data are lost. Thus, RAM can be used only as temporary storage.
RAM technology is divided into two technologies: dynamic and static. A dynamic RAM
(DRAM) is made with cells that store data as charge on capacitors. The presence or
absence of charge in a capacitor is interpreted as a binary 1 or 0. Because capacitors
have a natural tendency to discharge, dynamic RAMs require periodic charge refreshing
to maintain data storage. The term dynamic refers to this tendency of the stored charge
to leak away, even with power continuously applied.
DRAM and SRAM
A static RAM (SRAM) is a digital device that uses the same logic elements used in the
processor. In a SRAM, binary values are stored using traditional flip-flop logic-gate
configurations. A static RAM will hold its data as long as power is supplied to it.
The Figure is a typical SRAM structure for an individual cell. Four transistors (T1, T2, T3, T4)
are cross connected in an arrangement that produces a stable logic state. In logic state 1,
point C1 is high and point C2 is low; in this state, T1 and T4 are off and T2 and T3 are on.1 In
logic state 0, point C1 is low and point C2 is high; in this state, T1 and T4 are on and T2 and T3
are off. Both states are stable as long as the direct current (dc) voltage is applied. Unlike the
DRAM, no refresh is needed to retain data. As in the DRAM, the SRAM address line is used to
open or close a switch. The address line controls two transistors (T5 and T6). When a signal is
applied to this line, the two transistors are switched on, allowing a read or write operation.
For a write operation, the desired bit value is applied to line B while its complement is
applied to line B’. This forces the four transistors (T1, T2, T3, T4) into the proper state. For a
read operation, the bit value is read from line B.
Address Decoding
Memory cells organized in 1-D and 2-D memory arrays.
Module Organization
Fast Page Mode
Module Organization
Module Organization
