Digital Logic Design (CS-128L) SSUET/QR/114

Lab # 1

BASIC LOGIC GATES

Objective:
Explain basic logic gates with respect to their operation and display the implementation
according to correct pin configuration to verify truth table
Theory:
7408 is a 2-input AND gate IC. Any AND gate can have 2 or more inputs. The basic property
of AND gate is that it will produce a high signal i.e. binary ‘1’ and electronically 5V only if all
of its input are high i.e. binary ‘1’ or 5V. If any one of its input is ‘0’ the output will become
‘0’ i.e. 0V.

7432 is a 2-input OR gate IC. Any OR gate will produce ‘0’ only when all of its inputs are ‘0’.
Any one high input will result in a high output. Both 7404 and 7408 are 2-input IC’s the number
of possible output conditions will be 22=4. These 4 input conditions are always taken as 0,1,2,3
i.e. 00, 01, 10 and 11 in binary system respectively.

7404 is a single input NOT gate. A NOT gate will produce the complements of any input
applied to it. If the input is 1 then output will be zero and vice versa.
Bubbled AND gate is not available in IC form but it is an application of AND and NOT gate.
Although it seems to be similar to NAND but in NAND the bubble is after the AND gate and
here the bubble is before the AND gate. Therefore the two inputs of the AND gate takes the
complements of the original inputs that we applied. Similarly bubbled OR is an application of
OR and NOT gate.

Components Required:
Protoboard, Logic Probe, Connecting Wires, IC’s (7404, 7408, 7432, 7400 quad 2-input
NAND gate, 7402 quad 2-input NOR gate), 7486

Procedure:
a. 2 Input AND , OR, NOR , NAND
Figure 1.1 shows the logic symbols of AND, OR, NAND,NOR gates. Figure 1-2a, b,c,d shows
the layouts of AND gate IC (7408), OR gate IC (7432), NAND gate IC (7400), NOR gate
IC(7402). The pin configuration is also given in the layouts. Construct the circuit with the help
of these layouts. Pin no. 7 and Pin no 14 of each IC is Ground and Vcc respectively. Apply
different inputs on the given inputs and observe the outputs then complete the truth tables 1-1,
1-2,1-3 and 1-4 of these gates.

AND OR NAND NOR

Figure 1.1 Logic Symbols

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Figure 1.2a 7408 Quad 2-Input AND gate IC

Figure 1.2b 7432 Quad 2-Input OR gate IC

Figure 1.2c 7400 Quad 2-Input NAND gate IC

Figure 1.2d 7402 Quad 2-Input NOR gate IC

Table 1-1: Truth table for 2-Input AND gate

A B Q

0 0

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0 1

1 0

1 1

Table 1-2: Truth table for 2-Input OR gate

A B Q

0 0

0 1

1 0

1 1

Table 1-3: Truth table for 2-Input NAND gate

A B Q

0 0

0 1

1 0

1 1

Table 1-4: Truth table for 2-Input NOR gate

A B Q

0 0

0 1

1 0

1 1

b. Bubbled AND and Bubbled OR

Construct the circuit as shown in figure 1-3 and in 1-4 bubbled OR and bubbled AND
respectively. For constructing the circuit of bubbled OR gate short the output of NOT gate
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(Pin no. 2 of 7404) to the input of OR gate (Pin no. 1 of 7432). Similarly the output of
another NOT gate (Pin no. 4 of 7404) to the another input of OR gate (Pin no.2 of 7432)
then apply the binary inputs to Pin no. 1 and 3 of 7404 IC.and then complete the table 1-5
and 1-6.

Figure 1.3 Bubbled OR gate

Figure 1.4 Bubbled AND gate

Table 1-5: Truth table for Bubbled OR gate.

A B Output
0 0
0 1
1 0
1 1

Table 1-6: Truth table for Bubbled AND gate.

A B Output
0 0
0 1
1 0
1 1

c. 2 input XOR,XNOR and also design gates with AND, OR and NOT gate

The Exclusive OR and Exclusive NOR gates are commonly called and written as XOR and
XNOR gates. XOR is similar to OR gate except for input condition when A=1 and B=1.
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When two 1’s are added according to logical addition 1+1 = 1 as in OR gate, but according
to binary addition 1 + 1 = 10, here SUM = 0 and CARRY = 1. So OR gate performs logical
addition while XOR gate produces binary addition. So the conclusion is that it will produce
‘1’ only if both its inputs are unequal otherwise the output will be ‘0’. Since we are
discussing two input XOR gate so possible input conditions can be 00, 01, 10, and 11. XOR
will produce ‘1’ for 01 and 10 and ‘0’ for 00 and 11.

Figure 1-5 shows the logic symbols of XOR and XNOR gates while Figure 1-6 & Figure
1-7 shows the circuit for Exclusive OR gate and XNOR gate. To construct an Exclusive
NOR gate simply put a NOT gate in the end of circuit. You can also use 7486 quad XOR
IC. To construct XNOR circuit from this IC, connect the output of the gate to the input of
a NOT gate. The NOT gate’s output will be the XNOR output. After constructing both of
these circuits, observe the output and complete the truth tables 1-7 and 1-8.

Figure 1.5 Logic Symbols for XOR and XNOR gates

Figure 1.6 Circuit for XOR using basic logic gates

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Figure 1.7 Circuit for XNOR using basic logic gates

Table 1-7: Truth table for XOR gate

A B Output
0 0
0 1
1 0
1 1

Table 1-8: Truth table for XNOR gate

A B Output
0 0
0 1
1 0
1 1

d. Verify NOT gate and also implement NOT gate with XOR gate
7404 is a single input NOT gate. A NOT gate will produce the complements of any input
applied to it. If the input is 1 then output will be zero and vice versa.
Figure 1-8 shows the logic symbols of NOT gates. Figure 1-9 shows the layouts of NOT
gate IC (7404). The pin configuration is also given in the layouts. Construct the circuit
with the help of these layouts. Pin no. 7 and Pin no 14 of each IC is Ground and Vcc
respectively. Apply different inputs on the given inputs and observe the outputs then
complete the truth tables 1-9

Figure 1.8 Logic Symbol of NOT gate

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Figure 1.9 7404 Hex Inverter (NOT gate) IC

Table 1-9: Truth table for NOT gate.

A Q

Implementation of NOT by XOR gate is possible by connecting one of the pin of XOR gate
with logic 1 as shown in figure 1-10 and then apply input on the other pin, Figure 1-11 shows
the pin layout of XOR IC(7486) and complete the table 1-10.

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Figure 1.10 Implenting NOT logic using XOR gate

Figure 1.11 7486 Quad 2-Input XOR gate IC

Table 1-10: Truth table for NOT gate using XOR gate
A B Output
0 0 ----------
0 1 ----------
1 0
1 1

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Conclusion:

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Lab # 2

COMBINATIONAL LOGIC CIRCUITS

WITH NAND AND NOR GATES
Objective:
Explain the Combinational logic circuits using logic circuits with implementation using
universal gates.

Theory:
The Boolean expression for the NOR gate is F= A+B; in DE Morgan’s theorem, F=
(A+B) =A'B'. The NOR gate can be used to construct NOT; OR; AND; NAND; and XOR
gates. We will construct various logic gates in this experiment by connecting NOR gates in
different ways.

The Boolean expression for the NAND gate is F= (AB)’; in DeMorgan’s theorem, F=
(AB)=A'+B'. The NAND gate like the NOR gate can be used to construct NOT; OR; AND;
NAND; and XOR gates. We will attempt to construct various logic gates in this experiment
by connecting NAND gates in different ways.

Components Required:

Proto board, Logic Probe, 7400 (Quad 2 input NAND), 7402 (Quad 2 input NOR), 7408 (Quad
2 input AND), 7432 (Quad 2 input OR), 7404 (NOT gate) 7410 triple 3-input NAND gate,
7427 triple 3-input NOR gate)

Procedures:
a) Build combinational logic using NOR gate
 Use the 7402 NOR gate to build an inverter as shown in figure 2.1.
 Connect the circuit on the breadboard of the trainer kit, connect input A to data switch
SW0, and output F to LED L1, and verify the truth table.

Figure 2.1 Implenting NOT logic using NOR gate

Table 2-1: Truth table for NOT gate

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A F

 Use the 7402 NOR gates to build an OR gate as shown in figure 2.2
 Connect the circuit, on the breadboard of the trainer kit, connect inputs A, B, and output
F to SW1, SW0, and L1 respectively, and verify the truth table.

Figure 2.2 Implenting OR logic using NOR gate

Table 2-2: Truth table for 2-Input OR gate

A B F

0 0

0 1

1 0

1 1

b) Build combinational logic using NAND gate:

 Use the 7400 NAND gates to build an inverter as shown in figure (3).
 Connect the circuit on the breadboard of the trainer kit, connect input A to data switch
SW0, and output F to LED L1, and verify the truth table.

Figure 2.3 Implenting NOT logic using NAND gate

Table 2-3: Truth table for NOT gate

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A F

 Use the 74LS00 NAND gates to build an AND gate as shown in figure 2.4
 Connect the circuit on the breadboard of the trainer kit, connect inputs A, B, and output
F to SW1, SW0, and L1 respectively, and verify the truth table.

Figure 2.4 Implenting AND logic using NAND gate

Table 2-4: Truth table for 2-Input AND gate

A B F

0 0

0 1

1 0

1 1

 Use the 74LS00 NAND gates to build an OR gate as shown in figure 2.5
 Connect the circuit on the breadboard of the trainer kit, connect inputs A, B, and output
F to SW1, SW0, and L1 respectively, and verify the truth table.

Figure 2.5 Implenting OR logic using NAND gate

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Table 2-5: Truth table for 2-Input OR gate

A B Q

0 0

0 1

1 0

1 1

c) Build 3 input NAND using 2 input NAND gate

 Use the 74LS00 two input NAND gates to build a 3 input NAND gate as shown in
figure 2.6
 Connect the circuit on the breadboard of the trainer kit, connect inputs A, B, C, and
output F to SW2, SW1, SW0, and L1 respectively, and verify the truth table.

Figure 2.6 Implenting 3 Input NAND gate using NAND gates

Table 2-6: Truth table for Verification of NAND gate

A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

d) Implement 3 input NOR and NAND gates.

Figure 2.7 shows the logic symbols of 3-input NAND and 3-input NOR gates. Figure 2.8a
& 2.8b shows the layouts of 3-input NAND gate IC (7410) and 3-input NOR gate IC (7427).
 Construct the circuit with the help of the layouts. Pin no. 7 and Pin no. 14 of each
IC is Ground and Vcc respectively. Apply different inputs at the given input pins
and observe the outputs at the output pins, then complete the truth tables.

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(a) (b)
Figure 2.7 Symbols of (a) 3 Input NAND and (b) 3 Input NOR gates

Figure 2.8b 7410 Triple 3-Input NAND gate IC

Figure 2.8b 7427 Triple 3-Input NOR gate IC

Table 2-7: Truth table for Verification of NAND gate

A B C Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Table 2-8: Truth table for Verification of NOR gate

A B C Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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Conclusion:
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Lab # 3

IMPLEMENETING BOOLEAN FUNCTION

USING LOGIC GATES
Objective:
Explain the Combinational logic circuit implementation using given Boolean functions and
verify them.

Theory:
The circuit which will produce the give Boolean function will contain three 3-input AND gates
three NOT gates and one 3-input OR gate. The pin configuration of 3-input AND gate IC is
given in Figure 3.1. Here value is not assigned to A, B, C i.e. A, B and C can be ‘1’ or ‘0’.
Thus the circuit has three inputs A, B, C so you can apply eight possible input conditions i.e.
000 to 111, but this circuit will produce ‘1’ only when ABC=111,100 or 011 i.e. which is in
decimal system are equivalent to 7, 4, 3 respectively.

Components Required:
Protoboard, Logic Probe, Connecting Wires, 2-input OR gate IC (7432), 3-input AND gate IC
(7411) and a NOT gate IC (7404).

Procedure:
Construct the circuits as shown in Figure 3.2 and 3.3. Apply inputs A, B, C and check the
output functions F1 & F2 respectively. Finally complete the Table 3-1 and 3-2 for the respective
Boolean functions.

Figure 3.1 7411 Triple 3-Input AND gate IC

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Figure 3.2

Figure 3.3

Table 3-1: Truth table for the above given Boolean function.
A B C F1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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Table 3-2: Truth table for the above given Boolean function.
A B C F2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Conclusion:
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Lab # 4

BOOLEAN ALGEBRA
Objective
Proceed to simplify and modify logic expression using Boolean logic functions by means of
DE Morgan’s theorem and verify them experimentally.

Theory:
Boolean algebra is a deductive mathematical system closed over the values Zero and One (False
and True respectively). A binary operator defined over this set of values accepts a pair of
Boolean inputs and produces a single Boolean value as an output.

Laws of Boolean Algebra

Commutative Laws

• Commutative Law w.r.t. OR operation is A + B = B + A which is shown in Figure 4.1(a).

• Commutative Law w.r.t. AND operation is A . B = B . A which is shown in Figure 4.1(b).

Associative Laws

• Associative Law w.r.t. OR operation is A + ( B + C ) = ( A + B ) + C which is shown in

Figure 4.2(a).
• Associative Law w.r.t. AND operation A . ( B . C ) = ( A . B ) . C which is shown in Figure
4.2(b).

Figure 4.1(a) Commutative Law w.r.t OR

Figure 4.1(b) Commutative Law w.r.t AND

Figure 4.2(a) Associative Law w.r.t OR

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Figure 4.2(b) Associative Law w.r.t AND

Distributive Law is A . ( B + C ) = A . B + A . C which is shown in Figure 4.3.

Figure 4.3 Distributive Law

RULES:

1. A+0=A 7. A.A=A
2. A+1=1 8. A . 𝐴̅ = 0
3. A.0=0 9. 𝐴̿ = A
4. A.1=A 10. A + AB = A
5. A+A=A 11. A + 𝐴̅B = A + B
6. A + 𝐴̅ = 1 12. ( A +B )( A + C ) = A + BC
Equipments required:
Protoboard, 7400 Quadruple 2 input NAND gates, 7402 Quadruple 2 input NOR gates, 7408
Quadruple 2 input AND gates, 7432 Quadruple 2 input OR gates, 7404 Hex inverters.

Procedures:
Connect these circuits and verify their operations with the help of truth tables.

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DeMorgan’s Theorem
DeMorgan, a mathematician, proposed two theorems which are considered to be an important
part of Boolean Algebra. These theorems provide the equivalency of NAND and Bubbled-
OR (also known as negative-OR) gates and the equivalency of NOR and Bubbled-AND
(also known as negative-AND) gates.

One of the theorem states that

(i) The complement of a product of variables is equal to

the sum of the complements of the variables.

Second theorem states that

(ii) The complement of a sum of variables is equal to

the product of the complements of the variables.

 Construct the two circuits corresponding to the functions ( 𝑋̅. 𝑌̅ ) and (̅̅̅̅̅̅̅̅̅̅̅
𝑋+𝑌)
respectively.
 Show that for all combinations of X and Y, the two circuits give identical results.
 Connect these circuits and verify their operations and verify the truth table.

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Table 4-1: Truth table

X Y ̅.𝐘
𝐗 ̅ ( ̅̅̅̅̅̅̅̅
𝑿+𝒀)
0 0
0 1
1 0
1 1

Conclusion:

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Lab # 5

BINARY ADDER
Objective:
Proceed to investigate and implement the functions of a 4-Bit binary parallel adder.

Theory:
Half Adder and Full Adder
The half adder accepts two binary digits as its inputs and produces two binary digits as its
outputs, a sum bit and a carry-out bit. The carry output is a 1 only when both the inputs are 1s,
therefore carry output can be expressed as the AND of the input variables. The half adder is
considered as the first stage or the Least Significant bit of the addition operation. The logic
symbol of half adder is also given in Figure 5.1.

The full adder accepts three inputs (a carry-in bit in addition to the two binary digits) and
generates a sum output and a carry output. The full adder is considered as the subsequent stage/s
after the first stage or the LSB stage (i.e.; the half adder). The carry-in bit in the full adder is
available to take the carry-out bit of the previous stage forward to the next stage. The logic
symbol of full adder is also given in Figure 5.2.

A full adder can be made to function as a half adder by grounding its carry-in bit.

Figure 5.1 Logic Symbol of Half Adder

Figure 5.2 Logic Symbol of Full Adder

4-Bit Parallel Binary Adder

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To add binary numbers consisting of more than one binary term, two or more full adders are
used. To add two binary numbers, a full-adder is required for each bit in the numbers, so for 2-
bit numbers, two adders are needed; for 4-bit numbers, four adders are used and so on.
Adders that are available in integrated circuit (IC) form are parallel binary adders. A basic 4-
bit parallel adder is implemented with four full – adders. A single full – adder is capable of
adding two 1-bit numbers and an input carry. To add binary numbers with more than 1-bit,
additional full – adders must be used. When one binary number is added to another, each
column generates a sum bit and a ‘1’ or ‘0’ carry-out bit to the next column to the left. So for
four bit numbers four adders are needed. The carry output of each adder is connected to the
carry input of the next higher-order adder.

Components Required:
Proto board, logic probe, connecting wires, 2 input OR gate IC (7432), 2 INPUT and gate IC
(7408) and a XOR gate IC (7486).74LS83 4-bit binary parallel adder IC.

Procedure:
a. Arrange two half adders to form a full adder and to verify the truth table

Construct the circuit as shown in Figure 5.3 for the half adder and apply input conditions for
the two 1-bit variables A and B (from 0 0 to 1 1) and verify the truth table 5.1.Similarly
construct the circuit as shown in Figure 5.4 for the full adder and apply input conditions to
verify the truth table 5.2.

Figure 5.3 Half Adder Circuit

Figure 5.4 Full Adder Circuit

Table 5-1: Truth table for Half Adder

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C0 S
A B
(Carry-Out) (SUM)
0 0

0 1

1 0

1 1

Table 5-2: Truth table for Full Adder

Cin C0 S
A B
(Carry-In) (Carry-Out) (SUM)
0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

b. To demonstrate the function of a 4-Bit binary parallel adder using 74LS83 IC.

The block diagram depicted in Figure 5.5 shows the internal structure of 74LS83 IC in which
four full adders are clearly seen. The pin layout of the IC is shown in Figure 5.6. Apply the
binary numbers as the inputs of the IC. The first 4-bit number will be applied on pin numbers
10,8,3 and 1 (A1, A2, A3, A4). The second 4-bit number will apply through pin nos. 11, 7, 4 and
16 (B1, B2, B3, B4). The summation of these numbers can be found as output from pin nos. 9,
6, 2 and 15 (Σ1, Σ2, Σ3, Σ4 &C4). The carry output is found as Pin no. 14. labeled as C4 which is
the MSB of the result whereas the Σ1 is the LSB. Pin no. 13 is labeled as C0 in Figure 5.6. This
will be ‘0’ or Ground for addition purpose as it is the first (LSB) stage. We can also apply ‘1’
on this pin for subtraction of 4-bit numbers. After completing the circuit completes the truth
table 5.3 by observing the outputs. Also write the decimal values corresponding to the observed
output values.

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Figure 5.5 Block Diagram of 4-Bit Parallel Binary Adder

Figure 5.6 7483 4-Bit Parallel Binary Adder IC

Table 5-3: Truth table for 4-Bit Parallel Binary Adder

∑
A4 B4 A3 B3 A2 B2 A1 B1 C4 ∑4 ∑3 ∑2 ∑1 Decimal
MSB LSB Value
0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1
0 0 0 0 1 1 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 0 0
0 0 1 1 0 0 1 1
0 0 1 1 1 1 0 0
0 0 1 1 1 1 1 1
1 1 0 0 0 0 0 0
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
1 1 0 0 1 1 1 1
1 1 1 1 0 0 0 0
1 1 1 1 0 0 1 1
1 1 1 1 1 1 0 0
1 1 1 1 1 1 1 1

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Conclusion:

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Date: ___________ Signature: _________

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Lab # 6

SCENARIO BASED CIRCUIT DESIGN

Objectives:

Display the working of different circuits according to the given scenarios.

Theory:
There are four steps involved to design logic circuits, which are listed below.

1 Build the truth table.

2 Express output as a minterm expression (standard sum of product).
3 Simplify the minterm expression of output(s).
4 Implement the simplified Boolean function with logic gates.
Procedure:
S1. A battery powered lamp in a room is to be operated from two switches, One switch at the
back door and one at the front door. The lamp is to be ON if the front switch is turned ON and
the back switch is turned Off, or if the front switch is turned Off and the back switch is turned
On. The lamp is to be off if both the switches are turned Off or if both the switches are turned
On. Construct the circuit for the described situation. Assume a HIGH output represents the ON
status and a LOW output represents the OFF status.

S2. A circuit has four inputs and two outputs. Let the four inputs be A, B, C, D and the two
outputs be P and Q. Output P should be TRUE if the input number is Prime (NOTE: 0 and 1
are not Prime). Output Q should be TRUE if the input number is divisible by 3. Construct a
circuit that takes four inputs and produces the outputs P and Q.

S3. Consider A, B, C, D as four inputs to a logic circuit. Inputs A and B represent two bits. The
inputs C and D specify the logic operation to be performed on the bits A and B as shown in
Table 6.1. The result of operation performed on A and B is represented by the output Y.
Construct the circuit for the described situation.

Table 6-1: Table for operations specified by the inputs C and D

C D OPERATIONS

0 0 Logical AND

0 1 Logical NOR

1 0 Logical XOR

Do all the work in the following sheets under the headings Scenario-S1, Scenario-S2,
Scenario-S3.

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Scenario-S1:

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Scenario-S2:

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Scenario-S3:

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Conclusion:

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Lab#07

Open-Ended Lab
Title: Sequential Circuits

1. Objective: Write any logic equation with atleast two terms. Draw its
logic diagram, build truth table and verify it using hardware
implementation with logic gates.

2. Equation

3. Hardware/Software required:

4. Logic Diagram:

5. Methodology:

6. Observation:

7. Conclusion:

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Digital Logic Design (CS-128L) SSUET/QR/114

Lab # 8

MULTIPLEXER
Objective:
Proceed to the implementation of Boolean logic function using Multiplexer and verify it.
Theory:
Multiplexer
Sending a large number of information (provided as input) over smaller number of lines is
called Multiplexing. Digital Multiplexrer (MUX) is a device that sends binary information
selecting from one of the many input lines to a single output line. A set of selection lines is
used to select the particular input to be transmitted. There are n select lines in a MUX that has
2n input lines. Figure 8-1 shows the layout of 16-to-1 Lines MUX. E0… E15 are 16 data input
lines, W is output and ABCD are four control lines. Since control lines = 4 therefore 2 4 =16
possible control signals can be generated from 0000 to 1111 to select from the corresponding
16 (E0 to E15) input lines.
The single output line ‘W’ is with a bubble because the internal design of this IC is such that
the ‘W’ will produce the complement of the signal transferred to it.
Figure 8-1 shows another line named as STROBE which is also called activation pin. It has a
bubble showing that it will be ‘ON’ if we give it ‘0’ and it will inactive if it is given ‘1’ i.e.
+5V. if this line is inactive, the MUX IC cannot transfer any data inputs and Y is stuck at HIGH
irrespective of selected data.

Implementing Boolean Logic Functions using MUX

MUX can be used to implement Boolean logic functions. To implement a Boolean function
with v number of variables using MUX, we would require a MUX with v-1 select lines.
Suppose we want to implement the function F(A,B,C) = ∑ m(1,3,5,6). Here v=3 (i.e.; A,B,C),
then we will require a 22-to-1 line MUX. We may select B and C to be the select lines as S1
and S0 respectively. The truth table for the function is depicted in Table 8-1.

Figure 8-1 74150 (16-to-1 Line Multiplexer) IC

Table 8-1 Truth Table for F(A,B,C) = ∑ m(1,3,5,6)
A B C F
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0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Table 8-2 Implementation Table

Consider now the single variable A.As A is the Most Significant Bit (MSB) it will be
complemented in the first half of the 8 minterms. The second half of the minterms will have
their A variable uncomplemented i.e.; variable A is complemented in minterms 0 to 3 and
uncomplemented in min terms 4 to 7.

List the 4 inputs of the MUX (I0, I1, I2, I3). Lists all those minterms where A is complemented
in the first row and all the minterms with A uncomplemented in the second row below the
inputs respectively, as shown in Table 8-2. Circle all the minterms of the function and inspect
each column separately.
 If the two minterms in a column are not circled, apply 0 to the corresponding MUX
input.
 If the two minterms are circled, apply 1 to the corresponding MUX input.
 If the bottom minterm is circled and the top is not circled, apply A to the corresponding
MUX input.
 If the top minterm is circled and the bottom is not circled, apply A to the corresponding
MUX input.
Now apply A as found from the above procedure to the inputs of MUX and BC as select lines
S1S0 respectively.

Components Required:
Protoboard, Logic Probe, Connecting Wires, 74150 16 input data selector/multiplexer IC.

Procedure:
a. Familiarization with MUX 74150

The 74150 IC has sixteen data inputs and four data-select lines. In this case four bits are
required to select any one of the sixteen data inputs (24=16). There is also an active-LOW
Enabled input. On this particular device, only the complement of the output is available.. Apply
16-bit data at data inputs that are labeled as E0 to E15. Select the data input with the help of data

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selectors D to A (from 0000 to 1111). Observe the output at pin#10 and complete the truth
table given by Table 8-3. Fill the output ‘W’ in the form of E0 to E15.

Table 8-3 Truth Table for 16-to-1 Line MUX

OUTPUT
DATA INPUTS DATA SELECTS

E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 A B C D W

1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1
0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0
0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1
0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0
0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1
0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0
0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 0 0 1 1 1
0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0
0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1
0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0
0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 1
0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 0 0
0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 1
0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0
0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1
Strobe = 0V

b. Implement Boolean Logic Function using MUX

Use 74150 to implement the Boolean logic function F providing all the steps involved in the
process. Consider V2,V3,V4,V5 as select lines A, B, C,D respectively.

F(V1,V2,V3,V4,V5) = ∑ m(0,1,4,6,8,9,12,13)

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Conclusion:
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Digital Logic Design (CS-128L) SSUET/QR/114

Lab # 9

ENCODER & DECODER

Objective:
Proceed to the implementation of Boolean logic function using Encoder and Decoder and verify
it.
Theory:
Encoder:
The process of converting from familiar symbols or numbers to a coded format is called
encoding. In its general form, an encoder has 2n (or fewer) input lines and n output lines to
generate the binary code corresponding to the input value. In other words, an encoder accepts
an active level on its inputs representing a digit, such as decimal or octal digits, and converts it
to a coded output, such as BCD or binary. Encoders can also be devised to encode various
symbols and alphabetic characters.
There is an assumption that only one input has a value of 1 at any given time which is its
limitation also e.g.; consider in an Octal-to-Binary encoder, switching ON inputs 3 (0112) and
6 (1102) simultaneously will result in the wrong output i.e.; 7 (1112). This limitation can be
overcome by using a Priority Encoder including the priority function.
The decimal to BCD priority encoder performs the same basic encoding function as in ordinary
encoder. It also offers additional flexibility in that it can be used in applications that require
priority detection. The priority function means that the encoder will produce a BCD output
corresponding to the highest-order decimal digit input that is active and will ignore any other
active inputs.

Decoder:
The basic function of a decoder is to detect the presence of a specified combination of bits
(code) on its inputs and to indicate the presence of that code by a specified output level. In its
general form, a decoder has n inputs lines to handle n bits and from one to 2n output lines to
indicate the presence of one or more n-bit combinations. It performs the reverse function of an
encoder.
Decoder IC is similar to DeMultiplexer IC, the difference is only that instead of data input we
have an ENABLE input which is active LOW. So in addition to STROBE we also have to make
the ENABLE pin low to activate the decoder. In absence of data inputs, the function of a
decoder is that it checks the combination on ABCD and makes the corresponding output line
active. In a decoder if an output line is active it will be LOW and vice versa.

Components Required:
Protoboard, Logic Probe, Connecting Wires, 74154 4-Line Decoder IC, 74147 Encoder IC.
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Procedure:
a. Encoder(Using74147 IC)

The 74LS147 is a priority encoder with active-LOW inputs for decimal digits 1 through 9 and
active-LOW BCD outputs as indicated in the Figure 9-1. A BCD zero output is represented
when none of the inputs is active. To convert a decimal number to BCD apply the 9-bit number
at its inputs and find out its corresponding BCD outputs. The outputs should match the truth
table 9-1.

Figure 9.1 74147 Priority Encoder IC

b. Decoder (Using 74154 IC)

The 74154 is an example of an Medium Scale Integrated (MSI) decoder. The pin configuration
for 74154 is shown in Figure 9-2. There is a STROBE (an Active Low) input which is used to
activate or deactivate the IC. To activate the IC, the STROBE signal must be low. If the
STROBE signal is high then all sixteen decoder output will be HIGH regardless of the states
of the four input variables, A, B, C, D.

Connect the circuit by giving the DATA, STROBE, Vcc and Gnd. Then apply the input signals
that are given in truth table 9-2 and observe the output at Y0 to Y15 and complete the truth table
9-2.

Figure 9.2 74154 4-to-16 Line Decoder/DeMultiplexer IC

Table 9-1: Truth table for determining the function of 74147 PriorityEncoder
Inputs Outputs
X1 X2 X3 X4 X5 X6 X7 X8 X9 A B C D
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H H H H H H H H H
X X X X X X X X L
X X X X X X X L H
X X X X X X L H H
X X X X X L H H H
X X X X L H H H H
X X X L H H H H H
X X L H H H H H H
X L H H H H H H H
L H H H H H H H H

Table 9-2: Truth table for determining the function of 74154 Decoder/DeMultiplexer.
STROBE DATA A B C D Y0 to Y15
0 0 0 1 1 0
0 0 1 1 1 0
0 0 1 1 1 1
0 0 0 0 0 0
1 0 0 1 1 0
1 0 1 1 1 0
1 0 1 1 1 1
1 0 0 0 0 0

Conclusion:
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Sir Syed University of Engineering & Technology, Karachi
Digital Logic Design (CS-128L) SSUET/QR/114

Lab # 10

S-R Latches, Gated S-R Latches and D Latches

Objective:
Proceed to the implementation of S-R Latches, Gated S-R Latches and D Latches and verify
them.

Theory:
Latches and Flip-Flops are two categories of Bi-stable devices. Bi-stable devices are one of the
three types of Multi-vibrators. Astable and Mono-stable devices are the other two types as
shown in Figure 10.1. In this lab only bi-stable devices are discussed. Bi-stable devices, as the
name suggests, have two stable states namely SET (considered as HIGH or 1) and RESET
(considered as LOW or 0). These devices are useful for storage (memory) application as they
can retain either of their states (SET or RESET) indefinitely.

An active-HIGH input S-R (SET-RESET) Latch is formed with the help of two cross-coupled
NOR gates as shown in Figure 10.2 (a). Whereas, Figure 10.2 (b) shows an active-LOW input
S-R latch which is formed with the two cross-coupled NAND gates. Notice that a regenerative
Feedback is produced when the output of one gate of a latch is fed into the input of the other
gate. The regenerative Feedback is the characteristic of all latches and flip-flops. In S-R latch
there are 4 possible values of output Q, among those one output is undefined where the outputs
Q and Q comes out to be equal.

Multi-vibrators

Mono-stable Bi-stable Astable

Latches Flip-Flops
Figure 10.1 Types of Multi-vibrators

(a) An active-HIGH input S-R Latch (b) An active-LOW input S-R Latch
Figure 10.2 Two versions of S-R Latches

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Figure 10.3 Gated S-R Latche

The S-R latch changes state indefinitely. To control the change of state, a control input is
introduced as shown in Figure 10.3. This setup is called the Gated S-R Latch, where the change
in the input to the Latch is reflected in the output when the Gate input E is activated. However,
the undefined output remains unresolved in the Gated S-R Latch. To eliminate the undefined
output where the output Q and its complement appears to be equal, D-Latch is used. In D-Latch
(also known as Data Latch) the input S is connected with the input R through an inverter as
shown in Figure 10.4.

Components:
7402 (Quad 2-Input NOR gate IC),
7404 (Hex Inverter IC),
7408 (Quad 2-Input AND gate IC).

Procedure:
S-R Latch:
Make the circuit using the pin configuration of the IC 7402 as shown in Figure 10.5. Use any
two NOR gates to construct the S-R Latch as shown in Figure 10.1(a). Apply logic 0 and 1 at
the input and check the output by verifying the table 10-1.

Gated S-R Latch:

Make the circuit using the pin configurations of the IC 7402 and the IC 7408 as shown in Figure
10.5 and Figure 10.6 respectively. Use any two NOR gates and any two AND gates to construct
the gated S-R Latch as shown in Figure 10.3. Apply logic 0 and 1 at the input and check the
output by verifying the table 10-2.

D Latch:
Make the circuit using the pin configurations of the IC 7402 and the IC 7408 and IC 7404 as
shown in Figure 10.5, Figure 10.6 and Figure 10.7 respectively. Use any two NOR gates, any
two AND gates and any one NOT gate to construct the D Latch as shown in Figure 10.4. Apply
logic 0 and 1 at the input and check the output by verifying the table 10-3.

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Figure 10.4 D Latche

Figure 10.5 7402 Quad 2-Input NOR gate IC

Figure 10.6 7408 Quad 2-Input AND gate IC

Figure 10.7 7404 Hex Inverter (NOT gate) IC

Observations:

Table 10-1: Output of the S-R (SET-RESET) Latch

R S Q Q Action
0 1
1 1
1 0
0 0

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Table 10-2: Output of the Gated S-R (SET-RESET) Latch

E R S Q Q Action
1 0 1
1 1 1
1 1 0
1 0 0
0 X X

Table 10-3: Output of the D Latch

E D Q Q Action
1 1
1 0
0 X

Conclusion:
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Digital Logic Design (CS-128L) SSUET/QR/114

Lab #11
Initialization of the Flip-Flop using Asynchronous Inputs
Objective:
Proceed to the implementation of Flip-Flops using Asynchronous inputs and verify them

Theory:
Flip-Flop is a basic building block for counters, registers, and other sequential control logic
and is used in certain types of memories. The basic difference between latches and flip-flops is
the way in the which they are changed from one state to the other. Flip-Flops are synchronous
bistable devices as opposed to latches which are asynchronous in nature. The term synchronous
means that the output changes state only at a specified point on the triggering input called the
Clock (CLK). In simple words, the gate input in latch is replaced by the CLK input in Flip-
Flop.

When power is first applied, flip-flops came in a random state. So it is necessary to initialize
the flip-flop. For this purpose PRESET and CLEAR are used which are asynchronous inputs.

Components required:
54/7427, 74LS32, 74LS04

Procedure:
The IC to be used in this experiment is 74LS27, which is a three input NOR gate, 74LSs08
which is a two input AND gate, 74LS32 which is two input OR gate and 74LS04. Insert all the
IC’s in the proto board and make sure the legs of the IC’s are not shorted internally in the board.
Make the connection of the circuit according to the diagram. Provide Vcc to the pin 14 and
connect ground to pin 7. Make the connection for SR flip flop using 74LS27. In this experiment
we will implement PRESET and CLEAR inputs on the flip-flop that affect its state independent
of the clock (asynchronously). An active level on the PRESET input will set the flip flop and
an active level on the CLEAR input will reset it. Apply logic 0 and 1 at the input D and check
the output at pin 8 and 16. Perform this task and verify the table 11.1

Figure 11.1 Flip-Flop withPRESET and CLEAR inputs

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Table 11.1: Table for PRESET & CLEAR function in the Flip- Flop
PRESET CLEAR CLK INPUT (D) NEXT STATE (Qn+1)
1 0 X X
0 1 X X
0 0 0 X
0 0 0
0 0 1

Conclusion:
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Sir Syed University of Engineering & Technology, Karachi
Digital Logic Design (CS-128L) SSUET/QR/114

Lab#12

JK MASTER SLAVE FLIP – FLOP

Objective:
Proceed to the implementation of JK Master Slave flip flop circuit and verify its truth table.

Theory
This simple JK flip Flop is considered as a universal flip-flop circuit. The reason for its
universal characteristic is that it has no INVALID input states even when both its input (J &
K) are activated simultaneously. Other than this the sequential operation of the JK flip flop is
exactly the same as for the SR flip-flop with the “Set” and “Reset” inputs. The design of JK
flip flop is such that its state will toggle when both its input are activated simultaneously i.e.; if
previously the output is “1”, on applying J = K = 1, the output will become “0” on the next
clock edge and if previously the output is “0”, on applying J = K = 1, the output will become
“1” on the next clock edge. Therefore, a JK flip-flop has four possible input combinations,
“logic 1”, “logic 0”, “no change or storage” and “toggle”. The symbol & circuit for a JK flip-
flop is shown in Figure 12.1.

Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called “race” if the output Q changes state before the timing pulse of the clock input
has time to go “OFF”. To avoid this, the timing pulse period ( T ) must be kept as short as
possible (high frequency). As this is sometimes not possible with modern TTL ICs, therefore,
the much improved Master-Slave JK Flip-Flop was developed.

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from the “Slave” flip-
flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip-flop being
connected to the two inputs of the “Slave” flip flop. This feedback configuration from the
slave’s output to the master’s input gives the characteristic toggle of the JK flip flop as shown
in Figure 12.2.

Figure 12.1 Symbol and Circuit for a JK Flip-Flop

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Digital Logic Design (CS-128L) SSUET/QR/114

Figure 12.2 Master-Slave configuration

Components required
7427, 74LS00, 74LS11

Procedure
The IC to be used for this experiment is 74LS27, which is three input NOR gate and 74LS11
which is three input AND gate. The NOR gate IC is used to design the SR latches in the circuit.
Insert an IC the proto board. Make the connection of the circuit as shown in Figure 12.3.
Provide Vcc to the pin 14 of the IC and connect ground to pin 7. In this experiment, we
construct two back to back JKFlip-Flops, one is marked as Master and another as Slave. Any
input in the Master-Slave flip-flop at J and K is first seen by the Master part of the circuit while
CLK is High(1). An important feature here is that the complement of the circuit while CLK
pulse is fed to the Slave Flip-Flop when CLK is Low(0). Therefore on the High-to-Low CLK
transition, the outputs of the Master part are fed to the salve FF. Apply logic 0 and 1 at inputs
and check the output at pin 8 and 16. Perform the given task and verify the Table 12.1.

Figure 12.3 Master-Slave JK Flip-Flop using gated SR Latches

Table 12.1 Truth Table for Master-Slave JK Flip-Flop using gated SR Latches
INPUTS OUTPUTS
CLK Qn J K Qn+1
Current State Next State

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Conclusion:
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Digital Logic Design (CS-128L) SSUET/QR/114

Lab#13

COMPARATOR AND PARITY GENERATOR

Objective:
To show operational principles of comparators using suitable circuit configuration

Theory:
Comparator
At least two numbers are required to perform any comparison. There are two basic types of
comparators namely Identity Comparators and Magnitude Comparators. Identity comparators
compare two entities for equality (or non-equality) and have at-most two outputs Equal and
Not-equal. On the other hand, Magnitude comparators compare the magnitude of two entities
and have three outputs Equal, Greater than, Less than. Consider the two 1-bit inputs A and B
to be compared. For identity comparator the possible outputs are A=B and A≠ B. whereas for
magnitude comparator the possible outcomes are A>B, A=B, A<B. Figures 9-1a and 9-1b show
the symbol of a1-bit identity and magnitude comparator, respectively.

(a) (b)
Figure 9.1(a) Symbol of 1-bit Identity Comparator
(b) Symbol of 1-bit Magnitude Comparator

Parity Bit and its Application

The parity is defined as the number of 1s in the data. The parity is Even, If number of 1s in the
data is even, whereas the parity is considered an Odd parity if the number of 1s in the data is
odd. For example, if data is 65(decimal), which is represented as 1000001 in binary, the number
of 1s is 2 and the parity associated with it is Even. Since there are only two possibilities for a
parity, either Even or Odd, therefore only 1-bit can be sufficient for its representation.
Parity bit can be used in the data communication for single bit error detection in the data. In a
data communication system, a parity bit is generated and append to the data bits at the
transmission end in order to make the total number of 1s (including Parity bit) either even or
odd (depending on the system). For example, an ASCII character ‘A’ is to be transmitted. The
character ‘A’ is represented in binary as 1000001 and it has two 1s. So the parity generated for
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an Even system will have the value 0 making the overall parity even whereas for an Odd parity
system the parity is 1 making the overall parity odd.
In order to check for the correct (error-free) reception of the data, the parity checker circuit is
used at the receiver end of the data communication system. The Parity Checker circuit basically
generate the parity of the received information i.e.; data bits + Parity bit. If the information is
transmitted with an Even parity, the received bits of information must have an Even parity.

Equipment’s required:
Protoboard, 74LS04 (Hexa NOT), 74LS08 (Quad 2 input AND), 7486 Quadruple 2 input
XOR gate), IC 74180.

Procedures:
a. Construct Comparators with the help of basic logic gates
(i) Complete the truth table given in Table 9-1. and Construct a 1-bit Identity Comparator

Table 9-1: Truth table for Identity Comparator

INPUTS OUTPUTS
A B A=B A≠B
0 0
0 1
1 0
1 1

(i) Complete the truth table given in the truth table Table 9-2. and Construct a 1-bit
Magnitude Comparator

Table 9-2: Truth table for Magnitude Comparator

INPUTS OUTPUTS
A B A>B A=B A<B
0 0
0 1
1 0
1 1

a. Parity Generator and Checker Circuits

(i) Construct a Parity Generator Circuit to generate a 3-bit code (2-bit data + 1-bit Parity)
for an ODD parity system by completing the truth table given in Table 9-3.

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Table 9-3: Truth table for a 3-bit Parity Generator for ODD Parity System
DATA PARITY
A B P
0 0
0 1
1 0
1 1

(ii) Construct a Parity Checker Circuit to check a 3-bit code (2-bit data + 1-bit Parity) for
an ODD parity system by completing the truth table given in Table 9-4.

Table 9-4: Truth table for a 3-bit Parity Checker for ODD Parity System
RECEIVED DATA PARITY ERROR CHECK
A B P C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

NOTE:
The Parity Checker circuit can be used as a Parity Generator circuit if the input P is
connected to the logic 0, in which case the output C will be considered as the parity bit.

(iii) Construct a 9-bit Parity Generator/Checker Circuit using IC74180

The pin configuration of 74180 (Universal Parity Generator/Checker) is shown in Figure 9-2.
This particular Medium Scale Integrated (MSI) device can be used to generate a nine-bit odd
or even parity code (eight data bits and one parity bit), or it can be used to check for odd or
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even parity for a nine-bit code. The truth table for Universal Parity Generator / Checker 74180
is given by Table 9-5 showing the function of it’s the inputs and outputs.
Consider that EVEN INPUT (pin# 3) is grounded and the ODD INPUT (pin# 4) is connected
to +5V i.e.; the system is Odd Parity system. If the input data X7… X0 has even parity then
the third entry of Table 9-5 shows the Σ ODD OUTPUT (pin# 6) is high. Therefore the 9-bit
data X8... X0 comes out of the circuit has odd parity. This is depicted in the third Row of Table
9-5. On the other hand, if X7… X0 has odd parity then the fourth entry of Table 9-5 shows that
Σ ODD OUTPUT (pin# 6) is low. Again the 9-bit number X8…X0 comes out of the circuit
with odd parity.

Figure 9.2. 9-bit Parity Generator/Checker IC

Table 9-5: Truth table showing the function of 74180 the inputs and outputs
INPUTS OUTPUTS
Σ of H’s Σ Σ
Even Odd
at X7 to X0 Even Odd
Even H L H L
Odd H L L H
Even L H L H
Odd L H H L
X H H L L
X L L H H
L=LOW, H=HIGH, X=Don’t Care

Connect pin#14 and pin#3 to Vcc and pin#7 and pin#4 to Ground respectively according to the
pin configuration shown in Figure 9-2. Apply even parity and odd parity numbers to X7…X0
and complete the Table 9-6 by observing the outputs at pin# 5 and pin# 6, to verify the 9-bit
output X8…X0 parity.

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Table 9-6: Truth table of 74180 as Even Parity Generator/Checker

INPUTS OUTPUTS
Σ of 1s Σ Σ
X7 X6 X5 X4 X3 X2 X1 X0 Even Odd
in X7- X0 Even Odd
1 1 0 0 1 1 1 0 1 0
1 1 0 0 0 1 0 0 1 0
1 1 0 0 1 1 1 1 1 0
0 0 0 0 0 0 0 1 1 0
1 0 0 0 1 1 1 0 1 0
1 1 1 1 1 0 1 1 1 0
1 0 1 0 1 0 1 0 1 0
1 0 0 1 0 0 0 1 1 0

Connect pin#14 and pin#4 to Vcc and pin#7 and pin#3 to Ground respectively according to the
pin configuration shown in Figure 9-2. Apply even parity and odd parity numbers to X7…X0
and complete the Table 9-7 by observing the outputs at pin# 5 and pin# 6, to verify the 9-bit
output X8…X0 parity.

Table 9-7: Truth table of 74180 as Odd Parity Generator/Checker

INPUTS OUTPUTS
Σ of 1s Σ Σ
X7 X6 X5 X4 X3 X2 X1 X0 Even Odd
in X7- X0 Even Odd
1 1 0 0 1 1 1 0 0 1
1 1 0 0 0 1 0 0 0 1
1 1 0 0 1 1 1 1 0 1
0 0 0 0 0 0 0 1 0 1
1 0 0 0 1 1 1 0 0 1
1 1 1 1 1 0 1 1 0 1
1 0 1 0 1 0 1 0 0 1
1 0 0 1 0 0 0 1 0 1

Conclusion:
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Lab#14

MOD-10 COUNTER

Objective:
Proceed to implement a decade counter (Mod-10) by using JK flip flop

Theory:
It is often desirable to construct a counter other than 2, 4, and 8 and so on. A smaller modulus
counter can always be constructed from a larger modulus counter by skipping states. Such
counters are said to have a modified count. The two flip-flops in Figure 13-1 have been
connected to provide a mod-10 counter. Since four flip-flops have a natural count of 16, this
counter will skip six states. The truth table shows that this counter progress through the count
sequence 0000 to1010 and then back to 0000. It skips count 1011 to 1111 and that’s why also
called as Decade Counter.

Components required:
74LS76 (Dual Edge triggered JK flip-flop IC), 7420 (Dual 4-input NAND gate IC)

Procedure:
The pin configurations of ICs 74LS76 and 7420 are given in Figures 13.1 and 13.2 respectively.
These ICs are to be used for this experiment. Make the connection of the circuit as shown in
Figure 13.3. Note down the sequence of outputs in Table 13.1 after each successive clock pulse
and draw the timing diagram.

Figure 14.1 74LS76 dual Master-Slave JK Flip-Flop

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Figure 14.2 7420 dual 4 input NAND gate

Figure 14.3 Mod-10 counter using JK Flip-Flop

Observation:
Table 14.1: Truth Table for Mod-10 Counter using Master-Slave JK Flip-Flop
COUNT Q3 (MSB) Q2 Q1 Q0 (LSB)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

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Conclusion:

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