Course | Branch | Subject Subject Name Semester | Unit Name Code No. B.Tech [CSE | IEC-501 | Microprocessors and Controller m 2nd’unit-1 THE 8086 MICROPROCESSOR ARCHITECTURE What are the architecture blocks available in 8086? 8086 has two blocks BIU and EU. addresses on the buses for EU. instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. Architecture of 8086 Introduction : The 8086 microprocessor is an 8-bit/16-bit microprocessor designed by Intel in the late 1970s. It is the first member of the x86 family of microprocessors, which includes many popular CPUs used in personal computers, The architecture of the 8086 microprocessor is based on a complex instruction set computer (CISC) architecture, which means that it supports a wide range of instructions, many of which can perform multiple operations in a single instruction. The 8086 microprocessor has a 20-bit address bus, which can address up to 1 MB of memory, and a 16-bit data bus, which can transfer data between the microprocessor and memory or I/O devices, The 8086 microprocessor has a segmented memory architecture, which means that memory is divided into segments that are addressed using both a segment register and an offset. The segment register points to the start of a segment, while the offset specifies the location of a specific byte within the segment. This allows the 8086 microprocessor to access large amounts of memory, while still using a 16-bit data bus The 8086 microprocessor has two main execution units: the execution unit (EU) and the bus interface unit (BTU). The BIU is responsible for fetching instructions from memory and decoding them, while the EU executes the instructions. The BIU also manages data transfer between the microprocessor and memory or I/O devices. The 8086 microprocessor has a rich set of registers, including general-purpose registers, segment registers, and special registers. The general-purpose registers can be used to store data and perform arithmetic and logical operations, while the segment registers are used to address memory segments. The special registers include the flags register, which stores status information about the result of the previous operation, and the instruction pointer (IP), which points to the next instruction to be executed.A Microprocessor is an Integrated Circuit with all the functions of a CPU. However, it cannot be used stand-alone since unlike a microcontroller it has no memory or peripherals. 8086 does not have a RAM or ROM inside it. However, it has internal registers for storing intermediate and final results and interfaces with memory located outside it through the System Bus. In the case of 8086, it is a 16-bit Integer processor in a 40-pin, Dual Laline Packaged IC. The size of the internal registers(present within the chip) indicates how much information the processor can operate on at a time (in this case 16-bit registers) and how it moves data around internally within the chip, sometimes also referred to as the internal data bus. 8086 provides the programmer with 14 internal registers, each of 16 bits or 2 bytes wide. The main advantage of the 8086 microprocessor is that it supports Pipelining. + In order to increase execution speed and fetching speed, 8086 segments the memory. «Its 20-bit address bus can address IMB of memory, it segments it into 16 64kB segments, + 8086 works only with four 64KB segments within the whole IMB memory. The intemal architecture of Intel $086 is divided into 2 units: The Bus Interface Unit (BIU), and The Execution Unit (EU). These are explained as following below. 1. The Bus Interface Unit (BIU): It provides the interface of $086 to external memory and I/O devices via the System Bus. It performs various machine cycles such as memory read, VO read, ete. to transfer data between memory and 1/0 devices BIU performs the following functions are as follows «It generates the 20-bit physical address for memory access. «It fetches instructions from the memory. + Ittransfers data to and from the memory and VO. + Maintains the 6-byte pre-fetch instruction queue(supports pipelining). BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and an Address Generation Circuit, Instruction Pointer (IP): «Iisa 16-bit register. It holds offset of the next instructions in the Code Segment.+ IP is incremented after every instruction byte is fetched. + IP gets a new value whenever a branch instruction occurs. + CS is multiplied by 10H to give the 20-bit physical address of the Code Segment. + The address of the next instruetion is calculated by using the formula CS x 10H + IP Example: CS = 4321H IP = 1000H then CS x 10H = 43210H + offset = 44210H Here Offset = Instruction Pointer(IP) This is the address of the next instruction. Code Segment register: (16 Bit register): CS holds the base address for the Code Segment. All programs are stored in the Code Segment and accessed via the IP. Data Segment register: (16 Bit register): DS holds the base address for the Data Segment. Stack Segment register: (16 Bit register): SS holds the base address for the Stack Segment. Extra Segment register: (16 Bit register): ES holds the base address for the Extra ‘Segment. Please note that segments are present in memory and segment registers are present in “Microprocessor Segment registers store starting address of each segments. in memory. Address Generation Cireuit: + The BIU has a Physical Address Generation Circuit. + It generates the 20-bit physical address using Segment and Offset addresses using the formula: + In Bus Interface Unit (BIU) the circuit shown by the © symbol is responsible for the calculation unit which is used to calculate the physical address of an instruction in memory. Physical Address = Segment Address x 10H + Offset Address 6 Byte Pre-fetch Queue: + Itis.a 6-byte queue (FIFO). + Fetching the next instruction (by BIU from CS) while executing the current instruction is called pipelining. + Gets flushed whenever a braneh instruction occurs. + The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that can have in 8086 is 6 bytes. Hence to cover up all operands and data fields of maximum size instruction in 8086 Microprocessor there is a Pre-Fetch queue is 6 Bytes. + The pre-Fetch queue is connected with the control unit which is responsible for decoding op-code and operands and telling the execution unit what to do with the help of timing and control signals. + The pre-Fetch queue is responsible for pipelining and because of that 8086 microprocessor is called fetch, decode, execute type microprocessor. Since there are always instructions present for decoding and execution in this queue the speed of execution in the microprocessor is gradually increased. * When there is a 2-byte space in the instruction pre-fetch queue then only the next instruction will be pushed into the queue otherwise if only a 1-byte space is vacant then there will not be any allocation in the queue. It will wait for a spacing of 2 bytes in subsequent queue decoding operations+ Instruction pre-fetch queue works in a sequential manner so if there is any branch condition then in that situation pre-fetch queue fails. Hence to avoid chaos instruction queue is flushed out when any branch or conditional jumps occur. 2.prefetch unit: The Prefetch Unit in the $086 microprocessor is a component responsible for fetching instructions from memory and storing them in a queue. The prefetch unit allows the $086 to perform multiple instruction fetches in parallel, improving the overall performance of the microprocessor. The prefetch unit consists of a buffer and a program counter that are used to fetch instructions from memory. The buffer stores the instructions that have been fetched and the program counter keeps track of the memory location of the next instruction to be fetched. The prefetch unit fetches several instructions ahead of the current instruction, allowing the 8086 to execute instructions from the buffer rather than from memory. This parallel processing of instruction fetches helps to reduce the wait time for memory access, as the 8086 can continue to execute instructions from the buffer while it waits for memory access to complete. This results in improved overall performance, as the 8086 is able to execute more instructions in a given amount of time. The prefetch unit is an imporxtant component of the 8086 microprocessor, as it allows the microprocessor to work more efficiently and perform more instructions in a given amount of time. This improved performance helps to ensure that the S086 remains competitive in its performance and capabilities, even as technology continues to advance, 3. The Execution Unit (EU): The main components of the EU are General purpose registers, the ALU, Special purpose registers, the Instruction Register and Instruction Decoder, and the Flag/Status Register. 1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic operations using the ALU, 2. Sends control signals for intemal data transfer operations within the microprocessor.(Control Unit) 3. Sends request signals to the BIU to access the external module, 4. It operates with respect to T-states (clock cycles) and not machine eycles. 8086 has four 16-bit_general_purpose registers AX, BX, CX, and DX which store intermediate values during execution. Each of these has two 8-bit parts (higher and lower), + AX register: (Combination of Aand ‘An Registers) It holds operands and results during multiplication and division operations. Also an accumulator during String operations. + BX register: (Combination of Brand Bu Registers) It holds the memory address (offset address) in indirect addressing modes. + cx register: (Combination of Cand Cu Registers) It holds the count for instructions like a loop, rotates, shifts and string operations.* DX register: (Combination of Dr and Dx Registers) It is used with AX to hold 32-bit values during multiplication and division. Arithmetic Logie Unit (16-bit): Performs 8 and 16-bit arithmetic and logic operations. Special purpose registers (16-bit): Special purpose registers are called Offset registers also, Which points to specific memory locations under each segment? ‘We can understand the concept of segments as Textbook pages. Suppose there are 10 chapters in one textbook and each chapter takes exactly 100 pages. So the book will contain 1000 pages. Now suppose we want to access page mumber 575 from the book then 500 will be the segment base address which can be anything in the context of microprocessors like Code, Data, Stack, and Extra Segment. So 500 will be segment registers that are present in Bus Interface Unit (BIU). And 500 + 75 is called an offset register through which we can reach on specific page number under a specific segment. Hence 500 is the segment base address and 75 is an offset address or (Instruction Pointer, Stack Pointer, Base Pointer, Source Index, Destination Index) any of the above according to their segment implementation. «Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH, POP, CALL, RET ete. + Base Pointer: BP can hold the offset addresses of any location in the stack segment. It is used to access random locations of the stack. + Source Index: It holds offset address in Data Segment during string operations. + Destination Index: It holds offset address in Extra Segment during string operations. Instruction Register and Instruction Decoder: The EU fetches an opcode from the queue into the instruction register. The instruction decoder decodes it and sends the information to the control cireuit for execution, Flag/Status register (16 bits): It has 9 flags that help change or recognize the state of the microprocessor. 6 Status flags: Carry flag(CF) Parity flag(PF) Auxiliary carry flag(AF) Zero flag(Z) Sign flag(S) Overflow flag (0) Status flags are updated after every arithmetic and logic operation 3 Control flags: 1. Trap flag(TF) 2. Interrupt flag(IF) 3. Direction flag(DF) These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI, ete. The Control flags are used to control certain operations. ake 4.Decode unit: The Decode Unit in the 8086 microprocessor is a component that decodes the instructions that have been fetched from memory. The decode unit takes the machine code instructionsand translates them into micro-operations that can be executed by the microprocessor’s execution unit. The Decode Unit works in parallel with the Prefetch Unit, which fetches instructions from memory and stores them in a queue. The Decode Unit reads the instructions from the queue and translates them into micro-operations that can be executed by the microprocessor. The Decode Unit is an important component of the 8086 microprocessor, as it allows the microprocessor to execute instructions efficiently and accurately. The decode unit ensures that the microprocessor can execute complex instructions, such as jump instructions and loop instructions, by translating them into a series of simple micro-operations. The Decode Unit is responsible for decoding instructions, performing register-to-register operations, and performing memory-to-register operations. It also decodes conditional jumps, calls, and returns, and performs data transfers between memory and registers The Decode Unit helps to improve the performance of the 8086 microprocessor by allowing it to execute instructions quickly and accurately. This improved performance helps to ensure that the 8086 remains competitive in its performance and capabilities, even as technology continues to advance. 5. Control unit: The Control Unit in the 8086 microprocessor is a component that manages the overall operation of the microprocessor. The control unit is responsible for controlling the flow of instructions through the microprocessor and coordinating the activities of the other components, including the Decode Unit, Execution Unit, and Prefeteh Unit. The Control Unit acts as the central coordinator for the microprocessor, directing the flow of data and instructions and ensuring that the microprocessor operates correctly. It also monitors the state of the microprocessor, ensuring that the correct sequence of operations is followed, The Control Unit is responsible for fetching instructions from memory, decoding them, executing them, and updating the microprocessor’s state. It also handles interrupt requests and performs system management tasks, such as power management and error handling. The Control Unit is an essential component of the 8086 microprocessor, as it allows the microprocessor to operate efficiently and accurately. The control unit ensures that the microprocessor can execute complex instructions, such as jump instructions and loop instructions, by coordinating the activities of the other components. The Control Unit helps to improve the performance of the 8086 microprocessor by managing the flow of instructions and data through the microprocessor, ensuring that the microprocessor operates correctly and efficiently. This improved performance helps to ensure that the 8086 remains competitive in its performance and capabilities, even as technology continues to advance.The 8086 microprocessor uses three different buses to transfer data and instructions between the microprocessor and other components in a computer system. These buses are: LAddress Bus: The address bus is used to send the memory address of the instruction or data being read or written. The address bus is 16 bits wide, allowing the 8086 to address up to 64 kilobytes of memory. 2.Data Bus: The data bus is used to transfer data between the microprocessor and memory. The data bus is 16 bits wide, allowing the 8086 to transfer 16-bit data words at a time. 3.Control Bus: The control bus is used to transfer control signals between the microprocessor and other components in the computer system. The control bus is used to send signals such as read, write, and interrupt requests, and to transfer status information between the microprocessor and other components. The buses in the 8086 microprocessor play a crucial role in allowing the microprocessor to access and transfer data from memory. as well as to interact with other components in the computer system. The 8086's ability to use these buses efficiently and effectively helps to ensure that it remains competitive in its performance and capabilities, even as technology continues to advance. Execution of whole 8086 Architecture: 1. Alll instructions are stored in memory hence to fetch any instruction first task is to obtain the Physical address of the instruetion is to be fetched. Hence this task is done by Bus Interface Unit (BIU) and by Segment Registers. Suppose the Code segment has a Segment address and the Instruction pointer has some offset address then the physical address calculator circuit calculates the physical address in which our instruction is to be fetched. 2. After the address calculation instruction is fetched from memory and it passes through C-Bus (Data bus) as shown in the figure, and according to the size of the instruction, the instruction pre-fetch queue fills up. For example MOV AX, BX is | Byte instruction so it will take only the 1* block of the queue, and MOV BX,4050H is 3 Byte instruction so it will take 3 blocks of the pre-fetch queue. 3. When our instruction is ready for execution, according to the FIFO property of the queue instruction comes into the control system or control circuit which resides in the Execution unit. Here instruction decoding takes place. The decoding control system generates an opcode that tells the microprocessor unit which operation is to be performed. So the control system sends signals all over the microprocessor about what to perform and what to extract from General and Special Purpose Registers. 4, Hence after decoding microprocessor fetches data from GPR and according to instruetions like ADD, SUB, MUL, and DIV data residing in GPRs are fetched and put as ALU’s input. and after that addition, multiplication, division, or subtraction whichever calculation is to be carried out. According to arithmetic, flag register values change dynamically. 6. While Instruction was decoding and executing from step-3 of our algorithm, the Bus imerface Unit doesn’t remain idle. it continuously fetches an instruction from memory and put it in a pre-fetch queue and gets ready for execution in a FIFO manner whenever the time arrives. 7. So in this way, unlike the 8085 microprocessor, here the fetch, decode, and execution process happens in parallel and not sequentially. This is called pipelining, and because of the instruction pre-fetch queue, all fetching, decoding, and execution process happenside-by-side, Hence there is partitioning in 8086 architecture like Bus Interface Unit and Execution Unit to support Pipelining phenomena. Advantages of Architecture of 8086: The architecture of the $086 microprocessor provides several advantages, including: 1. Wide range of instructions: The 8086 microprocessor supports a wide range of instructions, allowing programmers to write complex programs that can perform many different operations. 2. Segmented memory architecture: The segmented memory architecture allows the 8086 microprocessor to address large amounts of memory, up to | MB, while still using a 16- bit data bus. 3. Powerful instruction set: The instruction set of the 8086 microprocessor includes many powerful instructions that can perform multiple operations in a single instruction, reducing the number of instructions needed to perform a given task. 4, Multiple execution units: The 8086 microprocessor has two main execution units, the execution unit and the bus interface unit, which work together to efficiently execute instructions and manage data transfer. 5. Rich set of registers: The 8086 microprocessor has a rich set of registers, including general-purpose registers, segment registers, and special registers, allowing programmers to efficiently manipulate data and control program flow. 6. Backward compatibility: The architecture of the 8086 microprocessor is backward compatible with earlier 8-bit microprocessors, allowing programs written for these earlier microprocessors to be easily ported to the 8086 microprocessor. Dis-advantages of Architecture of 8086: The architecture of the $086 microprocessor has some disadvantages, including: 1. Complex programming: The architecture of the 8086 microprocessor is complex and can be difficult to program, especially for novice programmers who may not be familiar with the assembly language programming required for the 8086 microprocessor. Segmented memory architecture: While the segmented memory architecture allows the 8086 microprocessor to address a large amount of memory, it can be difficult to program and manage, as it requires programmers to use both segment registers and offsets to address memory. 3. Limited performance: The 8086 microprocessor has a limited performance compared to modern microprocessors, as it has a slower clock speed and a limited number of execution units. 4. Limited instruction set: While the 8086 microprocessor has a wide range of instructions, it has a limited instruction set compared to modern microprocessors, which can limit its functionality and performance in certain applications. 5. Limited memory addressing: The 8086 microprocessor can only address up to 1 MB of memory, which can be limiting in applications that require large amounts of memory. 6. Lack of built-in features: The 8086 microprocessor lacks some built-in features that are commonly found in modern microprocessors, such as hardware floating-point support and virtual memory management.Memory Segmentation in 8086 Microprocessor Segmentation is the process in which the main memory of the computer is logically divided into different segments and each segment has its own base address. It is basically used to enhance the speed of execution of the computer system, so that the processor is able to fetch and execute the data from the memory easily and fast. Need for Segmentation - The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as Segment Registers. + Code segment register (CS): is used for addressing memory location in the code segment of the memory, where the executable program is stored. + Data segment register (DS): points to the data segment of the memory where the data is stored. + Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in the memory. + Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is that segment of memory which is used to store stack data The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the IMB memory locations. The four segment registers actually contain the upper 16 bits of the starting addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of time. A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up of contiguous memory locations, It is an independent, separately addressable unit. Starting address will always be changing, It will not be fixed Note that the $086 does not work the whole IMB memory at any given time. However, it works only with four 64KB segments within the whole IMB memory. Below is the one way of positioning four 64 kilobyte segments within the 1M byte memory space of an 8086.Physical foes, = Memory FFFFFH |¢— Hohestadsess TEFFF ago of EcraSegmet || Extra 3] | Segment Four segment registers InBlu 70000 jae Socom o xa Segment SRF. . es[7 [o[o|[o Jat— op ot Sack Seamer esta [ofo fo 2| | Stack ss[s [oo [o ‘Segment os[ 2 fo fo fo 50000 Fh ag Bota of Sack Segment a SFFFFH Jat— Top of Code Segment ‘Segment registers hold a] | Sede the upper 16 bits of the ‘Segment starting addresses of spon veate cana four memory segments. >) -——S- that 8086 is working with DEFFFH Jae Top of Data Segment at any particular time a| | Data 8] | Segment > 20000 H ag Soto of bata Segment ‘Types Of Segmentation — 1. Overlapping Segment — A segment starts at a particular address and its maximum size can go up to 64kilobytes. But if another segment starts along with this 64kilobytes location of the first segment, then the two are said to be Overlapping Segment. 2. Non-Overlapped Segment ~ A segment starts at a particular address and its maximum size can go up to G4kilobytes. But if another segment starts before this G4kilobytes location of the first segment, then the two segments are said to be Non-Overlapped Segimem. Rules of Segmentation Segmentation process follows some rules as follows + The starting address of a segment should be such that it can be evenly divided by 16. + Minimum size of a segment can be 16 bytes and the maximum can be 64 kB. coo cP os aX OLS! ss SP.OP ‘Ader he stack ox oLs! ‘Adoress of destraton did (or ssing operators) Advantages of the Segmentation The main advantages of segmentation are as follows: It provides a powerful memory management mechanism. Data related or stack related operations can be performed in different segments. Code related operation can be done in separate code segments. It allows to processes to easily share data.+ It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16 bit registers to give an addressing capability of 1 Megabytes. Without segmentation, it would require 20 bit registers, + Itis possible to enhance the memory size of code data or stack segments beyond 64 KB by allotting more than one segment for each area 8086 Microprocessor Linking and Relocation Execution of a program Binary progras — ~-= Control flow Problem: Write an assembly language program to transfer a block of bytes from one memory location to another memory location by using string instruction.Example: Input Data 04 03 05 06 | 08 Vemoy 500 | SOL ] 502] 503 | S04 Address Output Data 03 | 05 | 06 | 08 Memory Address 600 | 601 | 602 | 603 Example: 1. In this example, the counter value stored in CX register is 4. 2. The block of data which is stored from memory location starting from 501 to 504 offset is transferred to another memory location which is starting from 600 to 603 offset. Assumptions: + The value of counter which tells the number of bytes to be transferred is stored at offset 500. + The 8-bit data which have to be transfer is stored in continuous memory location starting from 501. + The data is transferred to a continuous memory location starting from 600. + The value of DS and ES is taken equal to 0000. + the program starts from offset 400. CLD instruction is used to clear the directional flag, i.e., DF=0. Now, value of SI and DI will be increased. SI=SI+1 DI=DI+1REP instruction is used to repeat the step until the value of CX is not equal to zero and the value of CX is decremented by one at every step, i.e., CX=CX-1 MOVSSB instruction is used to transfer bytes only from source memory location (MADS) to destination memory location (MAES). MADS-->MAES where MADS=DS*10+SI MAES=ES*10+01 Here, value of S| and DI is updated automatically. if DF=@, SI=SI+1 and DI=DI+1 Algorithm: . Set the value of offset SI equal to 500. . set the value of offset DI equal to 600. . load the value 0000 into register AX. . load the data of AX register into DS(data segment). . load the data of AX register into ES(extra segment). . load the data of offset SI into the CL register and load value 00 into CH register. . increment the value of S| by one. . clear the directional flag so that data is read from lower memory to higher memory location. . check the value of CX, if not equal to zero then repeat step 10 otherwise go to step 11. 10. transfer the data from source memory location to destination memory location and decrease the value of CX by one. 11. Stop. Microprocessor - 8086 Addressing Modes ON OOBON= © The different ways in which a source operand is denoted in an instruction is known as addressing modes. There are 8 different addressing modes in 8086 programming — Immediate addressing mode The addressing mode in which the data operand is a part of the instruction itself is known as immediate addressing mode. Example MOV CX, 4929 H, ADD AX, 2387 H, MOV AL, FFHRegister addressing mode It means that the register is the source of an operand for an instruction. Example MOV CX, AX; copies the contents of the 16-bit AX register into 5 the 16-bit CX register), ADD BX, AX Direct addressing mode The addressing mode in which the effective address of the memory location is written directly in the instruction. Example MOV AX, [1592H], MOV AL, [0300H] Register indirect addressing mode This addressing mode allows data to be addressed at any memory location through an offset address held in any of the following registers: BP, BX, DI & SI. Example MOV AX, [BX] ; Suppose the register BX contains 4895H, then the contents ; 4895H are moved to AX, ADD CX, {BX} Based addressing mode In this addressing mode, the offset address of the operand is given by the sum of contents of the BX/BP registers and 8-bit/16- bit displacement. Example MOV DX, [BX+04], ADD CL, [BX+08] Indexed addressing mode In this addressing mode, the operands offset address is found by adding the contents of SI or DI register and 8-bit/16-bit displacements.Example MOV BX, [SI+16], ADD AL, [DI=16] Based-index addressing mode In this addressing mode, the offset address of the operand is computed by summing the base register to the contents of an Index register. Example ADD CX, [AX+SI], MOV AX, [AX+DI] Based indexed with displacement mode In this addressing mode, the operands offset is computed by adding the base register contents. An Index registers contents and 8 or 16-bit displacement. Example MOV AX, [BX+DI-08], ADD CX, [BX+SI-16] Microprocessor - 8086 Pin Configuration 8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip. Let us now discuss in detail the pin configuration of a $086 Microprocessor. 8086 Pin Diagram Here is the pin diagram of 8086 microprocessor —} 40 [2 veo rou 9 [5 Ady Ayia 20 aes We C4 37D Ase ao, 1s 96 Awe Ade 16 5 5 Awe an, CI}? mS bes, ao, Cie 3 MN ao, 9 2 f ao, C10 oe a aor, oLD) a Con 20 AGGT, = (MLO) an, Ci aR mH = = ao, C13 aos ud) a, C4 7% (orm ao, O18 aoe oe i be a», 6 25 oy Me nu 7 24 {2 @s, nT) ata) 18 a {> Test ox cs a ano 20 21 reser Let us now discuss the signals in detail - Power supply and frequency signals It uses SV DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation. Clock signalClock signal is provided through Pin-19. It provides timing to the processor for operations. Its frequency is different for different versions, ie. SMHz, 8MHz and 10MHz. Address/data bus ADO-ADI15. These are 16 address/data bus. ADO-AD7 carries low order byte data and ADSADI5 carries higher order byte data. During the first clock cycle, it carries 16-bit address and after that it carries 16-bit data, Address/status bus A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-bit address and later it carries status signals. S7/BHE BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using data bus D8-D15. This signal is low during the first clock eyele, thereafter it is active. Read(S\overline{RD}S) It is available at pin 32 and is used to read signal for Read operation. Ready It is available at pin 22. It is an acknowledgement signal from I/O devices that data is transferred. It is an active high signal. When it is high, it indicates that the device is ready to transfer data. When it is low, it indicates wait state.RESET It is available at pin 21 and is used to restart the execution. It causes the processor to immediately terminate its present activity. This signal is active high for the first 4 clock cycles to RESET the microprocessor. INTR It is available at pin 18, It is an interrupt request signal, which is sampled during the last clock cyele of each instruction to determine if the processor considered this as an interrupt or not. ‘NMI It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which causes an interrupt request to the microprocessor. overline(TEST}S This signal is like wait state and is available at pin 23. When this signal is high, then the processor has to wait for IDLE state, else the execution continues. MN/S\overline{MX}$ It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor is to operate in; when it is high, it works in the minimum mode and vice- aversa. INTAIt is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor receives this signal, it acknowledges the interrupt. ALE It stands for address enable latch and is available at pin 25. A positive pulse is generated each time the processor begins any operation. This signal indicates the availability of a valid address on the addvess/data lines. DEN It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The transreceiver is a device used to separate data from the address/data bus. DIR It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of data flow through the transreceiver. When it is high, data is transmitted out and vice-a-versa. MAO This signal is used to distinguish between memory and /O operations. When it is high, it indicates /O operation and when it is low indicates the memory operation. Tt is available at pin 28, WRIt stands for write signal and is available at pin 29. It is used to write the data into the memory or the output device depending on the status of M/TO signal. HLDA It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges the HOLD signal. HOLD This signal indicates to the processor that external devices are requesting to access the address/data buses. It is available at pin 31. QS1 and QS0 These are queue status signals and are available at pin 24 and 25. These signals provide the status of instruction queue. Their conditions are shown in the following table ~ QS0 QS1_ Status 0 0 Nooperation 0 1 First byte of opcode from the queue 1 0 Empty the queue 1 1 Subsequent byte from the queue ‘80, S1,S2 These are the status signals that provide the status of operation, which is used by the Bus Controller 8288 to generate memory & V/O control signals. These are available at pin 26, 27, and 28. Following is the table showing their status ~$2 S180 Status 0 0 0 _ Interrupt acknowledgement 0 0 1 WORead 0 1 0 LOWrite o 1 1 Hatt 1 0 0 Opeode fetch 1 0 1 Memory read 1 10 Memory write 1 ot 1 Passive Lock When this signal is active, it indicates to the other processors not to ask the CPU to leave the system bus, It is activated using the LOCK prefix on any instruction and is available at pin 29, RQGTI and RYGTO These are the Request/Grant signals used by the other processors requesting the CPU to release the system bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GTO has a higher priority than RQ/GTI. Microprocessor - 8086 Interrupts Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to access the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine), which is a short program to instruet the microprocessor on how to handle the interrupt. The following image shows the types of interrupts we have in a 8086 microprocessor ~Interrupts. Hardware Software Interrupt Interrupt Maskable Interrupt a Hardware Interrupts ‘Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the microprocessor. The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called interrupt acknowledge. NMI It isa single non-maskable interrupt pin (NMD having higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt. When this interrupt is activated, these actions take place ~ + Completes the current instruction that is in progress. + Pushes the Flag register values on to the stack. + Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack. + IPs loaded from the contents of the word location 00008H. + CS is loaded from the contents of the next word location 0000AH. + Interrupt flag and trap flag are reset to 0. INTR The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction. The INTR interrupt is activated by an /O port. Ifthe interrupt is enabled and NMI is disabled, then the microprocessor first completes the current execution and sends *0” onINTA pin twice. The first “O° means INTA informs the extemal device to get ready and during the second ‘0° the microprocessor receives the 8 bit, say X, from the programmable interrupt controller. These actions are taken by the microprocessor — + First completes the current instruction + Activates INTA output and receives the interrupt type, say X. + Flag register value, CS value of the return address and IP value of the return address are pushed on to the stack. + IP value is loaded from the contents of word location X = 4 + Sis loaded from the contents of the next word location. + Interrupt flag and trap flag is reset to 0 Software Interrupts Some instructions are inserted at the desired position into the program to create interrupts. These interrupt instructions can be used to test the working of various interrupt handlers. It includes — INT- Interrupt instruction with type number It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt type number. There are 256 interrupt types under this group. Its execution includes the following steps ~ + Flag register value is pushed on to the stack. + CS value of the retum address and IP value of the return address are pushed on to the stack. + IPs loaded from the contents of the word location “type number’ * 4 + CS is loaded from the contents of the next word location. + Interrupt Flag and Trap Flag are reset to 0 The starting address for type0 interrupt is 000000H, for typel interrupt is 00004H similarly for type? is 00008H and ......s0 on. The first five pointers are dedicated interrupt pointers. ie.- TYPE 0 interrupt represents division by zero situation, TYPE 1 interrupt represents single-step execution during the debugging of a program. TYPE 2 interrupt represents non-maskable NMI interrupt. TYPE 3 interrupt represents break-point interrupt. TYPE 4 interrupt represents overflow interrupt. The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts from 32 to Type 255 are available for hardware and software interrupts.INT 3-Break Point Interrupt Instruction It isa I-byte instruction having op-code is CCH. These instructions are inserted into the program so that when the processor reaches there, then it stops the normal execution of program and follows the break-point procedure Its execution includes the following steps — + Flag register value is pushed on to the stack. + CS value of the return address and IP value of the return address are pushed on to the stack. + IPs loaded from the contents of the word location 34 = 0000CH + CSis loaded from the contents of the next word location + Interrupt Flag and Trap Flag are reset to 0 INTO - Interrupt on overflow instruction It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is set to | and branches to the interrupt handler whose interrupt type number is 4, If the overflow flag is reset then, the execution continues to the next instruction, Its execution includes the following steps ~ + Flag register values are pushed on to the stack. + CS value of the return address and IP value of the return address are pushed on to the stack. + IPs loaded from the contents of word location 44 ~ 00010H + CS iis loaded from the contents of the next word location Interrupt flag and Trap flag are reset to 0 Microprocessor - 8086 Instruction Sets The 8086 microprocessor supports 8 types of instructions ~ Data Transfer Instructions Arithmetic Instructions Bit Manipulation Instructions String Instructions Program Execution Transfer Instructions (Branch & Loop Instructions) Processor Control Instructions «Iteration Control Instructions + Interrupt Instructions Let us now discuss these instruction sets in detail. Data Transfer Instructions These instructions are used to transfer the data from the source operand to the destination operand. Following are the list of instructions under this group ~Instruction to transfer a word + MOY ~ Used to copy the byte or word fiom the provided source to the provided destination. PPUSH — Used to put a word at the top of the stack. POP ~ Used to get a word from the top of the stack to the provided location, PUSHA — Used to put all the registers into the stack. POPA ~ Used to get words from the stack to all registers. XCHG ~ Used to exchange the data from two locations. XLAT ~ Used to translate a byte in AL using a table in the memory. Instructions for input and output port transfer + IN— Used to read a byte or word from the provided port to the accumulator. + OUT = Used to send out a byte or word from the accumulator to the provided port, Instructions to transfer the address + LEA - Used to load the address of operand into the provided register. + LDS - Used to load DS register and other provided register from the memory + LES ~ Used to load ES register and otier provided register from the memory. Instructions to transfer flag registers + LAHF - Used to load AH with the low byte of the flag register. + SAHIF — Used to store AH register to low byte of the flag register. + PUSHE - Used to copy the flag register at the top of the stack. + POPF - Used to copy a word at the top of the stack to the flag register. Arithmetic Instructions These instructions are used to perform arithmetic operations like addition, subtraction, anultiplication, division, ete, Following is the list of instructions under this group ~ Instructions to perform addition + ADD ~ Used to add the provided byte to byte/word to word. «ADC - Used to add with carry. + INC — Used to increment the provided byte/word by 1 + AAA — Used to adjust ASCII after addition. + DAA - Used to adjust the decimal after the addition/subtraction operation. Instructions to perform subtraction SUB ~ Used to subtract the byte from byte/word from word. SBB - Used to perform subtraction with borrow: DEC ~ Used to decrement the provided byte‘word by 1. NPG ~ Used to negate each bit of the provided byte/word and add 1/2’s complement. CMP ~ Used to compare 2 provided byte/word. AAS ~ Used to adjust ASCII codes after subtraction, DAS ~ Used to adjust decimal after subtraction, Instruction to perform multiplication + MUL ~ Used to multiply unsigned byte by byte'word by word.+ IMUL ~ Used to multiply signed byte by byte/word by word. + AAM — Used to adjust ASCII codes after multiplication, Instructions to perform division + DIV~ Used to divide the unsigned word by byte or unsigned double word by word. + IDIV — Used to divide the signed word by byte or signed double word by word + AAD ~ Used to adjust ASCII codes after division. + CBW — Used to fill the upper byte of the word with the copies of sign bit of the lower byte + CWD - Used to fill the upper word of the double word with the sign bit of the lower word Bit Manipulation Instructions These instructions are used to perform operations where data bits are involved, i.e. operations like logical, shift, etc Following is the list of instruetions under this group — Instructions to perform logical operation NOT - Used to invert each bit of a byte or word, AND - Used for adding each bit in a byte/word with the corresponding bit in another byte/word. + OR — Used to multiply each bit in a byte/word with the corresponding bit in another byte/word. + XOR — Used to perform Exclusive-OR operation over each bit in a byte/word with the corresponding bit in another byte/word, + TEST - Used to add operands to update flags, without affecting operands. Instructions to perform shift operations + SHL/SAL - Used to shift bits of a byte/word towards left and put zero(S) in LSBs. + SHR ~ Used to shift bits of a byte/word towards the right and put zero(S) in MSBs + SAR - Used to shift bits of a byte/word towards the right and copy the old MSB into the new MSB. Instructions to perform rotate operations + ROL — Used to rotate bits of byte/word towards the left, Le. MSB to LSB and to Canry Flag [CF]. + ROR — Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag [CF], * RCR — Used to rotate bits of byte/word towards the right, ie. LSB to CF and CF to MSB. + RCL ~ Used to rotate bits of byte/word towards the lefi, ie. MSB to CF and CF to LSB. String Instructions String is a group of bytes/words and their memory is always allocated in a sequential order. Following is the list of instructions under this group ~+ REP ~ Used to repeat the given instruction till CX 0. « REPE/REPZ — Used to repeat the given instruction until CX = 0 or zero flag ZF = 1 + REPNE/REPNZ ~ Used to repeat the given instruction until CX = 0 or zero flag ZF + MOVS/MOVSB/MOVSW — Used to move the byte/word from one string to another. + COMS/COMPSB/COMPSW — Used to compare two string bytes/words. + INS/INSB/INSW ~ Used as an input string/byte/word from the 1/0 port to the provided memory location, + OUTS/OUTSB/OUTSW — Used as an output string/byte/word from the provided memory location to the /O port. + SCAS/SCASB/SCASW ~ Used to scan a string and compare its byte with a byte in AL or string word with a word in AX. + LODS/LODSB/LODSW — Used to store the string byte into AL or string word into AX. Program Execution Transfer Instructions (Branch and Loop Instructions) These instructions are used to transfer/branch the instructions during an execution. It includes the following instructions ~ Instructions to transfer the instruction during an execution without any condition ~ + CALL - Used to call a procedure and save their return address to the stack, + RET - Used to retum from the procedure to the main program + IMP — Used to jump to the provided address to proceed to the next instruction. Instructions to transfer the instruction during an execution with some conditions ~ JAJINBE — Used to jump if above/not below/equal instruction satisfies JAE/INB ~ Used to jump if above/not below instruction satisfies. JBE/JNA ~ Used to jump if below/equal/ not above instruction satisfies. JC — Used to jump if carry flag CF = 1 JE/JZ.~ Used to jump if equal/zero flag ZF = 1 JG/INLE ~ Used to jump if greater/not less than/equal instruction satisfies. JGE/INL ~ Used to jump if greater than/equal not less than instruction satisfies JLJINGE ~ Used to jump if less than/not greater than/equal instruetion satisfies JLE/JNG ~ Used to jump if less than/equal/if not greater than instruction satisfies. INC ~ Used to jump if no carry flag (CF = 0) INE/INZ ~ Used to jump if not equal/zero flag ZF = 0 JNO — Used to jump if no overflow flag OF = 0 INP/JPO — Used to jump if not parity/parity odd PF = 0 INS ~ Used to jump if not sign SF =0 JO — Used to jump if overflow flag OF = JP/JPE ~ Used to jump if parity’parity even PF JS — Used to jump if sign flag SF = 1 Processor Control Instructions These instructions are used to control the processor action by setting/resetting the flag values,Following are the instructions under this group ~ STC ~ Used to set carry flag CF to 1 CLC ~ Used to clear’reset carry flag CF to 0 CMC ~ Used to put complement at the state of carry flag CF. STD ~ Used to set the direction flag DF to | CLD — Used to clear’reset the direction flag DF to 0 STI — Used to set the interrupt enable flag to 1, ie., enable INTR input. CLI - Used to clear the interrupt enable flag to 0, i.e., disable INTR input. Iteration Control Instructions These instructions are used to execute the given instructions for number of times. Following is the list of instructions under this group — + LOOP - Used to loop a group of instructions until the condition satisfies, ie., CX = 0 + LOOPE/LOOPZ ~ Used to loop a group of instructions till it satisfies ZF = | & C) LOOPNZ ~ Used to loop a group of instructions till it satisfies ZF = 0 & + JCXZ ~ Used to jump to the provided address if CX = 0 Interrupt Instructions These instructions are used to call the interrupt during program execution. + INT — Used to interrupt the program during execution and calling service specified + INTO — Used to interrupt the program during execution if OF = | + IRET ~ Used to retum from interrupt service to the main program Data transfer instructions in 8086 microprocessor These instructions are used to transfer the data from the source operand to the destination operand. These are also known as copy instructions. Let us see the data transfer instructions of 8086 microprocessor. Here the D and S are destination and source respectively. D and S can be either register, data or memory address. Opcode Operand Description MOV D,S Used to copy the byte or word from the provided source to the provided destination. PUSH D Used to put a word at the top of the stack. POP D Used to get a word from the top of the stackOpcode Operand Description to the provided location. PUSHA Used to put all the registers into the stack. POPA ---- Used to get words from the stack to all registers, XCHG D,S Used to exchange the data from two locations. IN DS Used to read a byte or word from the provided port to the accumulator. OUT D,S Used to send out a byte or word from the accumulator to the provided port. XLAT~ ---- Used to translate a byte in AL using a table in the memory. LAHF~ ---- Used to load AH with the low byte of the flag register. SAHF~ ---- Used to store AH register to low byte of the flag register. PUSHF ---- Used to copy the flag register at the top of the stack. POPF~ ---- Used to copy a word at the top of the stack to the flag register. What is branch instruction in microprocessor? The branch instructions are used to change the sequence of instruction execution. Use branch instructions to change the sequence of instruction execution. Since all branch instructions are on word boundaries, the processor performing the branch ignores bits 30 and 31 of the generated branch target address. Machine Control Instructions in Microprocessor Introduction Microprocessors are electronic devices that process digital information using instructions stored in memory. Machine control instructions are a type of instructionthat control machine functions such as Halt, Interrupt, or do nothing. These instructions alter the different type of operations executed in the processor. In this article, we will discuss the various types of machine control instructions found in microprocessors and their significance in controlling the microprocessor’s operations. Types of Machine Control Instructions: The following are the types of Machine control instructions « NOP (No operation) + HLT (Halt) - DI (Disable interrupts) - EI (Enable interrupts) . SIM (Set interrupt mask) awrpwne RIM (Reset interrupt mask) 1. NOP (No operation) Opcode- 00 Operand- None Length- 1 byte M-Cycles- 1 T-states- 4 Hex code- 00 NOP is used when no operation is performed. It is commonly used to fill in time delay or to delete and insert instructions while troubleshooting. During the execution of NOP, no flags are affected. 2. HLT (Halt) Opcode- 76 Operand- None Length- 1 byte M-Cycles- 2 or more T-states- 5 or more Hex code- 76 HLT is used to stop the execution of the program temporarily. The microprocessor finishes executing the current instruction and halts any further execution. The contents of the registers are unaffected during the HLT state. HLT can be used to enter a wait state in which the microprocessor waits for a specific event to occur before resuming execution. 3. DI (Disable interrupts) Opcode- F3 Operand- None Length- 1 byteM-Cycles- 1 T-states- 4 Hex code- F3 Dl is used when the execution of a code sequence cannot be interrupted. For example, in critical time delays, this instruction is used at the beginning of the code and the interrupts are enabled at the end of the code. The TRAP interrupt cannot be disabled 4. El (Enable interrupts) Opcode- FB Operand- None Length- 1 byte M-Cycles- 1 T-states- 4 Hex code- FB Elis used to enable interrupts after a system reset or the acknowledgement of an interrupt. The Interrupt Enable flip-flop is reset, thus disabling the interrupts. 5. SIM (Set interrupt mask) Opcode- 30 Operand- None Length- 1 byte M-Cycles- 1 T-states- 4 Hex code- 30 SIM is used for the implementation of different interrupts of 8085 microprocessor like RST 7.5, 6.5, and 5.5 and also serial data output. It does not affect the TRAP interrupt. 6. RIM (Reset interrupt mask) Opcode- 20 Operand- None Length- 1 byte M-Cycles- 1 T-states- 4 Hex code- 20 RIM is a multipurpose instruction used to read the status of 8085 interrupts 7.5, 6.5, 5.5, and to read serial data input bit. Application of Machine Control Instructions Machine control instructions are used in a variety of applications, including embedded systems, control systems, and industrial automation.+ In embedded systems, machine control instructions are used to control the microprocessor’s operations, including the timing and sequencing of instructions. + Incontrol systems, machine control instructions are used to monitor and control physical processes, such as temperature, pressure, and flow. + In industrial automation, machine control instructions are used to control robots, assembly lines, and other machines. Features of Machine Control Instructions Machine control instructions have specific features that affect the microprocessor’s operations. For example, the HLT instruction halts any further execution of instructions by the microprocessor, while the NOP. instruction does not affect the microprocessor’s state. The DI and El instructions are used to disable and enable interrupts temporarily, respectively. Limitations of Machine Control Instructions Machine control instructions can have limitations that affect the performance and reliability of microprocessors. For example, the HLT instruction can cause the microprocessor to enter a wait state indefinitely, which can impact the system's responsiveness. Additionally, the use of interrupts can cause unpredictable behavior in certain situations, such as when multiple interrupts are received simultaneously. Microprocessor - 8086 Instruction Sets The 8086 microprocessor supports 8 types of instructions — + Data Transfer Instructions + Arithmetic Instructions + Bit Manipulation Instructions + String Instructions + Program Execution Transfer Instructions (Branch & Loop Instructions) + Processor Control Instructions + Iteration Control Instructions + Interrupt Instructions Let us now discuss these instruction sets in detail. Data Transfer Instructions These instructions are used to transfer the data from the source operand to the destination operand. Following are the list of instructions under this group —Instruction to transfer a word + MOV — Used to copy the byte or word from the provided source to the provided destination. PPUSH — Used to put a word at the top of the stack. POP — Used to get a word from the top of the stack to the provided location. + PUSHA — Used to put all the registers into the stack. POPA — Used to get words from the stack to all registers. XCHG — Used to exchange the data from two locations. XLAT — Used to translate a byte in AL using a table in the memory. Instructions for input and output port transfer + IN - Used to read a byte or word from the provided port to the accumulator. + OUT — Used to send out a byte or word from the accumulator to the provided port. Instructions to transfer the address + LEA — Used to load the address of operand into the provided register. + LDs — Used to load DS register and other provided register from the memory » LES — Used to load ES register and other provided register from the memory. Instructions to transfer flag registers » LAHF — Used to load AH with the low byte of the flag register. + SAHF — Used to store AH register to low byte of the flag register. « PUSHF — Used to copy the flag register at the top of the stack. + POPF — Used to copy a word at the top of the stack to the flag register. Arithmetic Instructions These instructions are used to perform arithmetic operations like addition, subtraction, multiplication, division, etc. Following is the list of instructions under this group —Instructions to perform addition + ADD — Used to add the provided byte to byte/word to word. + ADC — Used to add with carry. + INC - Used to increment the provided byte/word by 1. + AAA — Used to adjust ASCII after addition. + DAA — Used to adjust the decimal after the addition/subtraction operation. Instructions to perform subtraction + SUB — Used to subtract the byte from byte/word from word. + SBB — Used to perform subtraction with borrow. + DEC — Used to decrement the provided byte/word by 1. + NPG — Used to negate each bit of the provided byte/word and add 1/2’s complement. + CMP - Used to compare 2 provided byte/word. + AAS — Used to adjust ASCII codes after subtraction. + DAS — Used to adjust decimal after subtraction. Instruction to perform multiplication + MUL — Used to multiply unsigned byte by byte/word by word. + IMUL — Used to multiply signed byte by byte/word by word. + AAM — Used to adjust ASCII codes after multiplication. Instructions to perform division + DIV —- Used to divide the unsigned word by byte or unsigned double word by word. + IDIV — Used to divide the signed word by byte or signed double word by word. + AAD — Used to adjust ASCII codes after division. + CBW - Used to fill the upper byte of the word with the copies of sign bit of the lower byte. + CWD - Used to fill the upper word of the double word with the sign bit of the lower word. Bit Manipulation Instructions These instructions are used to perform operations where data bits are involved, i.e. operations like logical, shift, etc. Following is the list of instructions under this group —Instructions to perform logical operation NOT — Used to invert each bit of a byte or word. AND — Used for adding each bit in a byte/word with the corresponding bit in another byte/word. OR — Used to multiply each bit in a byte/word with the corresponding bit in another byte/word. XOR — Used to perform Exclusive-OR operation over each bit in a byte/word with the corresponding bit in another byte/word. TEST — Used to add operands to update flags, without affecting operands. Instructions to perform shift operations SHL/SAL — Used to shift bits of a byte/word towards left and put zero(S) in LSBs. SHR — Used to shift bits of a byte/word towards the right and put zero(S) in MSBs. SAR — Used to shift bits of a byte/word towards the right and copy the old MSB into the new MSB. Instructions to perform rotate operations ROL — Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag [CF]. ROR -— Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag [CF]. RCR — Used to rotate bits of byte/word towards the right, i.e, LSB to CF and CF to MSB. RCL — Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB. String Instructions String is a group of bytes/words and their memory is always allocated in a sequential order. Following is the list of instructions under this group — REP — Used to repeat the given instruction till CX + 0. REPE/REPZ — Used to repeat the given instruction until CX = 0 or zero flag ZF = 1. REPNE/REPNZ — Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.+ MOVS/MOVSB/MOVSW — Used to move the byte/word from one string to another. + COMS/COMPSB/COMPSW — Used to compare two string bytes/words. + INS/INSB/INSW — Used as an input string/byte/word from the I/O port to the provided memory location. + OUTS/OUTSB/OUTSW — Used as an output string/byte/word from the provided memory location to the I/O port. + SCAS/SCASB/SCASW — Used to scan a string and compare its byte with a byte in AL or string word with a word in AX. + LODS/LODSB/LODSW -— Used to store the string byte into AL or string word into AX. Program Execution Transfer Instructions (Branch and Loop Instructions) These instructions are used to transfer/branch the instructions during an execution. It includes the following instructions — Instructions to transfer the instruction during an execution without any condition — + CALL — Used to call a procedure and save their return address to the stack. + RET — Used to return from the procedure to the main program. + JMP — Used to jump to the provided address to proceed to the next instruction. Instructions to transfer the instruction during an execution with some conditions — + JA/JINBE — Used to jump if above/not below/equal instruction satisfies. + JAE/JNB — Used to jump if above/not below instruction satisfies. + JBE/JNA — Used to jump if below/equal/ not above instruction satisfies. + JC — Used to jump if carry flag CF = 1 + JE/JZ — Used to jump if equal/zero flag ZF = 1 + JG/JNLE — Used to jump if greater/not less than/equal instruction satisfies. + JGE/INL — Used to jump if greater than/equal/not less than instruction satisfies.JL/INGE — Used to jump if less than/not greater than/equal instruction satisfies. JLE/ING — Used to jump if less than/equal/if not greater than instruction satisfies. INC — Used to jump if no carry flag (CF = 0) JNE/INZ — Used to jump if not equal/zero flag ZF = 0 JNO — Used to jump if no overflow flag OF = 0 JNP/JPO — Used to jump if not parity/parity odd PF = 0 JNS — Used to jump if not sign SF = 0 JO — Used to jump if overflow flag OF = 1 JP/JPE — Used to jump if parity/parity even PF = 1 JS — Used to jump if sign flag SF = 1 Processor Control Instructions These instructions are used to control the processor action by setting/resetting the flag values. Following are the instructions under this group — STC — Used to set carry flag CF to 1 CLC — Used to clear/reset carry flag CF to 0 CMC — Used to put complement at the state of carry flag CF. STD — Used to set the direction flag DF to 1 CLD — Used to clear/reset the direction flag DF to 0 STI — Used to set the interrupt enable flag to 1, i.e., enable INTR input. CLI — Used to clear the interrupt enable flag to 0, i.e., disable INTR input. Iteration Control Instructions These instructions are used to execute the given instructions for number of times. Following is the list of instructions under this group — LOOP — Used to loop a group of instructions until the condition satisfies, i.e., CX = 0 LOOPE/LOOPZ — Used to loop a group of instructions till it satisfies ZF = 1 & CX =0 LOOPNE/LOOPNZ — Used to loop a group of instructions till it satisfies ZF = 0 &CX =0+ JCXZ — Used to jump to the provided address if CX = 0 Interrupt Instructions These instructions are used to call the interrupt during program execution. + INT - Used to interrupt the program during execution and calling service specified. + INTO — Used to interrupt the program during execution if OF =1 + IRET — Used to return from interrupt service to the main program Shift and Rotate Instructions in 8086 Microprocessor As we know that any machine (system) works on machine language, which consists of binary numbers. In the 8086 microprocessor, we have 16-bit registers to handle our data. Sometimes, the need to perform some necessary shift and rotate operations on our data may occur according to the given condition and requirement. So, for that purpose, we have various Shift and Rotate instructions present in the 8086 microprocessor. Let us discuss them one by one and understand their working: SHR : Shift Right SAR : Shift Arithmetic Right SHL : Shift Left SAL: Shift Arithmetic Left ROL : Rotate Left ROR : Rotate Right RCL : Rotate Carry Left RCR : Rotate Carry Right 1) SHR : Shift Right @ernaurRuna The SHR instruction is an abbreviation for ‘Shift Right’. This instruction simply shifts the mentioned bits in the register to the right side one by one by inserting the same number (bits that are being shifted) of zeroes from the left end. The rightmost bit that is being shifted is stored in the Carry Flag (CF). SHR Register, Bits to he shifted SHR AX, 2Working: 0 ata — a 2) SAR : Shift Arithmetic Right The SAR instruction stands for ‘Shift Arithmetic Right’. This instruction shifts the mentioned bits in the register to the right side one by one, but instead of inserting the zeroes from the left end, the MSB is restored. The rightmost bit that is being shifted is stored in the Carry Flag (CF). syntax: SAR Register, Bits to be shifted Example: SAR BX, 5 Working: i 3) SHL : Shift Left The SHL instruction is an abbreviation for ‘Shift Left’. This instruction simply shifts the mentioned bits in the register to the left side one by one by inserting the same number (bits that are being shifted) of zeroes from the right end. The leftmost bit that is being shifted is stored in the Carry Flag (CF). Syntax: SHL Register, Bits to be shifted Example: SHL AK, 2 Workingee 4) SAL : Shift Arithmetic Left The SAL instruction is an abbreviation for ‘Shift Arithmetic Left’. This instruction is the same as SHL. Syntax: Example: SAL Register, Bits to be shifted SAL CL, 2 Working ae 5) ROL: Rotate Left The ROL instruction is an abbreviation for ‘Rotate Left’. This instruction rotates the mentioned bits in the register to the left side one by one such that leftmost bit that is being rotated is again stored as the rightmost bit in the register, and it is also stored in the Carry Flag (CF). syntax: ROL Register, Bits to be shifted Example: ROL AH, 4 Working:I Drie) _| 6) ROR: Rotate Right The ROR instruction stands for ‘Rotate Right’. This instruction rotates the mentioned bits in the register to the right side one by one such that rightmost bit that is being rotated is again stored as the MSB in the register, and it is also stored in the Carry Flag (CF). syntax: ROR Register, Bits to he shifted Example: FOR AK, 4 Working: 7) RCL : Rotate Carry Left This instruction rotates the mentioned bits in the register to the left side one by one such that leftmost bit that is being rotated it is stored in the Carry Flag (CF), and the bit in the CF moved as the LSB in the register. syntax: RCL Register, Bits to be shifted Example: RCL CH, 1 Working<——| Data 8) RCR : Rotate Carry Right This instruction rotates the mentioned bits in the register to the right side such that rightmost bit that is being rotated it is stored in the Carry Flag (CF), and the bit in the CF moved as the MSB in the register. syntax: RCR Register, Bits to be shifted Example: RCR BH, 6 Working: