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Semiconductor Memory Types Explained

Semiconductor memories can be read-only or read-write. Memory chips are organized into a matrix of cells that store bits. Random-access memories (RAMs) include static RAMs (SRAMs) and dynamic RAMs (DRAMs). SRAM cells use static memory cells with access transistors, while DRAM cells use dynamic memory cells with an access transistor and storage capacitor. Address decoders are used to select word lines and bit lines in response to address inputs for reading or writing data.

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31 views29 pages

Semiconductor Memory Types Explained

Semiconductor memories can be read-only or read-write. Memory chips are organized into a matrix of cells that store bits. Random-access memories (RAMs) include static RAMs (SRAMs) and dynamic RAMs (DRAMs). SRAM cells use static memory cells with access transistors, while DRAM cells use dynamic memory cells with an access transistor and storage capacitor. Address decoders are used to select word lines and bit lines in response to address inputs for reading or writing data.

Uploaded by

amrsalah40820
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Semiconductor Memories

Read/write or read only memory


Memory-chip Organization

Memory chip consists of cells in which


the bits are stored
Cell matrix has 2M rows and 2N columns
Capacity 2M+N
Random-Access Memory (RAM)
Cells
Static RAMs (SRAMs)
Dynamic RAMs (DRAMs)
Static Memory Cell
Access transistors Q5 and Q6
read operation assume cell is storing 1
before read 𝐵 and 𝐵 precharged to VDD/2
when word line is selected current will flow from
VDD through Q4 and Q6 and onto line B, charging
the capacitance on line B, CB.
Current will flow from 𝐵 line through Q5 and Q1
to ground discharging 𝐶𝐵 .
Differential voltage 0.2V
SRAM nondistructive
Access transistors 2 to 3 times wider
than QN of inverters.
Write operation
Assume the cell is storing a 1
We wish to write a 0
Dynamic Memory Cell
An access transistor and a storage capacitor
only one bit line
a 1 the capacitor is charged to (VDD-Vt)
a 0 the capacitor is discharged to zero voltage
leakage effect: cell must be refreshed
refresh every 5 to 10 ms

Cs 30-50 fF
CB 30 to 50 times larger.
Read (bit line precharged to VDD/2)
Let VCS (VCS = VDD-Vt when a 1 is stored) and 0 when a zero is
stored
Using charge conservation

Since CB >> CS
If the cell is storing a 1, VCS = VDD – Vt and

If the cell is storing a 0, VCS = 0 and


Sense Amplifiers and Address
Decoders
The sense amplifier
Differential operation in Dynamic
RAMs
Row-Address Decoder

The row address decoder is required


to select on of the 2M word lines in
response to an M-bit address input
Ex. M=3, three address bits A0,A1,
and A2, eight word lines W0,
W1,….,W7

𝑊0 =𝐴0 𝐴1 𝐴2 = 𝐴0 + 𝐴1 + 𝐴2
W3 = A0A1𝐴2 = 𝐴0 + 𝐴1 + 𝐴2
Column-Address Decoder
NOR decoder and a pass-transistor
multiplexer
A tree column decoder
A0=1,A1= 0, and A2=1
READ-ONLY MEMORY (ROM)

32-bit (8-wordx4-bit)
Pseudo-NMOS logic
An NMOS transistor exists in a particular cell if the cell
is storing a 0; a cell storing a 1 has no MOSFET.

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