Scribd
Upload
13 views15 pages

Lecture 8

This document describes the operation of a CMOS monostable circuit. It consists of two NOR gates (G1 and G2) connected with a capacitor and resistor. When a trigger pulse is applied, the output of G1 goes low, charging the capacitor. This causes the output of G2 to go high, keeping the circuit in a quasi-stable state until the capacitor discharges through the resistor, returning the circuit to its original state. The time it takes the capacitor to discharge determines the pulse interval of the circuit.

Uploaded by

amrsalah40820
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
13 views15 pages

Lecture 8

This document describes the operation of a CMOS monostable circuit. It consists of two NOR gates (G1 and G2) connected with a capacitor and resistor. When a trigger pulse is applied, the output of G1 goes low, charging the capacitor. This causes the output of G2 to go high, keeping the circuit in a quasi-stable state until the capacitor discharges through the resistor, returning the circuit to its original state. The time it takes the capacitor to discharge determines the pulse interval of the circuit.

Uploaded by

amrsalah40820
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 15

CMOS Monostable Circuit

Two two-input CMOS NOR gates, G1 and G2, a capacitor C


and a resistor R. The input source vI supplies the triggering
pulses.
The diodes are to prevent the input voltage signal from rising
above the supply voltage VDD (by more than one diode drop) and
from falling below ground voltage(by more than one diode drop).
Approximate equivalent output circuit of the gate
when the gate output is low its o/p charact. Ron to ground
a few hundred ohms (sinking current)
When the gate output is high , current can flow
from VDD through the output terminal of the gate
into the external circuit (sourcing current)
Stable state before trigger pulse is applied
o/p G1 is high at VDD, the capacitor is discharged, and the i/p
to G2 is high at VDD.
o/p of G2 is low, fed back to G1, since vI low, o/p G1 high

Trigger pulse is applied. o/p of G1 will go low. G1 will be


sinking some current (Ron) its output will not go all the
way to 0 V. The output of G1 drops by a value ∆V1.
Back
The drop ∆V1 is coupled through C (short circuit at transient)
to i/p of G2. An instantaneous current that flows from VDD
through R and C and into the o/p terminal of G1 to ground.

We have a voltage divider formed by R and Ron


(instantaneous voltage across C is 0)

Back
The drop of voltage at input of G2 causes its output to go
high. The o/p of G1 low even after the triggering pulse has
disappeared. The circuit is in the quasi-stable state.

The current through R, C, and Ron causes C to charge,


and the voltage vI2 rises exponentially toward VDD
with a time constant C(R+Ron).
The vI2 will continue to rise untill Vth of inverter G2.
G2 will switch , o/p vo2 will go to 0 V, will cause G1 to
switch. o/p of G1 will attempt to rise to VDD, rise will
be limited to ∆V2.

Back
The rise in vo1 is coupled through C to i/p of G2.Because of D1,
between i/p of G1 and VDD, vI2 can rise only to VDD+VD1(0.7V)

vI2 is higher than VDD (by VD1) current will flow


from the output of G1 through C and then
through R//D1. C discharges until vI2 drops to
VDD and vo1 rises to VDD.

Back
The monostable circuit should not be triggered until the
capacitor has been discharged. The capacitor discharge
interval is known as the recovery time.
The pulse interval T can be derived, expressing vI2(t) as

Where τ1 = C(R + Ron).


Substituting for t = T and vI2 = Vth and
for ∆V1
And after some manipulation:
An Astable Circuit
The Ring Oscillator

You might also like