Chapter 1

Introduction to CMOS
VLSI Design
Course Topics

• Introduction to CMOS circuits

Chapter 1: introduction to VLSI design

• MOS transistor theory, processing technology

• CMOS circuit and logic design

• System design methods

• CAD algorithms for backend

design
Course materials
• Textbook
• Weste and Harris. CMOS VLSI Design
(4rd edition)

Chapter 1: introduction to VLSI design

• D. Hodges, H. G. Jackson, R.A. Saleh, Analysis and design of Digital
integrated circuits

Chapter 1: introduction to VLSI design

Introduction
• Integrated circuits: many transistors on one chip.
• Very Large Scale Integration (VLSI): very many
• Complementary Metal Oxide Semiconductor
• Fast, cheap, low power transistors
• Introduction: How to build your own simple CMOS
chip
• CMOS transistors
• Building logic gates from transistors

Chapter 1: introduction to VLSI design

• Transistor layout and fabrication
• Rest of the course: How to build a good CMOS chip

Chapter 1: introduction to VLSI design

A Brief History
• 1958: First integrated circuit
• Flip-flop using two transistors
• Built by Jack Kilby at Texas Instruments
• 2003
• Intel Pentium 4 mprocessor (55 million transistors)
• 512 Mbit DRAM (> 0.5 billion transistors)
• 53% compound annual growth rate over 45
years • No other technology has grown so fast so
long
• Driven by miniaturization of transistors
 • Smaller is cheaper, faster, lower in power!
• Revolutionary effects on society
Chapter 1: introduction to VLSI design

Annual Sales
• 1018 transistors manufactured in 2003
• 100 million for every human on the planet

Chapter 1: introduction to VLSI design

 ( Semiconductor Billings
Global
200

Billions of US$
150

100
)

50

0
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

Invention of the Transistor

• Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable
• 1947: first point contact transistor
Chapter 1: introduction to VLSI design
• John Bardeen and Walter
Brattain at Bell Labs
• Read Crystal Fire by
Riordan, Hoddeson

Transistor Types
• Bipolar transistors
• npn or pnp silicon structure
• Small current into very thin base layer controls large
currents between emitter and collector
• Base currents limit integration density
• Metal Oxide Semiconductor Field Effect
Transistors
Chapter 1: introduction to VLSI design
 • nMOS and pMOS MOSFETS
• Voltage applied to insulated gate controls current
between source and drain
• Low power allows very high integration
MOS Integrated Circuits
• 1970’s processes usually had only nMOS transistors

Chapter 1: introduction to VLSI design

• Inexpensive, but consume power while idle

Intel 1101 256-bit SRAM Intel 4004 4-bit mProc

• 1980s-present: CMOS processes for low idle power

Chapter 1: introduction to VLSI design

 Moore’s Law
• 1965: Gordon Moore plotted transistor on
each chip
• Fit straight line on semilog scale
• Transistor counts have doubled every 26 months
1,000,000,000

100,000,000
Pentium 4
Pentium III
Integration Levels
10,000,000 Pentium II
Pentium Pro
Transistors
1,000,000
Intel486
Pentium SSI: 10 gates
Intel386
100,000
80286
MSI: 1000 gates
8086
10,000
8008
8080
LSI: 10,000 gates
4004
1,000
VLSI: > 10k gates
1970 1975 1980 1985 1990 1995 2000

Year

Chapter 1: introduction to VLSI design

Chapter 1: introduction to VLSI design
Chapter 1: introduction to VLSI design
Chapter 1: introduction to VLSI design
Corollaries
• Many other factors grow exponentially
• Ex: clock frequency, processor performance
10,000

1,000 4004

8008

8080
Clock Speed (MHz)
100 8086

80286

Intel386

10 Intel486

Pentium

Pentium Pro/II/III

1 Pentium 4

1970 1975 1980 1985 1990 1995 2000 2005

Year
 Chapter 1: introduction to VLSI design

Silicon Lattice
• Transistors are built on a silicon substrate
• Silicon is a Group IV material
• Forms crystal lattice with bonds to four neighbors

Chapter 1: introduction to VLSI design

 Si Si Si

Si Si Si

Si Si Si

Dopants
• Silicon is a semiconductor
• Pure silicon has no free carriers and conducts poorly
• Adding dopants increases the conductivity
Chapter 1: introduction to VLSI design
• Group V: extra electron (n-type)
• Group III: missing electron, called hole (p-type)
Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

p-n Junctions
• A junction between p-type and n-type
semiconductor forms a diode.
• Current flows only in one direction
Chapter 1: introduction to VLSI design
 p-type n-type
anode cathode

nMOS Transistor
• Four terminals: gate, source, drain, body
• Gate – oxide – body stack looks like a capacitor
• Gate and body are conductors
• SiO2 (oxide) is a very good insulator
• Called metal – oxide – semiconductor (MOS) capacitor
Source Gate Drain

Chapter 1: introduction to VLSI design

 • Even though gate is
SiO
no longer
Polysilicon

made of metal 2
n+ n+

nMOS Operation p bulk Si

• Body is commonly tied to ground (0 V)

• When the gate is at a low voltage:
• P-type body is at low voltage
• Source-body and drain-body diodes are OFF
• No current flows, transistor is OFF

Chapter 1: introduction to VLSI design

 Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

nMOS Operation Cont.

• When the gate is at a high voltage:
• Positive charge on gate of MOS capacitor
• Negative charge attracted to body
• Inverts a channel under gate to n-type

Chapter 1: introduction to VLSI design

 • Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

pMOS Transistor
• Similar, but doping and voltages reversed
• Body tied to high voltage (VDD)
• Gate low: transistor ON
• Gate high: transistor OFF
Chapter 1: introduction to VLSI design
• Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

Chapter 1: introduction to VLSI design

Power Supply Voltage
• GND = 0 V
• In 1980’s, VDD = 5V
• VDD has decreased in modern processes
• High VDD would damage modern tiny transistors
• Lower VDD saves power
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
CMOS Inverter
Chapter 1: introduction to VLSI design

Transistors as Switches
• We can view MOS transistors as electrically
controlled switches
• Voltage at gate controls path from source to
draing = 0 g = 1
d d d

nMOS g OFF ON s ss

d d d

Chapter 1: introduction to VLSI design

 pMOS g ON OFF sss
A Y
VDD
0
1

AY

AY
GND

Chapter 1: introduction to VLSI design

CMOS Inverter
A Y
0
1 0

Chapter 1: introduction to VLSI design

CMOS NAND Gate
VDD

OFF

Chapter 1: introduction to VLSI design

CMOS Inverter
ON
A=0Y=1

OFF
AY
GND

Chapter 1: introduction to VLSI design

CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1

Chapter 1: introduction to VLSI design

CMOS Inverter

Y
A
B

Chapter 1: introduction to VLSI design

CMOS NAND Gate
A B Y ON ON
0 0 1 Y=1
0 1 A=0
OFF
1 0
B=0
1 1 OFF

Chapter 1: introduction to VLSI design

CMOS NAND Gate
A B Y OFF ON
0 0 1 Y=1
0 1 1 A=0
OFF
1 0
B=1
1 1 ON

Chapter 1: introduction to VLSI design

CMOS NAND Gate
A B Y ON OFF
0 0 1 Y=1
0 1 1 A=1
ON
1 0 1
B=0
1 1 OFF

Chapter 1: introduction to VLSI design

CMOS NAND Gate
A B Y OFF OFF
0 0 1 Y=0
0 1 1 A=1
ON
1 0 1
B=1
1 1 0 ON

Chapter 1: introduction to VLSI design

CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0
B
1 1 0
Y

Chapter 1: introduction to VLSI design

3-input NAND Gate
• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0

Y
A
B
C

Chapter 1: introduction to VLSI design

Compound Gates
• Compound gates can do any inverting function
• Ex:
Y AB C D 
(AND-AND-OR-INVERT, AOI22)
C A AC
D B BD
(a) (b)
C
D A
A BC
(d) D
(c)
C D B
A B
B
A C
D
B D

Y CY

Chapter 1: introduction to VLSI design

 (f)

(e)

Example: O3AI
Y A B C D   
•
A
B
C D
Y
D
A B C

Chapter 1: introduction to VLSI design

Pass transistors and transmission gate
• An nMOS transistor is an almost perfect switch when
passing a 0 and thus we say it passes a strong 0. However,
the nMOS transistor is imperfect at passing a 1. We say it
passes a degraded or weak 1
• A pMOS transistor again has the opposite behavior, passing
strong 1s but degraded 0s
• When an nMOS or pMOS is used alone as an imperfect
switch, we sometimes call it a pass transistor

Chapter 1: introduction to VLSI design

Pass transistors and transmission
gate

Chapter 1: introduction to VLSI design

 Chapter 1: introduction to VLSI design

Pass transistors and transmission

gate
CMOS Fabrication
• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• On each step, different materials are deposited or
etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

Chapter 1: introduction to VLSI design

 Chapter 1: introduction to VLSI design

Inverter Cross-section
• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

 Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
connection (used for Schottky Diode)
GND
taps Y
VDD

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

• Use heavily doped well and substrate contacts / A

Chapter 1: introduction to VLSI design
 Chapter 1: introduction to VLSI design

Inverter Mask Set

• Transistors and wires are defined by masks
• Cross-section taken along dashed line
Chapter 1: introduction to VLSI design
Chapter 1: introduction to VLSI design
Detailed Mask Views
• Six masks
• n-well
• Polysilicon
• n+ diffusion
• p+ diffusion
• Contact
• Metal
Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide) • Remove
layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer • Strip off
SiO2

p substrate

Chapter 1: introduction to VLSI design

Chapter 1: introduction to VLSI design
Oxidation
• Grow SiO2 on top of Si wafer
• The wafer is first oxidized in a high-temperature (typically
900–1200 °C) furnace that causes Si and O2 to react and
become SiO2 on the wafer surface

SiO2

p substrate
Photoresist
• Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

Photoresist

SiO2

p substrate

Chapter 1: introduction to VLSI design

Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist

Photoresist

Chapter 1: introduction to VLSI design

 SiO2

p substrate
Etch
• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed

Photoresist

Chapter 1: introduction to VLSI design

 SiO2

p substrate
Strip
Photoresist
• Strip off remaining photoresist
• Use mixture of acids called piranha etch
• Necessary so resist doesn’t melt in next step

Chapter 1: introduction to VLSI design

 SiO2

p substrate

Chapter 1: introduction to VLSI design

n-well
• n-well is formed with diffusion or ion
implantation
• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si
 n well

SiO2

Chapter 1: introduction to VLSI design

Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

Chapter 1: introduction to VLSI design

 n well
p substrate

Polysilicon
• Deposit very thin layer of gate oxide
• < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon
layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor
 Polysilicon
Thin gate oxide

n well
p substrate

Chapter 1: introduction to VLSI design

Chapter 1: introduction to VLSI design

Polysilicon Patterning
• Use same lithography process to pattern polysilicon

p substrate

Chapter 1: introduction to VLSI design

N-diffusion (cont.)

Polysilicon

Polysilicon

n well

Thi
n gate oxide

p substrate

Chapter 1: introduction to VLSI design

N-diffusion
• Use oxide and masking to expose where n+ dopants
should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well
contact

p substrate

Chapter 1: introduction to VLSI design

N-diffusion (cont.)

n well

• Pattern oxide and form n+ regions

n+ Diffusion

p substrate

Chapter 1: introduction to VLSI design

 n well

p substrate

Chapter 1: introduction to VLSI design

N-diffusion (cont.)
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well

• Strip off oxide to complete patterning step

p substrate

Chapter 1: introduction to VLSI design

 n+ n+ n+

n well

P-Diffusion
• Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p substrate
N-diffusion (cont.)
p+ n+ n+ p+ p+ n+

n well

Chapter 1: introduction to VLSI design

p substrate

Chapter 1: introduction to VLSI design

Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

p+ n+ n+ p+ p+ n+

n well

Thick field oxide

p substrate

Chapter 1: introduction to VLSI design

Metalization
• Sputter on copper / aluminum over whole wafer

Chapter 1: introduction to VLSI design

Chapter 1: introduction to VLSI design

Layout Design Rules
• Mead and Conway [Mead80] popularized scalable
design rules based on a single parameter, λ, that
characterizes the resolution of the process. λ is
generally half of the minimum drawn transistor
channel length. This length is the distance between
the source and drain of a transistor and is set by
the minimum width of a polysilicon wire. For
example, a 180 nm process has a minimum
polysilicon width (and hence transistor length) of
0.18 um and uses design rules with
Layout
• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
• Feature size f = distance between source and drain
• Set by minimum width of polysilicon
• Feature size scales ~X0.7 every 2 years both lateral and
vertical
• Moore’s law
• Normalize feature size when describing design rules
• Express rules in terms of l = f/2

Chapter 1: introduction to VLSI design

• E.g. l = 0.3 mm in 0.6 mm process
• Today’s l = 0.01 mm (10 nanometer = 10-8 meter)
Simplified Design Rules
• A conservative but easy-to-use set of design rules
for layouts with two metal layers in an n-well
process is as follows:
Metal and diffusion have minimum width and spacing of
4 λ.
Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on
the layers above and below.
Polysilicon uses a width of 2 λ.

Chapter 1: introduction to VLSI design

Simplified Design Rules
• Conservative rules to get you started

Chapter 1: introduction to VLSI design

Inverter Layout
• Transistor dimensions specified as Width /
Length
• Minimum size is 4l / 2l, sometimes called 1 unit

Chapter 1: introduction to VLSI design

long

• In f = 0.01
mm process, this is 0.04 mm wide, 0.02 mm

Chapter 1: introduction to VLSI design