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Assignment 04 Solution

This document contains an assignment for a digital systems course with multiple exercises: 1) The first exercise asks students to sketch the output of an SR latch given input signals. 2) The second exercise provides a sequential circuit and asks students to provide a truth table and describe what the circuit does. 3) The third exercise introduces a ring oscillator circuit and asks students to describe the nature of its output wave, calculate the output frequency, and consider how frequency would change if feedback delay was increased. 4) The remaining exercises ask students to construct various flip-flop circuits and analyze timing parameters of a given sequential circuit.

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40 views3 pages

Assignment 04 Solution

This document contains an assignment for a digital systems course with multiple exercises: 1) The first exercise asks students to sketch the output of an SR latch given input signals. 2) The second exercise provides a sequential circuit and asks students to provide a truth table and describe what the circuit does. 3) The third exercise introduces a ring oscillator circuit and asks students to describe the nature of its output wave, calculate the output frequency, and consider how frequency would change if feedback delay was increased. 4) The remaining exercises ask students to construct various flip-flop circuits and analyze timing parameters of a given sequential circuit.

Uploaded by

maroua.sayah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

The National Higher School of Artificial Intelligence 2023/2024

Digital Systems First Year


Solution

Assignment 04

Exercise 01
Given the input signals shown below, sketch the output, Q, of an SR latch.

Exercise 02
Examine the sequential circuit below. First, give a complete truth table, then describe conceptually what
the circuit does.

This is an RS latch, but instead of instability when both inputs are 1, this latch sets.

Exercise 03
The following circuit is called a ring oscillator. It generates a periodic wave output and can be used as a
clock generator.

OUTPUT

a) What is the nature of the periodic wave

The nature of the wave is square wave

b) If the delay of each inverter is 1/3 nanosecond, what will the output frequency be?

The output is inverted every 1 nanosecond. The circuit will produce a periodic square-wave of 2
nanosecond period or 500 MHz frequency

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The National Higher School of Artificial Intelligence 2023/2024
Digital Systems First Year
Solution

c) Can the frequency be reduced to half if the feedback delay is increased by doubling the number of
inverters.

For oscillation the total number of inversions must be odd. Thus, six inverters will not produce an
alternating output.

Exercise 04
Construct a D flip-flop using a JK Flip-flop.

Exercise 05
Construct a JK flip-flop using a D Flip-flop, a 2-to-1 line multiplexer and an inverter.

Exercice 06
Consider the following circuit:

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The National Higher School of Artificial Intelligence 2023/2024
Digital Systems First Year
Solution

You are given the following timing parameters: Register Clk-To-Q: 2ps, Register Setup: 2ps, NOT
Gate: 1ps, AND Gate: 4ps, OR Gate: 3ps, NAND Gate: 4ps. Assume the 2 inputs comes from
registers and the output is connected to a register as well.

What is the minimum clock period at which this circuit can be run?

Solution: 12 ps

We can break this circuit into 3 paths between registers. The minimum clock period will be the
maximum path delay, which is calculated by Clk-To-Q + Combinational Logic Delay + setup Time.
Path 1: Clk-To-Q + NOT + AND + NOT + Setup = 2ps + 1ps + 4ps + 1ps + 2ps = 10ps
Path 2: Clk-To-Q + OR + Setup = 2ps + 3ps + 2ps = 7ps
Path 3: Clk-to-Q + NAND + AND + Setup = 2ps + 4ps + 4ps + 2ps = 12ps
So, the critical path is path 3, and the max delay is 12ps.

What is the maximum hold time that would allow for this circuit to run correctly?

Solution: 5 ps

We find the max hold time by now looking at the shortest path, which is path 2.
We need to ensure that Hold Time ≤ Clk-To-Q + Combinational Logic delay.
Path 2: Clk-to-Q + OR = 2ps + 3ps = 5ps. So, our hold time can be no more than 5ps, or there will be
a hold time violation in path 2.

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