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4 Bit Shift Register

The document describes different types of shift registers that can be created using flip-flops including Serial In Serial Out (SISO), Parallel In Serial Out (PISO), Serial In Parallel Out (SIPO), and Parallel In Parallel Out (PIPO). It discusses how each type works, their advantages and disadvantages, and provides examples. The aim was to design a 4-bit shift register and analyze its operation in different configurations.

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balaram ji
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384 views11 pages

4 Bit Shift Register

The document describes different types of shift registers that can be created using flip-flops including Serial In Serial Out (SISO), Parallel In Serial Out (PISO), Serial In Parallel Out (SIPO), and Parallel In Parallel Out (PIPO). It discusses how each type works, their advantages and disadvantages, and provides examples. The aim was to design a 4-bit shift register and analyze its operation in different configurations.

Uploaded by

balaram ji
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Date

Expt. No.
Page No.
Experimet-12

Aim lo
lo make -bit shil Jregiato
PISO and PT so)uRing DGendJk
SOSI PO,
Jkflup-flop.
Simulatas
8 Logicihcui Sim 4&ed

heoy>
Skt Reniaden A
hegister ian aba
iplopR oith bast fumctiroe
DataStoAago
Data mo temeit

Shi hegisura Consist o a asmemen a lip-flopa.


Each ip-lopinashit kegizter hephesente ona bil
Capa çityIheRtokoge Capacaly
is Pho total numberohita tot a egintea
Can Hoe 1

he shiting CApacity penmitz ha motemet o dota


Leithin egister DA
hit nto a
t o the kegisBex
uponapplicakion pulse

DEent peok Regiter


SISO STPO PISO PIPO

Teacher's Signature
cepts data seiall
Serial in Serial Out (SISo) ine
One bt at a me on
a ngbe and
ppenducirg
also in
he an ts aupt oudtput a
&4ohed n Omodtion

Serialfom.
dotain E Docda out

Examle Data lo|o Entereo


into dhe sqisko,
Tllugthade enthy
the y bite
Tlusthate aially shißting h bte out bhe
cegister ecleahirg he hegiates
Tuth Ta ble o1)

elkKi

2
1
O
imingDagTam

CIk

Drta

Disadvanta23
nclock_pulses are Tequrecd to enter n-bt 'dota.
clata,_
clock pulses are seguired to re ad 'n-bit
is read it will be lost.
Once Hhe data
SIsO

200

-
Date

Expt. No. Page No.

Strial tn fal PabaWel od (STPo) >


Dota bitz ake emtehed Reiall and outpad ia got
Pakaely
Once h data ak 2iahded the putpud ach ztag
auailakle sudaud n e

Dada i-
Daasutput
In SISO olock pulse
data
eqiseeddo
doeadheadth
Ond Once dhe
the data a ead iwil be lortbut
in SIpo
lock Pulaa s) ixnot kequihed to 2oad
dada ond h a data is kequiked adlen hahead
Opeh autton
SIPO

-
Parallel In ehi OutP
he dab
Fo a paralel in Reial out sAa intoegister
th ei
bit e entered Simu taequ ily
bita ake
data
Aespertive
ines but the
atages Tn Poualle

l t o the
egater 2elally.
han eh ted
hale se a Conthal
Tn hi keg ter te

that colled h oad


the data must emt er ahil t
fo chiha
dabe a a o aigmal inpu anfo ottisn
het nieved 4he dada we mu puct hiph ahitload
Pata in

L data aut
PIPO

-
(Prfp)>
Panellei faralleJ Ot
aimultan eousl
nto thei
thei
tmtehed
The bit ake
hespective stage
appear
the paralle
Tmmeciotely th bih
eutpats.
athen because t x fa
sebetler than
easier to desig
patay

Dala put

Po

Le
clK
PISO

5120

676
Results
In us way we can malce diferent
of shft
type YCgiskr ing a
Hp-flop and
also analyse it gnd get PIPo s qcttey
shitt Yegister out of t
Hence we esign 4 b t shitt
rei shre
sEso, PIso SLPO PIPO) success hully.

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