The first 91 Chapter STM32H7 Of FDCAN Bus basics and HAL library API

This chapter will explain FDCAN Basic knowledge and corresponding HAL library API.CAN FD Medium FD
Meaning is flexible data, Flexible data communication , And the baud rate can be different from the baud rate
in the arbitration stage

Catalog
91.1 Important tips for beginners
91.2 FDCAN Basic knowledge of
91.2.1 CAN FD Protocol is introduced
91.2.2 CAN FD characteristic
91.2.3 CAN FD Format
91.2.4 CAN FD comparison CAN2.0 The promotion of
91.3 FDCAN Bus HAL Library usage
91.3.1 FDCAN Bus architecture FDCAN_GlobalTypeDef
91.3.2 FDCAN Bus time trigger structure TTCAN_TypeDef
91.3.3 FDCAN Bus initialization structure FDCAN_InitTypeDef

91.3.4 FDCAN Bus message RAM Address FDCAN_MsgRamAddressTypeDef

91.3.5 FDCAN Bus filter structure FDCAN_FilterTypeDef
91.3.6 FDCAN Bus message sending structure FDCAN_TxHeaderTypeDef
91.3.7 FDCAN Bus message receiving structure FDCAN_RxHeaderTypeDef
91.3.8 FDCAN Bus handle structure FDCAN_HandleTypeDef
91.4 FD CAN Bus source file stm32h7xx_hal_fdcan.c
91.4.1 function HAL_FDCAN_Init
91.4.2 function HAL_FDCAN_DeInit
91.4.3 function HAL_FDCAN_ConfigFilter
91.4.4 function HAL_FDCAN_ConfigFifoWatermark
91.4.5 function HAL_FDCAN_ActivateNotification
91.4.6 function HAL_FDCAN_Start
91.4.7 function HAL_FDCAN_AddMessageToTxFifoQ
91.4.8 function HAL_FDCAN_GetRxMessage
91.5 summary

91.1 Important tips for beginners

1. FDCAN The basic knowledge points can be seen in Chapter 90 Chapter , It has been described in detail
2. Especially recommend renessa's CAN Introduction Chinese and English manual , Very well done ： Address
Links
91.2 FDCAN Basic knowledge of

FDCAN The basics are in the... Of this tutorial 90 Chapter gives a very detailed description . Here we will explain
several knowledge points used in this chapter , For details, please refer to section 90 Chapter .

91.2.1 CAN FD Protocol is introduced

STM32H7 Of CAN FD accord with ISO 11898-12015 standard .STM32 On the device FDCAN The functions of are
as follows ：

（1） accord with CAN agreement 2.0 edition A,B and ISO 11898-1：2015,-4.

（2） addressable 10 KB RAM Memory , Up to 2560 A word .

（3） Improved reception filtering .

（4） Two configurable receivers FIFO.

（5） As many as 64 A dedicated receive buffer .

（6） Separate signaling when receiving high priority messages .

（7） As many as 32 A dedicated send buffer .

（8） Configurable sending FIFO And send queue .

（9） Configurable send events FIFO.

（10） Clock calibration unit .

（11） Transceiver delay compensation .

The following figure illustrates FDCAN block diagram .

From this diagram, you can learn the following information ：

（1）CANFD1 and CANFD2 Share one RAM Space .

（2） Every CANFD They all have their own kernels .

（3）CAN The kernel implements protocol control and transmit / receive shift register .

（4）Tx handler Control messages from CAN news RAM To CAN kernel .

（5）Rx handler control CAN Kernel to CAN news RAM.

91.2.2 CAN FD characteristic

（1） Compatible with classic CAN, Can follow ISO 11898-1 Send and receive data .

（2） Enhance error detection , Support as much as CRC 21 Bit checksums .

（3） Message priority .

（4） Guaranteed delay time .

（5） Configuration flexibility .

（6） Multicast reception with time synchronization .

（7） System wide data consistency , At most per message 64 Bytes .

（8） Multiple hosts .

（9） Error detection and signals .

（10） Distinguish between temporary and permanent failures of nodes and automatically close defective
nodes .

91.2.3 CAN FD Format

The first arbitration stage （The first arbitration phase） It's a message , It includes ：

（1） Frame start （SOF）.

（2）ID Number and other places , Indicates the purpose of the message （ Provide or request data ）, And
speed and format configuration （CAN or CAN-FD）.

Data transmission phase （The data transmission phase） Include ：

（1） Data length code （DLC）, Indicates how many data bytes the message contains .

（2） Data users want to send .

（3） Check the cyclic redundancy sequence （CRC）.

（4） Dominant position .

The second arbitration stage （The second arbitration phase） contain ：

（1） Acknowledgement sent by other nodes on the bus （ACK） 's receiver （ If at least one receiver
successfully receives the message ）

（2） Frame tail （EOF）, stay IFS No messages are transmitted during this period ： The goal is to separate the
current frame from the next .

Be careful ： about 29bit Identifier frame , When adding 18bit Mark to the second 1 It's an arbitration stage IDE
bit And then with the standard CAN FD It's similar .

91.2.4 CAN FD comparison CAN2.0 The promotion of

CAN-FD It can meet the need of communication network with higher bandwidth . Each frame has at most 64
Bytes of CAN-FD And to maximize the bit rate , Make the data phase faster 8 times , In the second arbitration
stage, it is necessary to return to the normal bit rate . Ensure the integrity of data transmission by ：

（1）17 The polynomial of order 1 is the largest 16 The payload of bytes carries CRC.

（2）21 A polynomial of order two 16 To 64 Check the payload between bytes .

Standard frame and CAN FD The difference between ：

After the identifier ,CAN 2.0 and CAN-FD It has different functions ：

（1）CAN 2.0 send out RTR Bit to accurately determine the frame type ： Data frame （RTR Mainly ） Or
remote frame （RTR） It's implicit ）.

（2） because CAN-FD Only data frames are supported , So always send the dominant RRS（ Retain ）.
IDE Bits remain in the same position , And use the same action to distinguish the basic format （11 Bit identifier
）. Please note that , In the case of extended formats ,IDE Bits are transmitted either explicitly or implicitly （29
Bit identifier ）.

And CAN 2.0 comparison , stay CAN-FD In the frame , Three new bits are added to the control field ：

（1） Extended data length （EDL） position ： The hidden frame is CAN-FD, Otherwise, it is dominant （ be
called R0） stay CAN 2.0 In the frame .

（2） Bit rate switching （BRS）： Indicates whether two bit rates are enabled （ for example , When the data
phase bits are transmitted to the arbitration phase at different bit rates ）.

（3） Error status indicator （ESI）： Indicates whether the node is in error active mode or error passive mode .

The last part of the control field is the data length code （DLC）, It has the same position and the same length
（4 position ）, be used for CAN 2.0 and CAN-FD. DLC Function in CAN-FD and CAN 2.0 In the same way , but
CAN-FD There is a small change （ The details in the table below ）. CAN-FD Extended frames allow sending in
a single message 64 Data bytes , and CAN 2.0 Payload data can be sent up to 8 Bytes .

Improve network bandwidth by adding data fields of payload data , Because it requires less packet processing .
meanwhile , By providing CRC Add more bits to enhance message integrity ：

（1） If the payload data is at most 16 Bytes , be CRC With 17 Bit code .

（2） If the payload data is greater than 20（16） Bytes , be CRC With 21 Bit code .

in addition , To make sure CAN-FD The robustness of the frame , The padding mechanism supports CRC Field .
The following table summarizes CAN-FD and CAN 2.0 The main difference between . The main functions
provided are as follows CAN 2.0 comparison ,CAN FD The improvement of is that the increase of data payload
and speed is caused by CAN-FD Available in BRS,EDL and ESI To make sure that .
91.3 FDCAN Bus HAL Library usage
91.3.1 FDCAN Bus architecture FDCAN_GlobalTypeDef

FD CAN The bus related registers are passed through HAL The structure in the library FDCAN_GlobalTypeDef
Definition , stay stm32h743xx.h This type definition can be found in ：

typedef struct
{
__IO uint32_t CREL;
__IO uint32_t ENDN;
__IO uint32_t RESERVED1;
__IO uint32_t DBTP;
__IO uint32_t TEST;
__IO uint32_t RWD;
__IO uint32_t CCCR;
__IO uint32_t NBTP;
__IO uint32_t TSCC;
__IO uint32_t TSCV;
__IO uint32_t TOCC;
__IO uint32_t TOCV;
__IO uint32_t RESERVED2[4];
__IO uint32_t ECR;
__IO uint32_t PSR;
__IO uint32_t TDCR;
__IO uint32_t RESERVED3;
__IO uint32_t IR;
__IO uint32_t IE;
__IO uint32_t ILS;
__IO uint32_t ILE;
__IO uint32_t RESERVED4[8];
__IO uint32_t GFC;
__IO uint32_t SIDFC;
__IO uint32_t XIDFC;
__IO uint32_t RESERVED5;
__IO uint32_t XIDAM;
__IO uint32_t HPMS;
__IO uint32_t NDAT1;
__IO uint32_t NDAT2;
__IO uint32_t RXF0C;
__IO uint32_t RXF0S;
__IO uint32_t RXF0A;
__IO uint32_t RXBC;
__IO uint32_t RXF1C;
 __IO uint32_t RXF1S;
__IO uint32_t RXF1A;
__IO uint32_t RXESC;
__IO uint32_t TXBC;
__IO uint32_t TXFQS;
__IO uint32_t TXESC;
__IO uint32_t TXBRP;
__IO uint32_t TXBAR;
__IO uint32_t TXBCR;
__IO uint32_t TXBTO;
__IO uint32_t TXBCF;
__IO uint32_t TXBTIE;
__IO uint32_t TXBCIE;
__IO uint32_t RESERVED6[2];
__IO uint32_t TXEFC;
__IO uint32_t TXEFS;
__IO uint32_t TXEFA;
__IO uint32_t RESERVED7;
} FDCAN_GlobalTypeDef;

The name and order of the members of this structure and CPU The register of is one A corresponding .

__IO Express volatile, This is the standard C A modifier in language , Indicates that the variable is nonvolatile ,
The compiler should not optimize it .core_m7.h The file defines the macro ：

#define __O volatile /*!< Defines 'write only' permissions */

#define __IO volatile /*!< Defines 'read / write' permissions */

So let's see FDCAN The definition of , stay stm32h743xx.h file .

#define PERIPH_BASE (0x40000000UL)

#define D2_APB1PERIPH_BASE PERIPH_BASE

#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)

#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)

#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) <----- Expand the macro ,

(FDCAN_GlobalTypeDef *)0x4000A000
#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

We visit FDCAN1 Of CCCR Registers can take this form ：FDCAN1->CCCR = 0.

91.3.2 FDCAN Bus time trigger structure TTCAN_TypeDef

FDCAN The registers related to bus time trigger are through HAL The structure in the library TTCAN_TypeDef
Definition , stay stm32h743xx.h This type definition can be found in ：
typedef struct
{
__IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address
offset: 0x100 */
__IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address
offset: 0x104 */
__IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address
offset: 0x108 */
__IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address
offset: 0x10C */
__IO uint32_t TURCF; /*!< TUR Configuration register, Address
offset: 0x110 */
__IO uint32_t TTOCN; /*!< TT Operation Control register, Address
offset: 0x114 */
__IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address
offset: 0x118 */
__IO uint32_t TTTMK; /*!< TT Time Mark register, Address
offset: 0x11C */
__IO uint32_t TTIR; /*!< TT Interrupt register, Address
offset: 0x120 */
__IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address
offset: 0x124 */
__IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address
offset: 0x128 */
__IO uint32_t TTOST; /*!< TT Operation Status register, Address
offset: 0x12C */
__IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address
offset: 0x130 */
__IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address
offset: 0x134 */
__IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address
offset: 0x138 */
__IO uint32_t TTCPT; /*!< TT Capture Time register, Address
offset: 0x13C */
__IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address
offset: 0x140 */
__IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144
- 0x2FC */
__IO uint32_t TTTS; /*!< TT Trigger Select register, Address
offset: 0x300 */
} TTCAN_TypeDef;
91.3.3 FDCAN Bus initialization structure FDCAN_InitTypeDef

Here is FDCAN The initialization structure of the bus ：

typedef struct
{
uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
This parameter can be a value of @ref
FDCAN_frame_format */

uint32_t Mode; /*!< Specifies the FDCAN mode.

This parameter can be a value of @ref
FDCAN_operating_mode */

FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission

mode.
This parameter can be set to ENABLE or
DISABLE */

FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature.

This parameter can be set to ENABLE or
DISABLE */

FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception

Handling.
This parameter can be set to ENABLE or
DISABLE */

uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator

frequency is
divided for generating the nominal bit
time quanta.
This parameter must be a number between 1
and 512 */

uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the
FDCAN
hardware is allowed to lengthen or
shorten a bit to perform
resynchronization.
This parameter must be a number between 1
and 128 */

uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment
1.
This parameter must be a number between 2
and 256 */
 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment
2.
This parameter must be a number between 2
and 128 */

uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator

frequency is
divided for generating the data bit time
quanta.
This parameter must be a number between 1
and 32 */

uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the
FDCAN
hardware is allowed to lengthen or
shorten a data bit to
perform resynchronization.
This parameter must be a number between 1
and 16 */

uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit
Segment 1.
This parameter must be a number between 1
and 32 */

uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit
Segment 2.
This parameter must be a number between 1
and 16 */

uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address.

This parameter must be a number between 0
and 2560 */

uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID

filters.
This parameter must be a number between 0
and 128 */

uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID

filters.
This parameter must be a number between 0
and 64 */
 uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements.
This parameter must be a number between 0
and 64 */

uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0

element.
This parameter can be a value of @ref
FDCAN_data_field_size */

uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements.

This parameter must be a number between 0
and 64 */

uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1

element.
This parameter can be a value of @ref
FDCAN_data_field_size */

uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer

elements.
This parameter must be a number between 0
and 64 */

uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer

element.
This parameter can be a value of @ref
FDCAN_data_field_size */

uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements.

This parameter must be a number between 0
and 32 */

uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers.

This parameter must be a number between 0
and 32 */

uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx

FIFO/Queue.
This parameter must be a number between 0
and 32 */

uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.

This parameter can be a value of @ref
FDCAN_txFifoQueue_Mode */
 uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element.
This parameter can be a value of @ref
FDCAN_data_field_size */

} FDCAN_InitTypeDef;

Let's explain the structure members one by one ：

• FrameFormat

Used for setting up CAN The frame format .

#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /* classic CAN Pattern */

#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /* FD CAN Without variable baud rate
*/
#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /* FD CAN With
variable baud rate */

• Mode

Used for setting up CAN Operation mode .

#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode

*/
#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Limited mode of operation
*/
#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus monitoring mode
*/
#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal loopback mode
*/
#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External loopback mode
*/

• AutoRetransmission

Enable automatic retransmission mode .

Can make ENABLE Or forbid DISABLE.

• TransmitPause

Enable or disable the transmission pause feature .ENABLE Enable or DISABLE prohibit .

• ProtocolException

Enable or disable protocol exception management .ENABLE To enable ,DISABLE It is forbidden to .

• NominalPrescaler

be used for CAN FD Frequency division setting in arbitration stage , The amount of time that the nominal bit is
generated , Parameter range 1-512.

• NominalSyncJumpWidth
 Set up FD CAN The maximum amount of time supported in the arbitration phase can be lengthened or
shortened by one bit To achieve resynchronization , Parameter range 1-128.

• NominalTimeSeg1

Set the arbitration phase Bit Segment 1 Time amount of , Range 2 – 256.

• NominalTimeSeg2

Set the arbitration phase Bit Segment 2 Time amount of , Range 2 – 128.

• DataPrescaler

be used for CAN FD Data stage frequency division setting , Range 1-32.

• DataSyncJumpWidth

Set up FD CAN The maximum amount of time supported in the data phase can be lengthened or shortened by
one bit To achieve data resynchronization , Parameter range 1-16.

• DataTimeSeg1

Set the data stage Data Bit Segment 1 Time amount of , Range 1 – 32.

• DataTimeSeg2

Set the data stage Data Bit Segment 2 Time amount of , Range 1 – 16.

• MessageRAMOffset

Setup message RAM Initial address , Range 0 To 2560.

• StdFiltersNbr

standard ID Number of filters , Range 0 To 128.

• ExtFiltersNbr

Expand ID Number of filters , Range 0 To 64.

• RxFifo0ElmtsNbr

RX FIFO0 Element number , Range 0 To 64.

• RxFifo0ElmtSize

RX FIFO0 The size of the data in each element , The supported parameters are as follows ：

#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */

#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */

• RxFifo1ElmtsNbr
 RX FIFO1 Number , Range 0 To 64.

• RxFifo1ElmtSize

RX FIFO1 The size of the data in each element , The supported parameters are as follows ：

#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */

#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */

• RxBuffersNbr

Set up Rx Buffer Element number , Range 0 - 64：

• RxBuffersSize

Set up Rx Buffer The size of each data in the element , Range 0 - 64：

#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */

#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */

• TxEventsNbr

Tx Event FIFO Element number , Range 0 To 32.

• TxBuffersNbr

Set a dedicated Tx Buffer Element number , Range 0 To 32.

• TxFifoQueueElmtsNbr

Setting is used for Tx FIFO/Queue Of Tx Buffers Number . Range 0 To 32.

• TxFifoQueueMode

Set up FIFO Mode or QUEUE Queue mode .

#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */

#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */

• TxElmtSize

Set up Tx Element Data field size in . The supported parameters are as follows ：

#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */

#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
91.3.4 FDCAN Bus message RAM Address FDCAN_MsgRamAddressTypeDef

Here's the news RAM Structure ：

typedef struct
{
uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
This parameter must be a 32-bit word address */

uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
This parameter must be a 32-bit word address */

uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address.

This parameter must be a 32-bit word address */

uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address.

This parameter must be a 32-bit word address */

uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address.

This parameter must be a 32-bit word address */

uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address.

This parameter must be a 32-bit word address */

uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address.

This parameter must be a 32-bit word address */

uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address.

This parameter must be a 32-bit word address */

uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address.

This parameter must be a 32-bit word address */

uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM.
This parameter must be a 32-bit word address */

} FDCAN_MsgRamAddressTypeDef;

Let's explain the structure members one by one ：

• StandardFilterSA

Set the starting address of the standard filter , Must be 32bit Address .

• ExtendedFilterSA

Set the start address of the extension filter , Must be 32bit Address .

• RxFIFO0SA

Set up RX FIFO 0 Initial address , Must be 32bit Address .

• RxFIFO1SA

Set up RX FIFO 1 Initial address , Must be 32bit Address .

• RxBufferSA

Set up RX Buffer Initial address , Must be 32bit Address .

• TxEventFIFOSA

Set up Tx Event FIFO Initial address , Must be 32bit Address .

• TTMemorySA

Set the starting address of trigger memory , Must be 32bit Address .

• EndAddress

Set up application RAM The end address of the space , Must be 32bit Address .

91.3.5 FDCAN Bus filter structure FDCAN_FilterTypeDef

Here is the filter structure ：

typedef struct
{
uint32_t IdType; /*!< Specifies the identifier type.
This parameter can be a value of @ref FDCAN_id_type
*/

uint32_t FilterIndex; /*!< Specifies the filter which will be initialized.

This parameter must be a number between:
- 0 and 127, if IdType is FDCAN_STANDARD_ID
- 0 and 63, if IdType is FDCAN_EXTENDED_ID
*/

uint32_t FilterType; /*!< Specifies the filter type.

This parameter can be a value of @ref FDCAN_filter_type.
The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
only when IdType is FDCAN_EXTENDED_ID.
This parameter is ignored if FilterConfig is set to
 FDCAN_FILTER_TO_RXBUFFER
*/

uint32_t FilterConfig; /*!< Specifies the filter configuration.

This parameter can be a value of @ref
FDCAN_filter_config */

uint32_t FilterID1; /*!< Specifies the filter identification 1.

This parameter must be a number between:
- 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
*/

uint32_t FilterID2; /*!< Specifies the filter identification 2.

This parameter is ignored if FilterConfig is set to
FDCAN_FILTER_TO_RXBUFFER.
This parameter must be a number between:
- 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
*/

uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the
matching message will be stored.
This parameter must be a number between 0 and 63.
This parameter is ignored if FilterConfig is different
from FDCAN_FILTER_TO_RXBUFFER
*/

uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for

calibration messages.
This parameter is ignored if FilterConfig is different
from FDCAN_FILTER_TO_RXBUFFER.
This parameter can be:
- 0 : ordinary message
- 1 : calibration message
*/

} FDCAN_FilterTypeDef;

• IdType

Used to set the standard ID And extend ID.

#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< standard ID */

#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Expand ID */

• FilterIndex
 Used to filter indexes , If it is the standard ID, Range 0 To 127. If it's an extension ID, Range 0 To 64.

• FilterType

Used to set the filter type . If members FilterConfig Set to FDCAN_FILTER_TO_RXBUFFER, This parameter will not
work .

#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filtering from FilterID1 To

FilterID2 */
#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< special ID Filter ,FilterID1 perhaps
FilterID2 */

/*!< Precision shielding filtering ,FilterID1 = filter, FilterID2 = mask */

#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U)

/*!< only ID Extended mode supports this parameter , Range from FilterID1 To FilterID2, EIDM
mask not applied */
#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U)

• FilterConfig

Used to set the filter type .

#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) Filtering is prohibited

#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) If the filter matches , Save data to
Rx FIFO 0
#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) If the filter matches , Save data to
Rx FIFO 1
#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) If the filter matches , Reject this
ID
#define FDCAN_FILTER_HP ((uint32_t)0x00000004U) If the filter matches , Set high
priority
#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) If the filter matches , Set high
priority and save to FIFO 0
#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) If the filter matches , Set high
priority and save to FIFO 1
#define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) If the filter matches , Save to Rx
Buffer, And ignore FilterType
To configure

• FilterID1

Used to set filtering ID1. If ID The type is FDCAN_STANDARD_ID, Range 0 To 0x7FF. If ID The type is
FDCAN_EXTENDED_ID, The scope is 0 To 0x1FFFFFFF.

• FilterID2

Used to set filtering ID2. If FilterConfig Set to FDCAN_FILTER_TO_RXBUFFER, This parameter has no effect . If ID
The type is FDCAN_STANDARD_ID, Range 0 To 0x7FF. If ID The type is FDCAN_EXTENDED_ID, The scope is 0 To
0x1FFFFFFF.

• RxBufferIndex
 The matching message is stored in Rx buffer Index in . Parameter range 0 To 63. If FilterConfig Set to
FDCAN_FILTER_TO_RXBUFFER, This parameter has no effect .

• IsCalibrationMsg

Used to set whether to configure calibration messages . If FilterConfig Set to FDCAN_FILTER_TO_RXBUFFER,

This parameter has no effect .

0 ： Indicates a normal message .

1 ： Flag calibration message .

91.3.6 FDCAN Bus message sending structure FDCAN_TxHeaderTypeDef

Here is CAN FD Send message structure ：

typedef struct
{
uint32_t Identifier; /*!< Specifies the identifier.
This parameter must be a number between:
- 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
*/

uint32_t IdType; /*!< Specifies the identifier type for the message that will be
transmitted.
This parameter can be a value of @ref FDCAN_id_type
*/

uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be
transmitted.
This parameter can be a value of @ref
FDCAN_frame_type */

uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted.
This parameter can be a value of @ref
FDCAN_data_length_code */

uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.

This parameter can be a value of @ref
FDCAN_error_state_indicator */

uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or
without
bit rate switching.
This parameter can be a value of @ref
FDCAN_bit_rate_switching */
 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in
classic or
FD format.
This parameter can be a value of @ref FDCAN_format
*/

uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control.

This parameter can be a value of @ref FDCAN_EFC
*/

uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event
FIFO
element for identification of Tx message status.
This parameter must be a number between 0 and 0xFF
*/

} FDCAN_TxHeaderTypeDef;

• Identifier

Used for setting up ID, If IdType It's a standard. FDCAN_STANDARD_ID, Range 0 To 0x7FF, If IdType yes
FDCAN_EXTENDED_ID Expand ID, Range 0 To 0x1FFFFFFF.

• IdType

Used to set the standard ID Or expand ID.

#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< standard ID */

#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Expand ID */

• TxFrameType

Used to set the frame type , Data frame or remote control frame .

#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */

#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote control frame */

• DataLength

Used to set the data length .

#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */

#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */

• ErrorStateIndicator

Used to set error status indication ：

#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transport nodes error active */

#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transport nodes error passive */

• BitRateSwitch

Used to set whether the baud rate of transmission is variable .

#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN Frame sending / Receive without variable
baud rate */
#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN Frame sending / The baud rate of the
receiving band is variable */

• FDFormat

Used to set whether the transmission frame is in classic format or CANFD Format .

#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame sending / Receive and use classic
CAN */
#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame sending / Receive use FDCAN Format
*/

• TxEventFifoControl

Used to set sending events FIFO control .

#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */

#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Storage Tx events */

• MessageMarker

Used to copy settings to TX EVENT FIFO The news of Maker, To identify the message status , Range 0 To 0xFF.

91.3.7 FDCAN Bus message receiving structure FDCAN_RxHeaderTypeDef

Here is CAN FD Receive message structure ：

typedef struct
{
uint32_t Identifier; /*!< Specifies the identifier.
This parameter must be a number between:
- 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
- 0 and 0x1FFFFFFF, if IdType is
FDCAN_EXTENDED_ID */

uint32_t IdType; /*!< Specifies the identifier type of the received message.
This parameter can be a value of @ref
FDCAN_id_type */
 uint32_t RxFrameType; /*!< Specifies the the received message frame type.
This parameter can be a value of @ref
FDCAN_frame_type */

uint32_t DataLength; /*!< Specifies the received frame length.

This parameter can be a value of @ref
FDCAN_data_length_code */

uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.

This parameter can be a value of @ref
FDCAN_error_state_indicator */

uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or

without bit
rate switching.
This parameter can be a value of @ref
FDCAN_bit_rate_switching */

uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or

FD
format.
This parameter can be a value of @ref FDCAN_format
*/

uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start
of frame
reception.
This parameter must be a number between 0 and
0xFFFF */

uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter

element.
This parameter must be a number between:
- 0 and 127, if IdType is FDCAN_STANDARD_ID
- 0 and 63, if IdType is FDCAN_EXTENDED_ID
*/

uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx
filter.
Acceptance of non-matching frames may be
enabled via
HAL_FDCAN_ConfigGlobalFilter().
 This parameter can be 0 or 1
*/

} FDCAN_RxHeaderTypeDef;

• Identifier

Used for setting up ID, If IdType It's a standard. FDCAN_STANDARD_ID, Range 0 To 0x7FF, If IdType yes
FDCAN_EXTENDED_ID Expand ID, Range 0 To 0x1FFFFFFF.

• IdType

Used to set flags ID Or expand ID.

#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< standard ID */

#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Expand ID */

• RxFrameType

Used to set the received frame type , Data frame or remote control frame

#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */

#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote control frame */

• DataLength

Used to set the data length .

#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */

#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */

• ErrorStateIndicator

Used to set error status indication ：

#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transport nodes error active */

#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transport nodes error passive */

• BitRateSwitch

Used to set whether baud rate switching is available for reception

 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN Frame sending / Receiving does not
support variable baud rate */
#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN Frame sending / Receiving supports
variable baud rate */

• FDFormat

Used to set whether the received frame is in classic format or CANFD Format

#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Classic frame */

#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< FDCAN frame */

• RxTimestamp

Used to set the frame reception timestamp , Range 0 To 0xFFFF.

• FilterIndex

Used to set the receive filter index . If it is the standard ID, Range 0 To 127, If it's an extension ID, Range 0 To
63.

• IsFilterMatchingFrame

Used to set whether to receive non matching frames , By function HAL_FDCAN_ConfigGlobalFilter() You can
make .

0： It means not to accept .

1： To receive .

91.3.8 FDCAN Bus handle structure FDCAN_HandleTypeDef

Here is CANFD Handle structure ：

#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
typedef struct __FDCAN_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
{
FDCAN_GlobalTypeDef *Instance; /*!< Register base address */

TTCAN_TypeDef *ttcan; /*!< TT register base address */

FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */

FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */

uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index

of latest Tx FIFO/Queue request */

__IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */

 HAL_LockTypeDef Lock; /*!< FDCAN locking object */

__IO uint32_t ErrorCode; /*!< FDCAN Error code */

#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t
ClkCalibrationITs); /*!< FDCAN Clock Calibration callback */
void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
/*!< FDCAN Tx Event Fifo callback */
void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
/*!< FDCAN Rx Fifo 0 callback */
void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
/*!< FDCAN Rx Fifo 1 callback */
void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);
/*!< FDCAN Tx Fifo Empty callback */
void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t
BufferIndexes); /*!< FDCAN Tx Buffer complete callback */
void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
/*!< FDCAN Tx Buffer abort callback */
void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);
/*!< FDCAN Rx Buffer New Message callback */
void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);
/*!< FDCAN High priority message callback */
void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);
/*!< FDCAN Timestamp wraparound callback */
void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);
/*!< FDCAN Timeout occurred callback */
void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);
/*!< FDCAN Error callback */
void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
/*!< FDCAN Error status callback */
void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t
TTSchedSyncITs); /*!< FDCAN T Schedule Synchronization callback */
void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
/*!< FDCAN TT Time Mark callback */
void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t
SWCycleCount); /*!< FDCAN TT Stop Watch callback */
void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
/*!< FDCAN TT Global Time callback */

void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);

/*!< FDCAN Msp Init callback */
void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);
/*!< FDCAN Msp DeInit callback */
 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */

} FDCAN_HandleTypeDef;

matters needing attention ：

Conditional compilation USE_HAL_FDCAN_REGISTER_CALLBACKS Used to set whether to use custom callback

or default callback , This definition is generally placed in stm32h7xx_hal_conf.h The file contains ：

#define USE_HAL_FDCAN_REGISTER_CALLBACKS 1

function HAL_FDCAN_RegisterCallback Register callback , Unregister to use functions

HAL_FDCAN_UnRegisterCallback.

Here we focus on the following parameters , Other parameters are mainly HAL Use and customize callback
functions inside the library .

• FDCAN_GlobalTypeDef *Instance

This parameter is an example of a register , Easy to operate registers .

• TTCAN_TypeDef *ttcan

TT CAN Time trigger register base address .

• FDCAN_InitTypeDef Init

FDCAN Related initialization parameters .

• FDCAN_MsgRamAddressTypeDef msgRam

news RAM Address .

• uint32_t LatestTxFifoQRequest

Tx buffer Index last Tx FIFO/Queue Parameters .

• __IO HAL_FDCAN_StateTypeDef State

HAL_LockTypeDef Lock

__IO uint32_t ErrorCode

Status parameters used internally in the program .

• The rest are callback functions

91.4 FD CAN Bus source file stm32h7xx_hal_fdcan.c

There are many functions involved in this file , Here are a few common functions to do a description ：

91.4.1 function HAL_FDCAN_Init

The function prototype ：
HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
{
uint32_t tickstart;
HAL_StatusTypeDef status;
const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};

/* testing FDCAN Whether the handle is valid */

if (hfdcan == NULL)
{
return HAL_ERROR;
}

/* Check FDCAN Exemplification */

if (hfdcan->Instance == FDCAN1)
{
hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
}

/* Check function parameters */

assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
{
assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
}
assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U));
assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U));
assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U));
if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
{
assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
}
assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U));
if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
{
 assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
}
assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U));
if (hfdcan->Init.RxBuffersNbr > 0U)
{
assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
}
assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U));
assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan-
>Init.TxFifoQueueElmtsNbr), 32U));
if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
{
assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
}
if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
{
assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
}

#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
if (hfdcan->State == HAL_FDCAN_STATE_RESET)
{
/* Unlock */
hfdcan->Lock = HAL_UNLOCKED;

/* Reset the default callback */

hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak
ClockCalibrationCallback */
hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak
TxEventFifoCallback */
hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak
RxFifo0Callback */
hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak
RxFifo1Callback */
hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak
TxFifoEmptyCallback */
hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak
TxBufferCompleteCallback */
hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak
TxBufferAbortCallback */
hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback; /* Legacy weak
RxBufferNewMessageCallback */
hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak
HighPriorityMessageCallback */
 hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak
TimestampWraparoundCallback */
hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak
TimeoutOccurredCallback */
hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak
ErrorCallback */
hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak
ErrorStatusCallback */
hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak
TT_ScheduleSyncCallback */
hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak
TT_TimeMarkCallback */
hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak
TT_StopWatchCallback */
hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak
TT_GlobalTimeCallback */

if (hfdcan->MspInitCallback == NULL)
{
hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */
}

/* initialization CLOCK and NVIC */

hfdcan->MspInitCallback(hfdcan);
}
#else
if (hfdcan->State == HAL_FDCAN_STATE_RESET)
{
/* Unlock */
hfdcan->Lock = HAL_UNLOCKED;

/* Initialize the underlying hardware */

HAL_FDCAN_MspInit(hfdcan);
}
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */

/* sign out Sleep */

CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);

/* Get clock */
tickstart = HAL_GetTick();

/* wait for Sleep Mode confirmation */

while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
{
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;

/* change FDCAN state */

hfdcan->State = HAL_FDCAN_STATE_ERROR;

return HAL_ERROR;
}
}

/* Request initialization */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);

/* Get clock */
tickstart = HAL_GetTick();

/* wait for CCCR The register of INIT position */

while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
{
/* Check overflow time */
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;

/* Set up FDCAN state */

hfdcan->State = HAL_FDCAN_STATE_ERROR;

return HAL_ERROR;
}
}

/* Enable configuration modification */

SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);

/* Set whether to retransmit automatically */

if (hfdcan->Init.AutoRetransmission == ENABLE)
{
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
}
else
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
}

/* Set the transmission pause feature */

if (hfdcan->Init.TransmitPause == ENABLE)
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
}
else
{
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
}

/* Set protocol exception handling */

if (hfdcan->Init.ProtocolException == ENABLE)
{
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
}
else
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
}

/* Set up FDCAN The frame format */

MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);

/* Reset FDCAN Operation mode */

CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);

/* Set up FDCAN Operation mode :

| Normal | Restricted | Bus | Internal | External
| | Operation | Monitoring | LoopBack | LoopBack
CCCR.TEST | 0 | 0 | 0 | 1 | 1
CCCR.MON | 0 | 0 | 1 | 1 | 0
TEST.LBCK | 0 | 0 | 0 | 1 | 1
CCCR.ASM | 0 | 1 | 0 | 0 | 0
*/
if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
{
/* Enable to limit the mode of operation */
 SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
}
else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
{
if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
{
/* TEST Register write access enable */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);

/* Enable loopback mode */

SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);

if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
}
}
else
{
/* Enable detection mode */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
}
}
else
{
/* Nothing to do: normal mode */
}

/* Set up nominal bit timing register */

hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) <<
FDCAN_NBTP_NSJW_Pos) | \
(((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) <<
FDCAN_NBTP_NTSEG1_Pos) | \
(((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) <<
FDCAN_NBTP_NTSEG2_Pos) | \
(((uint32_t)hfdcan->Init.NominalPrescaler - 1U) <<
FDCAN_NBTP_NBRP_Pos));

/* If enabled BRS（BitRate Switching Variable baud rate ）, Set up data bit timing register
*/
if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
{
 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) <<
FDCAN_DBTP_DSJW_Pos) | \
(((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) <<
FDCAN_DBTP_DTSEG1_Pos) | \
(((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) <<
FDCAN_DBTP_DTSEG2_Pos) | \
(((uint32_t)hfdcan->Init.DataPrescaler - 1U) <<
FDCAN_DBTP_DBRP_Pos));
}

if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)

{
/* Set up Tx FIFO or Tx Queue Operation mode */
SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
}

/* To configure Tx element size */

if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
{
MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
}

/* To configure Rx FIFO 0 size */

if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
{
MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan-
>Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
}

/* To configure Rx FIFO 1 size */

if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
{
MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan-
>Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
}

/* To configure Rx buffer element size */

if (hfdcan->Init.RxBuffersNbr > 0U)
{
MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize]
<< FDCAN_RXESC_RBDS_Pos));
}
 /* The default is the event trigger mode , If time triggered mode is used , Users need to
HAL_FDCAN_Init
After the call HAL_FDCAN_TT_ConfigOperation */
if (hfdcan->Instance == FDCAN1)
{
CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
}

/* initialization Tx FIFO/Queue */
hfdcan->LatestTxFifoQRequest = 0U;

/* Initialization error code */

hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;

/* initialization FDCAN state */

hfdcan->State = HAL_FDCAN_STATE_READY;

/* Calculate each RAM Block address */

status = FDCAN_CalcultateRamBlockAddresses(hfdcan);

/* Return function status */

return status;
}
Function description ：

This function is used to initialize FDCAN.

Function parameter ：
• The first 1 The parameters are FDCAN_HandleTypeDef Type struct pointer variable , Used to configure
parameters to be initialized .
• Return value , return HAL_TIMEOUT Said the timeout ,HAL_ERROR Parameter error ,HAL_OK Means the
delivery is successful. ,HAL_BUSY Means busy , In use .
matters needing attention ：
1. function HAL_FDCAN_MspInit For initialization FDCAN The underlying clock 、 Pin and other functions . You
need to implement specific functions in this function . Because this function is weakly defined , Allow users to
re implement this function in other source files of the project . Of course , There is no limit to the
implementation of this function , It can also be like the early standard library , Users can initialize themselves ,
More flexible .
2. If formal parameter hfdcan The structural members of State No initial state , This place is a pit . In particular, the
user made a local variable FDCAN_HandleTypeDef FdCANHandle.

For local variables , This parameter is a random value , If it's a global variable , commonly MDK and IAR All
variables are initialized to 0, And this happens to be HAL_FDCAN_STATE_RESET = 0x00U.

There are three solutions

Method 1： The user initializes itself FDCAN And involved in GPIO etc. .
Method 2： Definition FDCAN_HandleTypeDef FdCANHandle Is a global variable .

Method 3： The following method

if(HAL_FDCAN_DeInit(&FdCANHandle) != HAL_OK)
{
Error_Handler();
}
if(HAL_FDCAN_Init(&FdCANHandle) != HAL_OK)
{
Error_Handler();
}
Use examples ：
FDCAN_HandleTypeDef hfdcan1;

/*
*************************************************************************************************
********
* Letter Count name : bsp_InitCan1
* Functional specifications : initial CAN1
* shape ginseng : nothing
* return return value : nothing
*************************************************************************************************
********
*/
void bsp_InitCan1(void)
{
/* Bit time characteristic configuration
Bit time parameter | Nominal | Data
---------------------------|--------------|----------------
fdcan_ker_ck | 20 MHz | 20 MHz
Time_quantum (tq) | 50 ns | 50 ns
Synchronization_segment | 1 tq | 1 tq
Propagation_segment | 23 tq | 1 tq
Phase_segment_1 | 8 tq | 4 tq
Phase_segment_2 | 8 tq | 4 tq
Synchronization_Jump_width | 8 tq | 4 tq
Bit_length | 40 tq = 2us | 10 tq = 0.5us
Bit_rate | 0.5 MBit/s | 2 MBit/s
*/
hfdcan1.Instance = FDCAN1; /* To configure FDCAN1 */
hfdcan1.Init.FrameFormat = FDCAN_FRAME_FD_BRS; /* Configuration and use FDCAN Variable
baud rate */
hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; /* Configure to use normal mode */
hfdcan1.Init.AutoRetransmission = ENABLE; /* Enable automatic retransmission */
 hfdcan1.Init.TransmitPause = DISABLE; /* Configure the disable transmission
pause feature */
hfdcan1.Init.ProtocolException = ENABLE; /* Protocol exception handling enable
*/

/*
Configure baud rate in arbitration phase
CAN The clock 20MHz when , The baud rate in the arbitration phase is
CAN FD Freq / (Sync_Seg + Pro_Seg + Phase_Seg1 + Phase_Seg2) = 20MHz /
（1+0x1F + 8） = 0.5Mbps

among Sync_Seg It's a fixed value = 1 , Pro_Seg + Phase_Seg1 =

NominalTimeSeg1, Phase_Seg2 = NominalTimeSeg2
*/
/* CAN Clock allocation settings , Generally set as 1 that will do , All by PLL Good
configuration ,tq = NominalPrescaler x (1/ fdcan_ker_ck) */
hfdcan1.Init.NominalPrescaler = 0x01;

/* For dynamic adjustment Phase_Seg1 and Phase_Seg1, So you can't compare

Phase_Seg1 and Phase_Seg1 Big */
hfdcan1.Init.NominalSyncJumpWidth = 0x08;

/* Pay special attention here Seg1, Here is the sum of the two parameters , Corresponding bit
time characteristic diagram Pro_Seg + Phase_Seg1 */
hfdcan1.Init.NominalTimeSeg1 = 0x1F;

/* Corresponding bit time characteristic diagram Phase_Seg2 */

hfdcan1.Init.NominalTimeSeg2 = 0x08;

/*
Configure baud rate in data phase
CAN The clock 20MHz when , The baud rate in the data phase is
CAN FD Freq / (Sync_Seg + Pro_Seg + Phase_Seg1 + Phase_Seg2) = 20MHz / （1+5+
4） = 2Mbps

among Sync_Seg It's a fixed value = 1 , Pro_Seg + Phase_Seg1 =

DataTimeSeg1, Phase_Seg2 = DataTimeSeg2
*/
/* CAN Clock allocation settings , Generally set as 1 that will do , All by PLL Good
configuration ,tq = NominalPrescaler x (1/ fdcan_ker_ck),
Range 1-32 */
hfdcan1.Init.DataPrescaler = 0x01;
/* For dynamic adjustment Phase_Seg1 and Phase_Seg1, So you can't compare Phase_Seg1 and
Phase_Seg1 Big , Range 1-16 */
hfdcan1.Init.DataSyncJumpWidth = 0x04;

/* Pay special attention here Seg1, Here is the sum of the two parameters , Corresponding bit
time characteristic diagram Pro_Seg + Phase_Seg1, Range */
hfdcan1.Init.DataTimeSeg1 = 0x05;

/* Corresponding bit time characteristic diagram Phase_Seg2 */

hfdcan1.Init.DataTimeSeg2 = 0x04;

hfdcan1.Init.MessageRAMOffset = 0; /* CAN1 and CAN2 share 2560 A word , here CAN1

Before distribution 1280 word */

hfdcan1.Init.StdFiltersNbr = 1; /* Set standards ID

Number of filters , Range 0-128 */
hfdcan1.Init.ExtFiltersNbr = 0; /* Set extension ID
Number of filters , Range 0-64 */
hfdcan1.Init.RxFifo0ElmtsNbr = 2; /* Set up Rx FIFO0 Number of
elements of , Range 0-64 */
/* Set up Rx FIFO0 The size of each element in the , Support 8,12,16,20,24,32,48
perhaps 64 byte */
hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxFifo1ElmtsNbr = 0; /* Set up Rx FIFO1 Number of
elements of , Range 0-64 */

/* Set up Rx FIFO1 The size of each element in the , Support 8,12,16,20,24,32,48 perhaps 64 byte
*/
hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxBuffersNbr = 0; /* Set up Rx Buffer Number , Range
0-64 */

/* Set up Rx Buffer The size of each element in the , Support 8,12,16,20,24,32,48 perhaps 64
byte */
hfdcan1.Init.RxBufferSize = 0;

hfdcan1.Init.TxEventsNbr = 0; /* Set up Tx Event FIFO The number of elements

in , Range 0-32 */
hfdcan1.Init.TxBuffersNbr = 0; /* Set up Tx Buffer The number of elements in
, Range 0-32 */
 hfdcan1.Init.TxFifoQueueElmtsNbr = 2; /* Setting is used for Tx FIFO/Queue Of Tx
Buffers Number . Range 0 To 32 */
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; /* Set up FIFO Mode or QUEUE
Queue mode */

/* Set up Tx Element Data field size in , Support 8,12,16,20,24,32,48 perhaps 64 byte */

hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
HAL_FDCAN_Init(&hfdcan1);

// Omit unwritten

}
91.4.2 function HAL_FDCAN_DeInit
The function prototype ：
HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
{
/* Detect handle */
if (hfdcan == NULL)
{
return HAL_ERROR;
}

/* Check function parameters */

assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));

/* stop it FDCAN */
(void)HAL_FDCAN_Stop(hfdcan);

/* No interruptions */
CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));

#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
if (hfdcan->MspDeInitCallback == NULL)
{
hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
}

/* Reset the underlying hardware , Like a clock ,NVIC etc. */

hfdcan->MspDeInitCallback(hfdcan);
#else
/* Reset the underlying hardware , Like a clock ,NVIC etc. */
HAL_FDCAN_MspDeInit(hfdcan);
#endif
 /* Reset error code */
hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;

/* Set up FDCAN state */

hfdcan->State = HAL_FDCAN_STATE_RESET;

/* return HAL_OK */
return HAL_OK;
}
Function description ：

Used to reset FDCAN.

Function parameter ：
• The first 1 The parameters are FDCAN_HandleTypeDef Type struct pointer variable .
• Return value , return HAL_TIMEOUT Said the timeout ,HAL_ERROR Parameter error ,HAL_OK Means the
delivery is successful. ,HAL_BUSY Means busy , In use .
91.4.3 function HAL_FDCAN_ConfigFilter
The function prototype ：
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef
*sFilterConfig)
{
uint32_t FilterElementW1;
uint32_t FilterElementW2;
uint32_t *FilterAddress;
HAL_FDCAN_StateTypeDef state = hfdcan->State;

if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))

{
/* Detect function parameters */
assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
{
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U));
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U));
}

/* standard ID */
if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
{
/* Detect function parameters */
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr -
1U)));
 assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
{
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
}

/* Build filter elements */

if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
{
FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U) |
(sFilterConfig->FilterID1 << 16U) |
(sFilterConfig->IsCalibrationMsg << 8U) |
sFilterConfig->RxBufferIndex);
}
else
{
FilterElementW1 = ((sFilterConfig->FilterType << 30U) |
(sFilterConfig->FilterConfig << 27U) |
(sFilterConfig->FilterID1 << 16U) |
sFilterConfig->FilterID2);
}

/* Calculate filter address */

FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex
* 4U));

/* Write the filter element to the message RAM in */

*FilterAddress = FilterElementW1;
}
/* Expand ID */
else
{
/* Detect function parameters */
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr -
1U)));
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
{
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
}
 /* Build a second 1 individual word Filter elements for */
FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);

/* Build a second 2 individual word Filter elements for */

if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
{
FilterElementW2 = sFilterConfig->RxBufferIndex;
}
else
{
FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
}

/* Calculate filter address */

FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex
* 4U * 2U));

/* Write filter elements to messages RAM */

*FilterAddress = FilterElementW1;
FilterAddress++;
*FilterAddress = FilterElementW2;
}

return HAL_OK;
}
else
{
/* Update error code e */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;

return HAL_ERROR;
}
}
Function description ：

This function is mainly used to set FDCAN Filter .

Function parameter ：
• The first 1 The parameters are FDCAN_HandleTypeDef Type struct pointer variable .
• The first 2 The parameters are FDCAN_FilterTypeDef Type structure variable , It is mainly used for filtering
parameter configuration .
• Return value , return HAL_TIMEOUT Said the timeout ,HAL_ERROR Parameter error ,HAL_OK Means the
delivery is successful. ,HAL_BUSY Means busy , In use .
Use examples ：
FDCAN_HandleTypeDef hfdcan1;
/*
*************************************************************************************************
********
* Letter Count name : bsp_InitCan1
* Functional specifications : initial CAN1
* shape ginseng : nothing
* return return value : nothing
*************************************************************************************************
********
*/
void bsp_InitCan1(void)
{

/*
Configure filters , The filter is mainly used to receive , Here the
sampling mask bit pattern .
FilterID1 = filter
FilterID2 = mask

FilterID2 Of mask Every bit meaning

0: No concern , This bit is not used for comparison ;
1: Must match , The received ID Must correspond to the filter ID Phase
consistent .

Illustrate with examples ：

FilterID1 = 0x111
FilterID2 = 0x7FF
Means to receive only ID by 0x111 Of FDCAN frame .

*/
sFilterConfig1.IdType = FDCAN_STANDARD_ID; /* Set standards ID Or expand
ID */
/* Used to filter indexes , If it is the standard ID, Range 0 To 127. If it's an
extension ID, Range 0 To 64 */
sFilterConfig1.FilterIndex = 0;
sFilterConfig1.FilterType = FDCAN_FILTER_MASK; /* Filter sampling mask bit
mode */
sFilterConfig1.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; /* If the filter matches ,
Save data to Rx FIFO 0 */
sFilterConfig1.FilterID1 = 0x111; /* In shielded bit
mode ,FilterID1 It's the news ID */
sFilterConfig1.FilterID2 = 0x7FF; /* In shielded
bit mode ,FilterID2 Is the message mask bit */
 HAL_FDCAN_ConfigFilter(&hfdcan1, &sFilterConfig1); /* Configure filters */

}
91.4.4 function HAL_FDCAN_ConfigFifoWatermark
The function prototype ：
HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO,
uint32_t Watermark)
{
/* Test parameters */
assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
{
assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U));
}
else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
{
assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U));
}

if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Set send event FIFO */
if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
{
MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark <<
FDCAN_TXEFC_EFWM_Pos));
}
/* Set reception FIFO0 */
else if (FIFO == FDCAN_CFG_RX_FIFO0)
{
MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark <<
FDCAN_RXF0C_F0WM_Pos));
}
/* Set reception FIFO1 */
else
{
MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark <<
FDCAN_RXF1C_F1WM_Pos));
}

/* Return to status */
return HAL_OK;
}
else
 {
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;

return HAL_ERROR;
}
}
Function description ：

This function is mainly used to configure FIFO Watermark

Function parameter ：
• The first 1 The parameters are FDCAN_HandleTypeDef Type struct pointer variable .
• The first 2 The parameters are FDCAN FIFO Watermark
#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
#define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */
#define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */

• The first 3 Parameters FIFO Watermark Interrupt location , If it is FDCAN_CFG_TX_EVENT_FIFO, Range 0 To 32,
If it is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1, Range 0 To 64.
• Return value , return HAL_TIMEOUT Said the timeout ,HAL_ERROR Parameter error ,HAL_OK Means the
delivery is successful. ,HAL_BUSY Means busy , In use .
Use examples ：
FDCAN_HandleTypeDef hfdcan1;

/* Set up Rx FIFO0 Of wartermark by 1 */

HAL_FDCAN_ConfigFifoWatermark(&hfdcan1, FDCAN_CFG_RX_FIFO0, 1);
91.4.5 function HAL_FDCAN_ActivateNotification
The function prototype ：
HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
uint32_t BufferIndexes)
{
HAL_FDCAN_StateTypeDef state = hfdcan->State;

/* Detect function parameters */

assert_param(IS_FDCAN_IT(ActiveITs));

if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))

{
/* Enable interrupt line */
if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
{
/* Enable interrupt line 0 */
SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
}
else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
{
 /* Enable interrupt line 1 */
SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
}
else
{
/* Enable interrupt line 0 And interrupt lines 1 */
hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
}

if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)

{
/* Can make Tx Buffer Transmission interrupt */
SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
}

if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)

{
/* Can make Tx Buffer Cancellation Finished interrupt */
SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
}

/* Enable selected interrupts */

__HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);

/* Return function status */

return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;

return HAL_ERROR;
}
}
Function description ：

This function is mainly used to enable interrupt .

Function parameter ：
• The first 1 The parameters are FDCAN_HandleTypeDef Type struct pointer variable .
• The first 2 Two parameters are used to set the interrupt to be enabled , The supported parameters are as
follows ：
#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed
#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished
*/
#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty

#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received

*/
#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored
into a Rx Buffer

#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around

*/
#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */

#define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state

changed */
#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog
event occurred

#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost

*/
#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full
*/
#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached
watermark */
#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element
*/

#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost

*/
#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full
*/
#define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark
*/
#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0
*/

#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost

*/
#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full
*/
#define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark
*/
#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1
*/
 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred
#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging
Counter occurred
#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to
missing READY
#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase
detected
#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase
detected
#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred

#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */

#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */

• The first 3 The parameters are Tx Buffer Indexes, You can use any combination of the following parameters ：
#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */
#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */
#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */
#define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */
#define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */
#define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */
#define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */
#define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */
#define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */
#define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */
#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
 #define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */

If the first 2 Parameters do not include FDCAN_IT_TX_COMPLETE or FDCAN_IT_TX_ABORT_COMPLETE, This

parameter will be ignored .

• Return value , return HAL_TIMEOUT Said the timeout ,HAL_ERROR Parameter error ,HAL_OK Means the
delivery is successful. ,HAL_BUSY Means busy , In use .
Use examples ：
FDCAN_HandleTypeDef hfdcan1;

/* Activate RX FIFO0 Of watermark Notice of interruption , Bit on Tx Buffer interrupt */

HAL_FDCAN_ActivateNotification(&hfdcan1, FDCAN_IT_RX_FIFO0_WATERMARK, 0);
91.4.6 function HAL_FDCAN_Start
The function prototype ：
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Set up FDCAN Peripheral status */
hfdcan->State = HAL_FDCAN_STATE_BUSY;

/* Request to leave the initialization state */

CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);

/* Set error code */

hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;

return HAL_OK;
}
else
{
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;

return HAL_ERROR;
}
}
Function description ：

This function is mainly used to start FDCAN.

Function parameter ：
• The first 1 The parameters are FDCAN_HandleTypeDef Type struct pointer variable .
• Return value , return HAL_TIMEOUT Said the timeout ,HAL_ERROR Parameter error ,HAL_OK Means the
delivery is successful. ,HAL_BUSY Means busy , In use .
Use examples ：
/**
* @brief Writes block(s) to a specified address in an SD card, in DMA mode.
* @param pData: Pointer to the buffer that will contain the data to transmit
* @param WriteAddr: Address from where data is to be written
* @param NumOfBlocks: Number of SD blocks to write
* @retval SD status
*/
uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)
{

if( HAL_SD_WriteBlocks_DMA(&uSdHandle, (uint8_t *)pData, WriteAddr, NumOfBlocks) == HAL_OK)

{
return MSD_OK;
}
else
{
return MSD_ERROR;
}
}
91.4.7 function HAL_FDCAN_AddMessageToTxFifoQ
The function prototype ：
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan,
FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
{
uint32_t PutIndex;

/* Check function parameters */

assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
if (pTxHeader->IdType == FDCAN_STANDARD_ID)
{
assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
}
else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
{
assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
}
assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));

if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
{
/* testing Tx FIFO/Queue Whether in RAM Space allocated in */
 if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;

return HAL_ERROR;
}

/* Check Tx FIFO/Queue Full or not */

if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;

return HAL_ERROR;
}
else
{
/* obtain Tx FIFO PutIndex */
PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);

/* Add message to Tx FIFO/Queue */

FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);

/* Activate the corresponding transmission request */

hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);

/* Store the most recent Tx FIFO/Queue Request Buffer Index */

hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
}

/* Return error status */

return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;

return HAL_ERROR;
}
}
Function description ：
 This function is used to add a message to Tx FIFO/Queue And activate the corresponding transmission request .

Function parameter ：
• The first 1 The parameters are FDCAN_HandleTypeDef Type struct pointer variable .
• The first 2 The parameters are FDCAN_TxHeaderTypeDef Type structure variable , For message sending .
• The first 3 One parameter is the data address to send . The program will copy the data to the send buffer .
• Return value , return HAL_TIMEOUT Said the timeout ,HAL_ERROR Parameter error ,HAL_OK Means the
delivery is successful. ,HAL_BUSY Means busy , In use .
Use examples ：
/*
*************************************************************************************************
********
* Letter Count name : can1_SendPacket
* Functional specifications : Send a packet of data
* shape ginseng ：_DataBuf Data buffer
* _Len Data length , Support 8,12,16,20,24,32,48 perhaps 64 byte
* return return value : nothing
*************************************************************************************************
********
*/
void can1_SendPacket(uint8_t *_DataBuf, uint8_t _Len)
{
FDCAN_TxHeaderTypeDef TxHeader = {0};

/* Configure send parameters */

TxHeader.Identifier = 0x222; /* Set the time to receive
frame messages ID */
TxHeader.IdType = FDCAN_STANDARD_ID; /* standard ID */
TxHeader.TxFrameType = FDCAN_DATA_FRAME; /* Data frame */
TxHeader.DataLength = (uint32_t)_Len << 16; /* Send data length */
TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE; /* Set error status indication */
TxHeader.BitRateSwitch = FDCAN_BRS_ON; /* Turn on variable baud rate */
TxHeader.FDFormat = FDCAN_FD_CAN; /* FDCAN Format */
TxHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS;/* Used to send events FIFO control ,
Do not store */
TxHeader.MessageMarker = 0; /* Used to copy to TX EVENT FIFO The news of Maker To
identify the message status , Range 0 To 0xFF */

/* Add data to TX FIFO */

HAL_FDCAN_AddMessageToTxFifoQ(&hfdcan1, &TxHeader, _DataBuf);
}
91.4.8 function HAL_FDCAN_GetRxMessage
The function prototype ：
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
{
 uint32_t *RxAddress;
uint8_t *pData;
uint32_t ByteCounter;
uint32_t GetIndex = 0;
HAL_FDCAN_StateTypeDef state = hfdcan->State;

if (state == HAL_FDCAN_STATE_BUSY)
{
if (RxLocation == FDCAN_RX_FIFO0) /* Rx element Assigned to Rx FIFO 0 */
{
/* Check Rx FIFO 0 Allocated RAM Space */
if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;

return HAL_ERROR;
}

/* Check Rx FIFO 0 Non empty */

if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;

return HAL_ERROR;
}
else
{
/* Check Rx FIFO 0 Full and open overlay mode */
if(((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
{
if(((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) ==
FDCAN_RX_FIFO_OVERWRITE)
{
/* Overlay mode is turned on , Discard the second 1 Data */
GetIndex = 1U;
}
}

/* Calculation Rx FIFO 0 element Indexes */

GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
 /* Calculation Rx FIFO 0 element Address */
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan-
>Init.RxFifo0ElmtSize * 4U));
}
}
else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
{
/* Check Rx FIFO 1 Allocated RAM Space */
if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;

return HAL_ERROR;
}

/* Check Rx FIFO 0 Non empty */

if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;

return HAL_ERROR;
}
else
{
/* Check Rx FIFO 1 Full and open overlay mode */
if(((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
{
if(((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) ==
FDCAN_RX_FIFO_OVERWRITE)
{
/* Overlay mode is turned on , Discard the second 1 Data */
GetIndex = 1U;
}
}

/* Calculation Rx FIFO 1 element Indexes */

GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);

/* Calculation Rx FIFO 1 element Address */

RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan-
>Init.RxFifo1ElmtSize * 4U));
 }
}
else /* Rx element Dedicated... Is assigned Rx buffer */
{
/* Check the selected buffer Allocated RAM Space */
if (RxLocation >= hfdcan->Init.RxBuffersNbr)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;

return HAL_ERROR;
}
else
{
/* Calculation Rx buffer Address */
RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan-
>Init.RxBufferSize * 4U));
}
}

/* receive IdType */
pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;

/* receive Identifier */
if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
{
pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
}
else /* Extended ID element */
{
pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
}

/* receive RxFrameType */
pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);

/* receive ErrorStateIndicator */
pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);

/* Increment RxAddress pointer to second word of Rx FIFO element */

RxAddress++;

/* receive RxTimestamp */
pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);

/* receive DataLength */
pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);

/* receive BitRateSwitch */
pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);

/* receive FDFormat */
pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);

/* receive FilterIndex */
pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);

/* receive NonMatchingFrame */
pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);

/* Add address , Point to Rx FIFO element Of payload */

RxAddress++;

/* receive Rx payload */
pData = (uint8_t *)RxAddress;
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
{
pRxData[ByteCounter] = pData[ByteCounter];
}

if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */

{
/* confirm Rx FIFO 0 Advanced data has been read out */
hfdcan->Instance->RXF0A = GetIndex;
}
else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
{
/* confirm Rx FIFO 1 Advanced data has been read out */
hfdcan->Instance->RXF1A = GetIndex;
}
else /* Rx element is assigned to a dedicated Rx buffer */
{
/* Clear current Rx buffer New data flag */
if (RxLocation < FDCAN_RX_BUFFER32)
{
hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
 }
else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
{
hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
}
}

/* Return to status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;

return HAL_ERROR;
}
}
Function description ：

This function is mainly used to obtain the received data .

Function parameter ：
• The first 1 The parameters are FDCAN_HandleTypeDef Type struct pointer variable .
• The first 2 The first parameter is the read location , The following parameters are supported ：
#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */
#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */
#define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */
#define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */
#define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */
#define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */
#define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */
#define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */
#define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */
#define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */
#define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */
#define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */
#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
• The first 3 The parameters are FDCAN_RxHeaderTypeDef Type structure variable , Mainly used for message
receiving .
• The first 4 The first parameter is the data receiving buffer address .
• Return value , return HAL_TIMEOUT Said the timeout ,HAL_ERROR Parameter error ,HAL_OK Means the
delivery is successful. ,HAL_BUSY Means busy , In use .
Use examples ：
/*
*************************************************************************************************
********
* Letter Count name : HAL_FDCAN_RxFifo0Callback
* Functional specifications : CAN Interrupt service routine - Callback function
* shape ginseng : hfdcan
* return return value : nothing
*************************************************************************************************
********
*/
void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
{
if (hfdcan == &hfdcan1)
{
if ((RxFifo0ITs & FDCAN_IT_RX_FIFO0_WATERMARK) != RESET)
{
/* from RX FIFO0 Reading data */
HAL_FDCAN_GetRxMessage(hfdcan, FDCAN_RX_FIFO0, &g_Can1RxHeader,
g_Can1RxData);

/* Activate Rx FIFO0 watermark notification */

HAL_FDCAN_ActivateNotification(hfdcan, FDCAN_IT_RX_FIFO0_WATERMARK,
0);

if (g_Can1RxHeader.Identifier == 0x111 && g_Can1RxHeader.IdType ==

FDCAN_STANDARD_ID)
{
bsp_PutMsg(MSG_CAN1_RX, 0); /* Send a message and
receive a packet , It turns out that g_Can1RxHeader, g_Can1RxData */
}
}
}
}
91.5 summary

So much for you in this chapter , more FDCAN Knowledge can be found in the... Of this tutorial 90 Chapter .

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https://chowdera.com/2021/11/20211123010332633V.html