GATE SOLVED PAPER - EC ANALOG ELECTRONIC

GATE SOLVED PAPER - EC

ANALOG ELECTRONIC

2013 ONE MARK

Q. 1 In the circuit shown below what is the output voltage Vout

^ if ha silicon transistor
Q and an ideal op-amp are used?

(A) -15 V (B) -0.7 V

(C) +0.7 V (D) +15 V

Q. 2 In a voltage-voltage feedback as shown below, which one of the following statements

is TRUE if the gain k is increased?

(A) The input impedance increases and output impedance decreases

(B) The input impedance increases and output impedance also increases
(C) The input impedance decreases and output impedance also decreases
(D) The input impedance decreases and output impedance increases

2013 TWO MARKS

Q. 3 The ac schematic of an NMOS common-source state is shown in the figure below,

where part of the biasing circuits has been omitted for simplicity. For the n
-channel MOSFET M, the transconductance gm = 1 mA / V, and body effect and
channel length modulation effect are to be neglected. The lower cutoff frequency
in HZ of the circuit is approximately at
 (A) 8 (B) 32
(C) 50 (D) 200

Q. 4 In the circuit shown below, the knee current of the ideal Zener dioide is10 mA
. To maintain 5 V across RL , the minimum value of RL in W and the minimum power
rating of the Zener diode in mW , respectively, are

(A) 125 and 125 (B) 125 and 250

(C) 250 and 125 (D) 250 and 250

Q. 5 In the circuit shown below the op-amps are ideal. Then,V out in Volts is

(A) 4 (B) 6
(C) 8 (D) 10

Q. 6 In the circuit shown below, Q1 has negligible collector-to-emitter saturation

voltage and the diode drops negligible voltage across it under forward bias. IfVcc
is +5 V, X and Y are digital signals with 0 V as logic 0 and Vcc as logic 1, then
the Boolean expression for Z is
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) X Y (B) X Y
(C) X Y (D) X Y

Q. 7 A voltage 1000 sin wt Volts is applied across YZ . Assuming ideal diodes, the
voltage measured across W X in Volts, is

(A) sin wt (B) _sin wt + sin wt i / 2

(C) ^sin wt - sin wt h / 2 (D) 0 for all t

Q. 8 In the circuit shown below, the silicon npn transistor Q has a very high value of
b . The required value of R 2 in kW to produce IC = 1 mA is

(A) 20 (B) 30
(C) 40 (D) 50

2012 ONE MARK

Q. 9 The i -v characteristics of the diode in the circuit given below are

v - 0.7 A,
v $ 0.7 V
i = * 500
0A v < 0.7 V
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

The current in the circuit is

(A) 10 mA
(B) 9.3 mA
(C) 6.67 mA
(D) 6.2 mA

Q. 10 The current ib through the base of a siliconnpn transistor is 1 + 0.1 cos (10000pt) mA
At 300 K, the rp in the small signal model of the transistor is

(A) 250 W (B) 27.5 W

(C) 25 W (D) 22.5 W

Q. 11 The diodes and capacitors in the circuit shown are ideal. The voltagev (t) across
the diode D1 is

(A) cos (wt) - 1 (B) sin (wt)

(C) 1 - cos (wt) (D) 1 - sin (wt)

Q. 12 The impedance looking into nodes 1 and 2 in the given circuit is

(A) 50 W (B) 100 W

(C) 5 kW (D) 10.1 kW
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

2012 TWO MARKS

Q. 13 The circuit shown is a

rad /s

1
(A) low pass filter with f3dB =
( R 1 + R2) C
(B) high pass filter with f3dB = 1 rad /s
R 1C
(C) low pass filter with f3dB = 1 rad /s
R 1C
1
(D) high pass filter with f3dB = rad /s
( R 1 + R2) C
Q. 14 The voltage gain A v of the circuit shown below is
A v . 100
A v . 10

(A) A v . 200 (B)

(C) A v . 20 (D)

2011 ONE MARK

Q. 15 In the circuit shown below, capacitors C1 and C2 are very large and are shorts at
the input frequency. vi is a small signal input. The gain magnitude vo at 10 M
vi
rad / s is

(A) maximum (B) minimum

(C) unity (D) zero
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 16 The circuit below implements a filter between the input current ii and the output
voltage vo . Assume that the op-amp is ideal. The filter implemented is a

(A) low pass filter (B) band pass filter

(C) band stop filter (D) high pass filter

2011 TWO MARKS

Q. 17 In the circuit shown below, for the MOS transistors, mn Cox = 100 mA / V 2 and the
threshold voltage VT = 1 V. The voltage Vx at the source of the upper transistor is

(A) 1 V (B) 2 V
(C) 3 V (D) 3.67 V

Q. 18 For a BJT, the common base current gain a = 0.98 and the collector base
junction reverse bias saturation current I CO = 0.6 mA. This BJT is connected in
the common emitter mode and operated in the active region with a base drive
current IB = 20 mA. The collector current IC for this mode of operation is
(A) 0.98 mA (B) 0.99 mA
(C) 1.0 mA (D) 1.01 mA

Q. 19 For the BJT, Q1 in the circuit shown below, b = 3, VBEon = 0.7 V, VCEsat = 0.7 V
. The switch is initially closed. At time t = 0, the switch is opened. The time t at
which Q1 leaves the active region is
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) 10 ms (B) 25 ms
(C) 50 ms (D) 100 ms

Statement for Linked Answer Questions: 20 and 21

In the circuit shown below, assume that the voltage drop across a forward biased
diode is 0.7 V. The thermal voltage Vt = k T /q = 25 mV . The small signal input
vi = Vp cos^wt h where Vp = 100 mV.

Q. 20 The bias current I DC through the diodes is

(A) 1 mA (B) 1.28 mA
(C) 1.5 mA (D) 2 mA

Q. 21 The ac output voltage vac is

(A) 0.25 cos wt
^ mV
h (B) 1 cos (wt) mV
(C) 2 cos (wt) mV (D) 22 cos (wt) mV

2010 ONE MARK

Q. 22 The amplifier circuit shown below uses a silicon transistor. The capacitors CC
and C E can be assumed to be short at signal frequency and effect of output
resistance r0 can be ignored. If C E is disconnected from the circuit, which one of
the following statements is true

(A) The input resistance R i increases and magnitude of voltage gainAV

decreases
(B) The input resistance R i decreases and magnitude of voltage gain A V
increases
(C) Both input resistance R i and magnitude of voltage gain A V decreases
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(D) Both input resistance R i and the magnitude of voltage gain A V increases

Q. 23 In the silicon BJT circuit shown below, assume that the emitter area of transistor
Q1 is half that of transistor Q2

The value of current Io is approximately

(A) 0.5 mA (B) 2 mA
(C) 9.3 mA (D) 15 mA

Q. 24 Assuming the OP-AMP to be ideal, the voltage gain of the amplifier shown below
is

(A) - R 2 (B) - R 3
R1 R1

(D) -b R 2 + R 3 l
R || R 3
(C) - 2
R1 R
1

2010 TWO MARKS

Common Data For Q. 25 and 26

Consider the common emitter amplifier shown below with the following circuit
parameters:
b = 100, gm = 0.3861 A/ V, r0 = 259 W, RS = 1 kW, R B = 93 kW,
RC = 250 kW, R L = 1 kW, C 1 = 3 and C 2 = 4.7 mF
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 25 The resistance seen by the source v S is

(A) 258 W (B) 1258 W
(C) 93 kW (D) 3

Q. 26 The lower cut-off frequency due to C2 is

(A) 33.9 Hz
(B) 27.1 Hz
(C) 13.6 Hz
(D) 16.9 Hz

Q. 27 The transfer characteristic for the precision rectifier circuit shown below is
(assume ideal OP-AMP and practical diodes)

2009 TWO MARKS

Q. 28 In the circuit below, the diode is ideal. The voltageV is given by

(A) min ( Vi, 1) (B) max ( Vi, 1)

(C) min (- Vi , 1) (D) max (- Vi , 1)
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 29 In the following a stable multivibrator circuit, which properties of v0 (t) depend

on R 2?

(A) Only the frequency

(B) Only the amplitude
(C) Both the amplitude and the frequency
(D) Neither the amplitude nor the frequency

Statement for Linked Answer Question 30 and 31

Consider for CMOS circuit shown, where the gate voltagev0 of the n-MOSFET is
increased from zero, while the ga te voltage of the p -MOSFE T is kept constant
at 3 V. Assume, that, for both transistors, the magnitude of the threshold voltage
is 1 V and the product of the trans-conductance parameter is 1mA. V -2

Q. 30 For small increase in VG beyond 1V, which of the following gives the correct
description of the region of operation of each MOSFET
(A) Both the MOSFETs are in saturation region
(B) Both the MOSFETs are in triode region
(C) n-MOSFE Ts is in triode and p -MOSFET is in sa turation region
(D) n- MOSFE T is in sa turation and p -MOSFE T is in triode region

Q. 31 Estimate the output voltage V0 for VG = 1.5 V. [Hints : Use the appropriate
current-voltage equation for each MOSFET, based on the answer to Q.4.16]
(A) 4 - 1 (B) 4 + 1
2 2
(C) 4 - 3 (D) 4 + 3
2 2

Q. 32 In the circuit shown below, the op-amp is ideal, the transistor hasV BE = 0.6 V
and b = 150. Decide whether the feedback in the circuit is positive or negative
and determine the voltage V at the output of the op-amp.
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) Positive feedback, V = 10 V

(B) Positive feedback, V = 0 V
(C) Negative feedback, V = 5 V
(D) Negative feedback, V = 2 V
Q. 33 A small signal source Vi (t) = A cos 20t + B sin 106t is applied to a transistor
amplifier as shown below. The transistor has b = 150 and hie = 3W. Which
expression best approximate V0 (t)

(A) V0 (t) =- 1500( A cos 20t + B sin 106t )

(B) V0 (t) = - 1500( A cos20t + B sin106t )
(C) V0 (t) =- 1500B sin 106t
(D) V0 (t) =- 150B sin 106t

2008 ONE MARK

Q. 34 In the following limiter circuit, an input voltage Vi = 10 sin 100pt is applied.

Assume that the diode drop is 0.7 V when it is forward biased. When it is forward
biased. The zener breakdown voltage is 6.8 V
The maximum and minimum values of the output voltage respectively are

(A) 6.1 V, - 0.7 V (B) 0.7 V, - 7.5 V

(C) 7.5 V, - 0.7 V (D) 7.5 V, - 7.5 V
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

2008 TWO MARSK

Q. 35 For the circuit shown in the following figure, transistor M1 and M2 are identical
NMOS transistors. Assume the M2 is in saturation and the output is unloaded.

The current Ix is related to Ibias as

(A) Ix = Ibias + Is (B) Ix = Ibias
(C) Ix = Ibias - cVDD - V out
(D) Ix = Ibias - Is
RE m
Q. 36 Consider the following circuit using an ideal OPAMP. The I-V characteristic of
V-1
the diode is described by the rela tion I = I 0 _e V i where VT = 25 mV, I0 = 1mA
t

and V is the voltage across the diode (taken as positive for forward bias). For an input
voltage Vi =- 1 V, the output voltage V0 is

(A) 0 V (B) 0.1 V

(C) 0.7 V (D) 1.1 V

Q. 37 The OPAMP circuit shown above represents a

(A) high pass filter

(B) low pass filter
(C) band pass filter
(D) band reject filter

Q. 38 Two identical NMOS transistors M1 and M2 are connected as shown below. Vbias
is chosen so that both transistors are in saturation. The equivalent gm of the pair
is defied to be 2Iout at constant Vout
2Vi
The equivalent gmof the pair is
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) the sum of individual gm 's of the transistors

(B) the product of individual gm ’s of the transistors
(C) nearly equal to the gm of M1
g
(D) nearly equal to m of M2
g0
Q. 39 Consider the Schmidt trigger circuit shown below
A triangular wave which goes from -12 to 12 V is applied to the inverting input
of OPMAP. Assume that the output of the OPAMP swings from + 15 V to -15 V.
The voltage at the non-inverting input switches between

(A) -12V to + 12 V (B) -7.5 V to 7.5 V

(C) -5 V to + 5 V (D) 0 V and 5 V

Statement for Linked Answer Question 40 and 41

In the following transistor circuit, VBE = 0.7 V, r3 = 25 mV / IE , and b and all the
capacitances are very large

Q. 40 The value of DC current IE is

(A) 1 mA (B) 2 mA
(C) 5 mA (D) 10 mA

Q. 41 The mid-band voltage gain of the amplifier is approximately

(A) -180 (B) -120
(C) -90 (D) -60
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

2007 ONE MARK

Q. 42 The correct full wave rectifier circuit is

Q. 43 In a transconductance amplifier, it is desirable to have

(A) a large input resistance and a large output resistance
(B) a large input resistance and a small output resistance
(C) a small input resistance and a large output resistance
(D) a small input resistance and a small output resistance

2007 TWO MARKS

Q. 44 For the Op-Amp circuit shown in the figure, V0 is

(A) -2 V (B) -1 V
(C) -0.5 V (D) 0.5 V

Q. 45 For the BJT circuit shown, assume that the b of the transistor is very large and
VBE = 0.7 V. The mode of operation of the BJT is

(A) cut-off (B) saturation

(C) normal active (D) reverse active

Q. 46 In the Op-Amp circuit shown, assume that the diode current follows the equation
I = Is exp (V /VT ) . For Vi = 2V, V0 = V 01, and for Vi = 4V, V0 = V 02.
The relationship between V01 and V02 is
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) V02 = 2 Vo1 (B) Vo2 = e2 Vo1

(C) Vo2 = Vo11n2 (D) Vo1 - Vo2 = VT 1n2
Q. 47 In the CMOS inverter circuit shown, if the trans conductance parameters of the
NMOS and PMOS transistors are
W
kn = kp = mn Cox Wn = mCox p = 40mA / V2
Ln Lp
and their threshold voltages ae VTHn = VTHp = 1 V the current I is

(A) 0 A (B) 25 mA
(C) 45 mA (D) 90 mA

Q. 48 For the Zener diode shown in the figure, the Zener voltage at knee is 7 V, the knee
current is negligible and the Zener dynamic resistance is 10 W. If the input voltage
( Vi) range is from 10 to 16 V, the output voltage( V0) ranges from

(A) 7.00 to 7.29 V (B) 7.14 to 7.29 V

(C) 7.14 to 7.43 V (D) 7.29 to 7.43 V

Statement for Linked Answer Questions 49 and 50:

Consider the Op-Amp circuit shown in the figure.

Q. 49 The transfer function V0 (s)/ Vi( s) is

(A) 1 - sRC (B) 1 + sRC
1 + sRC 1 - sRC
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

1 (D) 1
(C)
1 - sRC 1 + sRC

Q. 50 If Vi = V1 sin (wt ) and V0 = V2 sin (wt + f), then the minimum and maximum values
of f (in radians) are respectively
(A) - p and p (B) 0 and p
2 2 2
- p
(C) -p and 0 (D) and 0
2

2006 ONE MARK

Q. 51 The input impedance (Z i ) and the output impedance (Z0) of an ideal trans-
conductance (voltage controlled current source) amplifier are
(A) Zi = 0, Z0 = 0
(B) Zi = 0, Z0 = 3
(C) Zi = 3, Z0 = 0
(D) Zi = 3, Z0 = 3
curve:
Q. 52 An n-channel depletion MOSFET has following two points on its ID - VGs
(i) VGS = 0 at ID = 12 mA and
(ii) VGS =- 6 Volts at ID = 0 mA
Which of the following Q point will given the highest trans conductance gain for
small signals?
(A) VGS =- 6 Volts (B) VGS =- 3 Volts
(C) VGS = 0 Volts (D) VGS = 3 Volts

2006 TWO MARKS

Q. 53 For the circuit shown in the following figure, the capacitorC is initially uncharged.
At t = 0 the switch S is closed. The Vc across the capacitor at t = 1 millisecond is
In the figure shown above, the OP-AMP is supplied with !15V .

(A) 0 Volt (B) 6.3 Volt

(C) 9.45 Volts (D) 10 Volts

Q. 54 For the circuit shown below, assume that the zener diode is ideal with a breakdown
voltage of 6 volts. The waveform observed across R is
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Common Data For Q. 55 to 57

In the transistor amplifier circuit shown in the figure below, the transistor has
the following parameters:
bDC = 60, VBE = 0.7V,hie " 3
The capacitance CC can be assumed to be infinite.
In the figure above, the ground has been shown by the symbol 4

Q. 55 Under the DC conditions, the collector-or-emitter voltage drop is

(A) 4.8 Volts (B) 5.3 Volts
(C) 6.0 Volts (D) 6.6 Volts

Q. 56 If bDC is increased by 10%, the collector-to-emitter voltage drop

(A) increases by less than or equal to 10%
(B) decreases by less than or equal to 10%
(C) increase by more than 10%
(D) decreases by more than 10%
Q. 57 The small-signal gain of the amplifier vc is
vs
(A) -10 (B) -5.3
(C) 5.3 (D) 10

Common Data For Q. 58 and 59

A regulated power supply, shown in figure below, has an unregulated input (UR)
of 15 Volts and generates a regulated output Vout . Use the component values
shown in the figure.
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 58 The power dissipation across the transistor Q1 shown in the figure is

(A) 4.8 Watts (B) 5.0 Watts
(C) 5.4 Watts (D) 6.0 Watts

Q. 59 If the unregulated voltage increases by 20%, the power dissipation across the
transistor Q1
(A) increases by 20% (B) increases by 50%
(C) remains unchanged (D) decreases by 20%

2005 ONE MARK

Q. 60 The input resistance Ri of the amplifier shown in the figure is

30 kW (B) 10 kW
(A)
4
(C) 40 kW (D) infinite

Q. 61 The effect of current shunt feedback in an amplifier is to

(A) increase the input resistance and decrease the output resistance
(B) increases both input and output resistance
(C) decrease both input and output resistance
(D) decrease the input resistance and increase the output resistance

Q. 62 The cascade amplifier is a multistage configuration of

(A) CC - CB (B) CE - CB
(C) CB - CC (D) CE - CC

2005 TWO MARKS

Q. 63 In an ideal differential amplifier shown in the figure, a large value of( RE ).

(A) increase both the differential and common - mode gains.
(B) increases the common mode gain only.
(C) decreases the differential mode gain only.
(D) decreases the common mode gain only.
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 64 For an npn transistor connected as shown in figure VBE = 0.7 volts. Given that
reverse saturation current of the junction at room temperature 300 K is 10-13 A,
the emitter current is

(A) 30 mA (B) 39 mA
(C) 49 mA (D) 20 mA

Q. 65 The voltage e0 is indicated in the figure has been measured by an ideal voltmeter.
Which of the following can be calculated ?

(A) Bias current of the inverting input only

(B) Bias current of the inverting and non-inverting inputs only
(C) Input offset current only
(D) Both the bias currents and the input offset current

Q. 66 The Op-amp circuit shown in the figure is filter. The type of filter and its cut. Off
frequency are respectively

(A) high pass, 1000 rad / sec. (B) Low pass, 1000 rad / sec
(C) high pass, 1000 rad / sec (D) low pass, 10000 rad / sec

Q. 67 The circuit using a BJT with b = 50 and VBE = 0.7V is shown in the figure. The
base current IB and collector voltage by VC and respectively
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) 43 mA and 11.4 Volts (B) 40 mA and 16 Volts

(C) 45 mA and 11 Volts (D) 50 mA and 10 Volts

Q. 68 The Zener diode in the regulator circuit shown in the figure has a Zener voltage
of 5.8 volts and a zener knee current of 0.5 mA. The maximum load current
drawn from this current ensuring proper functioning over the input voltage range
between 20 and 30 volts, is

(A) 23.7 mA (B) 14.2 mA

(C) 13.7 mA (D) 24.2 mA

Q. 69 Both transistors T1 and T2 show in the figure, have a b = 100, threshold voltage of
1 Volts. The device parameters K1 and K2 of T1 and T2 are, respectively, 36 m A / V 2
and 9 mA / V 2 . The output voltage Vo i s

(A) 1 V (B) 2 V
(C) 3 V (D) 4 V

Common Data For Q. 70 to 72

Given, rd = 20kW, IDSS = 10 mA, Vp =- 8 V

Q. 70 Zi and Z0 of the circuit are respectively

(A) 2 MW and 2 kW (B) 2 MW and 20 kW
11
(C) infinity and 2 MW (D) infinity and 20 kW
11
Q. 71 ID and VDS under DC conditions are respectively
(A) 5.625 mA and 8.75 V (B) 1.875 mA and 5.00 V
(C) 4.500 mA and 11.00 V (D) 6.250 mA and 7.50 V
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 72 Transconductance in milli-Siemens (mS) and voltage gain of the amplifier are

respectively
(A) 1.875 mS and 3.41
(B) 1.875 ms and -3.41
(C) 3.3 mS and -6
(D) 3.3 mS and 6

Q. 73 Given the ideal operational amplifier circuit shown in the figure indicate the
correct transfer characteristics assuming ideal diodes with zero cut-in voltage.

2004 ONE MARK

Q. 74 An ideal op-amp is an ideal

(A) voltage controlled current source
(B) voltage controlled voltage source
(C) current controlled current source
(D) current controlled voltage source

Q. 75 Voltage series feedback (also called series-shunt feedback) results in

(A) increase in both input and output impedances
(B) decrease in both input and output impedances
(C) increase in input impedance and decrease in output impedance
(D) decrease in input impedance and increase in output impedance
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 76 The circuit in the figure is a

(A) low-pass filter (B) high-pass filter

(C) band-pass filter (D) band-reject filter

2004 TWO MARKS

Q. 77 A bipolar transistor is operating in the active region with a collector current of 1

mA. Assuming that the b of the transistor is 100 and the thermal voltage ( VT ) is
25 mV, the transconductance (gm) and the input resistance (rp) of the transistor
in the common emitter configuration, are
(A) gm = 25 mA / V and rp = 15.625 kW (B) gm = 40 mA / V and rp = 4.0 kW
(C) gm = 25 mA / V and rp = 2.5 k W (D) gm = 40 mA / V and rp = 2.5 kW

Q. 78 The value of C required for sinusoidal oscillations of frequency 1 kHz in the

circuit of the figure is

(A) 1 mF (B) 2p mF
2p
(C) 1 mF (D) 2p 6 mF
2p 6
Q. 79 In the op-amp circuit given in the figure, the load current iL is

(A) - Vs (B) Vs
R2 R2
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(C) - Vs (D) Vs
RL R1
Q. 80 In the voltage regulator shown in the figure, the load current can vary from 100
mA to 500 mA. Assuming that the Zener diode is ideal (i.e., the Zener knee
current is negligibly small and Zener resistance is zero in the breakdown region),
the value of R is

(A) 7 W (B) 70 W
70 W (D) 14 W
(C)
3
Q. 81 In a full-wave rectifier using two ideal diodes, Vdc and Vm are the dc and peak
values of the voltage respectively across a resistive load. If PIV is the peak inverse
voltage of the diode, then the appropriate relationships for this rectifier are
(A) Vdc = Vm , PIV = 2Vm (B) Idc = 2 Vm , PIV = 2Vm
p p
(C) Vdc = 2 Vm , PIV = Vm (D) Vdc Vm , PIV = Vm
p p
Q. 82 Assume that the b of transistor is extremely large and VBE = 0.7V,I C and VCE in
the circuit shown in the figure

(A) IC = 1 mA, VCE = 4.7 V (B) IC = 0.5 mA, VCE = 3.75 V

(C) IC = 1 mA, VCE = 2.5 V (D) IC = 0.5 mA, VCE = 3.9 V

2003 ONE MARK

Q. 83 Choose the correct match for input resistance of various amplifier configurations
shown below :
Configuration Input resistance
CB : Common Base LO : Low
CC : Common Collector MO : Moderate
CE : Common Emitter HI : High
(A) CB - LO, CC - MO, CE -HI
(B) CB - LO, CC - HI, CE -MO
(C) CB - MO, CC - HI, CE -LO
(D) CB - HI, CC -LO, CE -MO
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 84 The circuit shown in the figure is best described as a

(A) bridge rectifier (B) ring modulator

(C) frequency discriminator (D) voltage double

Q. 85 If the input to the ideal comparators shown in the figure is a sinusoidal signal of 8
V (peak to peak) without any DC component, then the output of the comparators
has a duty cycle of

(A) 1 / 2 (B) 1 / 3
(C) 1 / 6 (D) 1 / 2

Q. 86 If the differential voltage gain and the common mode voltage gain of a differential
amplifier are 48 dB and 2 dB respectively, then common mode rejection ratio is
(A) 23 dB (B) 25 dB
(C) 46 dB (D) 50 dB

Q. 87 Generally, the gain of a transistor amplifier falls at high frequencies due to the
(A) internal capacitances of the device
(B) coupling capacitor at the input
(C) skin effect
(D) coupling capacitor at the output

2003 TWO MARKS

Q. 88 An amplifier without feedback has a voltage gain of 50, input resistance of 1 k

W and output resistance of 2.5 kW. The input resistance of the current-shunt
negative feedback amplifier using the above amplifier with a feedback factor of
0.2, is
(A) 1 kW (B) 1 kW
11 5
(C) 5 kW (D) 11 kW

Q. 89 In the amplifier circuit shown in the figure, the values of R1 and R2 are such that
the transistor is operating at VCE = 3 V and IC = 1.5 mA when its b is 150. For
a transistor with b of 200, the operating point ( VCE , IC ) is
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) (2 V, 2 mA) (B) (3 V, 2 mA)

(C) (4 V, 2 mA) (D) (4 V, 1 mA)

Q. 90 The oscillator circuit shown in the figure has an ideal inverting amplifier. Its
frequency of oscillation (in Hz) is

(A) 1 (B) 1
(2p 6 RC) (2pRC)
(C) 1 (D) 6
( 6 RC) (2pRC)

Q. 91 The output voltage of the regulated power supply shown in the figure is

(A) 3 V (B) 6 V
(C) 9 V (D) 12 V

Q. 92 If the op-amp in the figure is ideal, the output voltageVout will be equal to

(A) 1 V (B) 6 V
(C) 14 V (D) 17 V

Q. 93 Three identical amplifiers with each one having a voltage gain of 50, input
resistance of 1 kW and output resistance of 250 W are cascaded. The opened
circuit voltages gain of the combined amplifier is
(A) 49 dB (B) 51 dB
(C) 98 dB (D) 102 dB
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 94 An ideal sawtooth voltages waveform of frequency of 500 Hz and amplitude 3 V

is generated by charging a capacitor of 2 m F in every cycle. The charging requires
(A) Constant voltage source of 3 V for 1 ms
(B) Constant voltage source of 3 V for 2 ms
(C) Constant voltage source of 1 mA for 1 ms
(D) Constant voltage source of 3 mA for 2 ms

2002 ONE MARK

Q. 95 In a negative feedback amplifier using voltage-series (i.e. voltage-sampling, series

mixing) feedback.
(A) Ri decreases and R0 decreases (B) Ri decreases and R0 increases
(C) Ri increases and R0 decreases (D) Ri increases and R0 increases
( Ri and R0 denote the input and output resistance respectively)

Q. 96 A 741-type opamp has a gain-bandwidth product of 1 MHz. A non-inverting

amplifier suing this opamp and having a voltage gain of 20 dB will exhibit a -3
dB bandwidth of
(A) 50 kHz (B) 100 kHz
(C) 1000 kHz (D) 1000 kHz
17 7.07
Q. 97 Three identical RC-coupled transistor amplifiers are cascaded. If each of the
amplifiers has a frequency response as shown in the figure, the overall frequency
response is as given in
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

2002 TWO MARKS

Q. 98 The circuit in the figure employs positive feedback and is intended to generate
V (f)
sinusoidal oscillation. If at a frequency f0, B (f) =3 f = 1 +0c, then to sustain
V0 (f) 6
oscillation at this frequency

(A) R2 = 5R 1 (B) R2 = 6R1

(C) R2 = R1 (D) R2 = R1
6 5

Q. 99 An amplifier using an opamp with a slew-rate SR = 1 V / m sec has a gain of 40

dB. If this amplifier has to faithfully amplify sinusoidal signals from dc to 20 kHz
without introducing any slew-rate induced distortion, then the input signal level
must not exceed.
(A) 795 mV (B) 395 mV
(C) 79.5 mV (D) 39.5 mV

Q. 100 A zener diode regulator in the figure is to be designed to meet the specifications:
IL = 10 mA V0 = 10 V and Vin varies from 30 V to 50 V. The zener diode has
Vz = 10 V and Izk (knee current) = 1 mA. For satisfactory operation

(A) R # 1800W (B) 2000W # R # 2200W

(C) 3700W # R # 4000W (D) R $ 4000W
v
Q. 101 The voltage gain Av = 0 of the JFET amplifier shown in the figure is IDSS = 10
vt
mA Vp =- 5 V(Assume C1, C 2 and Cs to be very large

(A) + 16 (B) -16

(C) + 8 (D) -6
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

2001 ONE MARK

Q. 102 The current gain of a BJT is

gm
(A) gm r0 (B)
r
gm
(C) gm rp (D)
rp
Q. 103 Thee ideal OP-AMP has the following characteristics.
(A) Ri = 3, A = 3, R 0 = 0
(B) Ri = 0, A = 3, R 0 = 0
(C) Ri = 3,
A = 3, R 0 = 3
(D) Ri = 0,
A = 3, R 0 = 3

Q. 104 Consider the following two statements :

Statement 1 :
A stable multi vibrator can be used for generating square wave.
Statement 2:
Bistable multi vibrator can be used for storing binary information.
(A) Only statement 1 is correct
(B) Only statement 2 is correct
(C) Both the statements 1 and 2 are correct
(D) Both the statements 1 and 2 are incorrect

2001 TWO MARKS

Q. 105 An npn BJT has gm = 38 mA / V, C m = 10 -14 F, C p = 4 # 10 -13 F, and DC current

gain b0 = 90. For this transistor fT and fb are
(A) fT = 1.64 # 108 Hz and fb = 1.47 # 1010 Hz
(B) fT = 1.47 # 1010 Hz and fb = 1.64 # 108 Hz
(C) fT = 1.33 # 1012 Hz and fb = 1.47 # 1010 Hz
(D) fT = 1.47 # 1010 Hz and fb = 1.33 # 1012 Hz
Q. 106 The transistor shunt regulator shown in the figure has a regulated output voltage
of 10 V, when the input varies from 20 V to 30 V. The relevant parameters for
the zener diode and the transistor are : Vz = 9.5, VBE = 0.3 V, b = 99, Neglect the
current through R B . Then the maximum power dissipated in the zener diode (Pz )
and the transistor (PT ) are

(A) Pz = 75 mW, PT = 7.9 W

(B) Pz = 85 mW, PT = 8.9 W
(C) Pz = 95 mW, PT = 9.9 W
(D) Pz = 115 mW, PT = 11.9 W
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 107 The oscillator circuit shown in the figure is

(A) Hartely oscillator with foscillation = 79.6 MHz

(B) Colpitts oscillator with foscillation = 50.3 MHz
(C) Hartley oscillator with foscillation = 159.2 MHz
(D) Colpitts oscillator with foscillation = 159.3 MHz

Q. 108 The inverting OP-AMP shown in the figure has an open-loop gain of 100.

The closed-loop gain V0 is

Vs
(A) -8 (B) -9
(C) -10 (D) -11

Q. 109 In the figure assume the OP-AMPs to be ideal. The output v0 of the circuit is

t
(A) 10 cos (100t) (B) 10 #0 cos (100T) dT
#
t
(C) 10-4 T ) dT (D) 10-4 d cos (100t)
cos (100
0 dt

2000 ONE MARK

Q. 110 Introducing a resistor in the emitter of a common amplifier stabilizes the dc

operating point against variations in
(A) only the temperature (B) only the b of the transistor
(C) both temperature and b (D) none of the above

Q. 111 In the differential amplifier of the figure, if the source resistance of the current
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

source IEE is infinite, then the common-mode gain is

(A) zero (B) infinite

V + Vin2
(C) indeterminate (D) in1
2VT
Q. 112 In the circuit of the figure, V0 is

(A) -1 V (B) 2 V
(C) + 1 V (D) + 15 V

Q. 113 The current gain of a bipolar transistor drops at high frequencies because of
(A) transistor capacitances (B) high current effects in the base
(C) parasitic inductive elements (D) the Early effect

Q. 114 If the op-amp in the figure, is ideal, then v0 is

(A) zero (B) ( V1 - V2) sin wt

(C) - ( V1 + V2) sin wt (D) ( V1 + V2) sin wt

Q. 115 The configuration of the figure is a

GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) precision integrator (B) Hartely oscillator

(C) Butterworth high pass filter (D) Wien-bridge oscillator

Q. 116 Assume that the op-amp of the figure is ideal. If vi is a triangular wave, then v0
will be

(A) square wave (B) triangular wave

(C) parabolic wave (D) sine wave

Q. 117 The most commonly used amplifier is sample and hold circuits is
(A) a unity gain inverting amplifier
(B) a unity gain non-inverting amplifier
(C) an inverting amplifier with a gain of 10
(D) an inverting amplifier with a gain of 100

2000 TWO MARKS

Q. 118 In the circuit of figure, assume that the transistor is in the active region. It has a
large b and its base-emitter voltage is 0.7 V. The value of Ic is

(A) Indeterminate since Rc is not given (B) 1 mA

(C) 5 mA (D) 10 mA

Q. 119 If the op-amp in the figure has an input offset voltage of 5 mV and an open-loop
voltage gain of 10000, then v0 will be

(A) 0 V (B) 5 mV
(C) + 15 V or -15 V (D) + 50 V or -50 V
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

1999 ONE MARK

Q. 120 The first dominant pole encountered in the frequency response of a compensated op-
amp is approximately at
(A) 5 Hz (B) 10 kHz
(C) 1 MHz (D) 100 MHz

Q. 121 Negative feedback in an amplifier

(A) reduces gain
(B) increases frequency and phase distortions
(C) reduces bandwidth
(D) increases noise

Q. 122 In the cascade amplifier shown in the given figure, if the common-emitter
stage (Q1) has a transconductance gm1, and the common base stage (Q2) has
a transconductance gm2, then the overall transconductance g (= i0 / vi) of the
cascade amplifier is

(A) g m1 (B) g m2
g g
(C) m1 (D) m2
2 2
Q. 123 Crossover distortion behavior is characteristic of
(A) Class A output stage (B) Class B output stage
(C) Class AB output stage (D) Common-base output stage

1999 TWO MARK

Q. 124 An amplifier has an open-loop gain of 100, an input impedance of 1 kW,and an

output impedance of 100 W. A feedback network with a feedback factor of 0.99 is
connected to the amplifier in a voltage series feedback mode. The new input and
output impedances, respectively, are
(A) 10 W and 1W (B) 10 W and 10 k W
(C) 100 kW and 1 W (D) 100 kW and 1 k W

Q. 125 A dc power supply has a no-load voltage of 30 V, and a full-load voltage of

25 V at a full-load current of 1 A. Its output resistance and load regulation,
respectively, are
(A) 5 W and 20% (B) 25 W and 20%
(C) 5 W and 16.7% (D) 25 W and 16.7%

1998 ONE MARK

Q. 126 The circuit of the figure is an example of feedback of the following type
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) current series (B) current shunt

(C) voltage series (D) voltage shunt

Q. 127 In a differential amplifier, CMRR can be improved by using an increased

(A) emitter resistance (B) collector resistance
(C) power supply voltages (D) source resistance

Q. 128 From a measurement of the rise time of the output pulse of an amplifier whose is
a small amplitude square wave, one can estimate the following parameter of the
amplifier
(A) gain-bandwidth product (B) slow rate
(C) upper 3–dB frequency (D) lower 3–dB frequency

Q. 129 The emitter coupled pair of BJT’s given a linear transfer relation between the
differential output voltage and the differential output voltage and the differential
input voltage Vid is less a times the thermal voltage, where a is
(A) 4 (B) 3
(C) 2 (D) 1

Q. 130 In a shunt-shunt negative feedback amplifier, as compared to the basic amplifier

(A) both, input and output impedances,decrease
(B) input impedance decreases but output impedance increases
(C) input impedance increase but output
(D) both input and output impedances increases.

1998 TWO MARKS

Q. 131 A multistage amplifier has a low-pass response with three real poles at s =-w1
- w2 and w3 . The approximate overall bandwidth B of the amplifier will be
given by
(A) B = w1 + w2 + w3 (B) 1 = 1 + 1 + 1
B w1 w2 w3
(C) B = (w1 + w2 + w 3) 1/3 (D) B = w2 + w2 + w2
1 2 3

Q. 132 One input terminal of high gain comparator circuit is connected to ground and a
sinusoidal voltage is applied to the other input. The output of comparator will be
(A) a sinusoid (B) a full rectified sinusoid
(C) a half rectified sinusoid (D) a square wave

Q. 133 In a series regulated power supply circuit, the voltage gain A v of the ‘pass’
transistor satisfies the condition
(A) Av " 3 (B) 1 << A v < 3
(C) A v . 1 (D) A v << 1
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Q. 134 For full wave rectification, a four diode bridge rectifier is claimed to have the
following advantages over a two diode circuit :
(A) less expensive transformer,
(B) smaller size transformer, and
(C) suitability for higher voltage application.
Of these,
(A) only (1) and (2) are true (B) only (1) and (3) are true
(C) only (2) and (3) are true (D) (1), (2) as well as (3) are true

Q. 135 In the MOSFET amplifier of the figure is the signal output V1 and V2 obey the
relationship

(A) V1 = V2 (B) V1 =-V2

2 2
(C) V1 = 2V2 (D) V1 =- 2V2

Q. 136 For small signal ac operation, a practical forward biased diode can be modelled as
(A) a resistance and a capacitance in series
(B) an ideal diode and resistance in parallel
(C) a resistance and an ideal diode in series
(D) a resistance

1997 ONE MARK

Q. 137 In the BJT amplifier shown in the figure is the transistor is based in the forward
active region. Putting a capacitor across R E will

(A) decrease the voltage gain and decrease the input impedance
(B) increase the voltage gain and decrease the input impedance
(C) decrease the voltage gain and increase the input impedance
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(D) increase the voltage gain and increase the input impedance

Q. 138 A cascade amplifier stags is equivalent to

(A) a common emitter stage followed by a common base stage
(B) a common base stage followed by an emitter follower
(C) an emitter follower stage followed by a common base stage
(D) a common base stage followed by a common emitter stage

Q. 139 In a common emitter BJT amplifier, the maximum usable supply voltage is
limited by
(A) Avalanche breakdown of Base-Emitter junction
(B) Collector-Base breakdown voltage with emitter open (BV CBO )
(C) Collector-Emitter breakdown voltage with base open (BV CBO )
(D) Zener breakdown voltage of the Emitter-Base junction

1997 TWO MARKS

Q. 140 In the circuit of in the figure is the current iD through the ideal diode (zero cut
in voltage and forward resistance) equals

(A) 0 A (B) 4 A
(C) 1 A (D) None of the above

Q. 141 The output voltage V0 of the circuit shown in the figure is

(A) -4 V (B) 6 V
(C) 5 V (D) -5.5 V

Q. 142 A half wave rectifier uses a diode with a forward resistance Rf . The voltage is
Vm sin wt and the load resistance is RL . The DC current is given by
(A) Vm (B) Vm
2 RL p ( R f + RL)
(C) 2Vm (D) Vm
p RL
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

1996 ONE MARK

Q. 143 In the circuit of the given figure, assume that the diodes are ideal and the meter
is an average indicating ammeter. The ammeter will read

(A) 0.4 2 A (B) 0.4 A

0.8
(C) A (D) 0.4 mamp
p p
Q. 144 The circuit shown in the figure is that of

(A) a non-inverting amplifier (B) an inverting amplifier

(C) an oscillator (D) a Schmitt trigger

1996 TWO MARKS

Q. 145 In the circuit shown in the given figure N is a finite gain amplifier with a gain
of k , a very large input impedance, and a very low output impedance. The input
impedance of the feedback amplifier with the feedback impedance Z connected
as shown will be

(A) Zb1 - 1 l (B) Z (1 - k)

k
Z Z
(C) (D)
(k - 1) (1 - k)
Q. 146 A Darlington stage is shown in the figure. If the transconductance ofQ1 is gm1 and
ic
Q2 is gm2, then the overall transconductance gmc ;T c E is given by
v bec
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

(A) g m1 (B) 0.5 g m1

(C) g m2 (D) 0.5 g m2

Q. 147 Value of R in the oscillator circuit shown in the given figure, so chosen that it just
oscillates at an angular frequency of w. The value of w and the required value of
R will respectively be

(A) 105 rad / sec, 2 #10 4 W (B) 2 # 104 rad / sec, 2 # 104 W
(C) 2 # 104 rad / sec, 10 5 W (D) 105 rad / sec, 10 5 W

Q. 148 A zener diode in the circuit shown in the figure is has a knee current of5 mA,
and a maximum allowed power dissipation of 300 mW . What are the minimum
and maximum load currents that can be drawn safely from the circuit, keeping
the output voltage V0 constant at 6 V?

(A) 0 mA, 180 mA (B) 5 mA, 110 mA

(C) 10 mA, 55 mA (D) 60 mA, 180 mA

***********
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

SOLUTIONS

Sol. 1 Option (B) is correct.

For the given ideal op-amp, negative terminal will be also ground (at zero voltage)
and so, the collector terminal of the BJT will be at zero voltage.
i.e., VC = 0 volt
The current in 1 kW resistor is given by
I = 5 - 0 = 5 mA
1 kW
This current will flow completely through the BJT since, no current will flow
into the ideal op-amp (I / P resistance of ideal op-amp is infinity). So, for BJT
we have
VC = 0
VB = 0
IC = 5 mA
i.e.,the base collector junction is reverse biased (zero voltage) therefore, the
collector current ( IC ) can have a value only if base-emitter is forward biased.
Hence,
VBE = 0.7 volts
& VB - VE = 0.7
& 0 - Vout = 0.7
or, Vout =- 0.7 volt
Sol. 2 Option (A) is correct.
The i / p voltage of the system is given as
Vin = V1 + Vf = V1 + k Vout
= V1 + k A 0 V 1 ^Vout = A 0 V1h
= V1 ^1 + k A 0h
Therefore, if k is increased then input voltage is also increased so, the input
impedance increases. Now, we have Vin A 0 Vin
Vout = A 0 V 1 = A 0 =
^1 + k A 0h ^1 + k A 0h
Since, Vin is independent of k when seen from output mode, the output voltage
decreases with increase in k that leads to the decrease of output impedance.
Thus, input impedance increases and output impedance decreases.
Sol. 3 Option (A) is correct.
For the given circuit, we obtain the small signal model as shown in figure below :
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

We obtain the node voltage at V1 as

V1 + V1 + g V = 0
m i
RD 1
RL +
sC
- g m Vi
& V1 = 1
1
RD + R + 1
sC
Therefore, the output voltage V0 is obtained as L
RL J -g m Vi N
V0 = V1 R L1 = 1 K1 1 O
RL + RL + +
sC sC K RD 1O
K R L+ O
L sC
P
so, the transfer function is
V0 = - R D R L sCg m
Vi 1 + sC ^R D + R L h
Then, we have the pole at w = 1
C^RD + R Lh
It gives the lower cutoff frequency of transfer function.
i.e., w0 = 1
C^RD + R Lh 1
or, f0 = 1 +R = p -6 3
2p C ^R D Lh 2 # 10 # 20 # 10
= 7.97 . 8 Hz
Sol. 4 Option (B) is correct.

From the circuit, we have

Is = IZ + IL
or, IZ = Is - IL (1)
Since, voltage across zener diode is 5 V so, current through 100 W resistor is
obtained as
Is = 10 - 5 = 0.05 A
100
Therefore, the load current is given by
IL = 5
RL
Since, for proper operation, we must have
IZ $ Iknes
So, from Eq. (1), we write
0.05 A - 5 $ 10 mA
RL
50 mA - 5 $ 10 mA
RL
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

40 mA $ 5
RL
40 # 10 $ 5
- 3
RL
1 # LR
40 # 10-3 5
5
-3 # R L
40 # 10
or, 125 W # R L
Therefore, minimum value of RL = 125 W
Now, we know that power rating of Zener diode is given by
PR = VZ IZ^maxh
IZ^maxh is maximum current through zener diode in reverse bias. Maximum
currrent through zener diode flows when load current is zero. i.e.,
IZ^maxh = Is = 10 - 5 = 0.05
100
Therefore, PR = 5 # 0.05 W = 250 mW
Sol. 5 Option (C) is correct.

For the given ideal op-Amps we can assume

V - = V + = V (ideal)
2 2 2
V + = V - = V (ideal)
1 1 1
So, by voltage division
V1 = Vout # 1
2
Vout = 2V1
and, as the I / P current in Op-amp is always zero therefore, there will be no voltage
drop across 1 KW in II op-amp
i.e., V2 = 1 V
Therefore,
V1 - V2 V - ^-2h
= 2
1 1
& V1 - 1 = 1 + 2
or, V1 = 4
Hence, Vout = 2V1 = 8 volt
Sol. 6 Option (B) is correct.
For the given circuit, we can make the truth table as below
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

X Y Z
0 0 0
0 1 1
1 0 0
1 1 0
Logic 0 means voltage is v = 0 volt and logic 1 means voltage is 5 volt
For x = 0, y = 0, Transistor is at cut off mode and diode is forward biased. Since, there
is no drop across forward biased diode.
So, Z= Y=0
For x = 0, y = 1, Again Transistor is in cutoff mode, and diode is forward biased. with
no current flowing through resistor.
So, Z= Y=1
For x = 1, y = 0, Transistor is in saturation mode and so, z directly connected to
ground irrespective of any value of Y .
i.e., Z = 0 (ground)
Similarly for X = Y = 1
Z = 0 (ground)
Hence, from the obtained truth table, we get
Z=XY
Sol. 7 Option (D) is correct.
Given, the input voltage
VYZ = 100 sin wt

For + ve half cycle

VYZ > 0
i.e., VY is a higher voltage than VZ
So, the diode will be in cutoff region. Therefore, there will no voltage difference
between X and W node.
i.e., VWX = 0
Now, for - ve half cycle all the four diodes will active and so, X and W
terminal is short circuited
i.e., VWX = 0
Hence, VWX = 0 for all t
Sol. 8 Option (C) is correct.
The equivalent circuit can be shown as
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

R2 3R2
VTh = VCC =
R1 + R2 R1 + R 2
and RTh = R 2 R 1
R2+ R 1
Since, IC = bIB has b . 3 (very high) so, IB is negative in comparison to IC .
Therefore, we can write the base voltage
VB = VTh
So, VTh - 0.7 - IC R E = 0
3R 2
or, - 0.7 - ^10-3h^500h = 0
R1 + R 2
3R 2 = 0.7 + 0.5
or,
60 kW+ R 2
or, 3R 2 = ^60 kWh^1.2h + 1.2R 2

or, 1.8R 2 = ^60 kWh # ^1.2h

Hence, R 2 = 60 # 1.2 = 40 kW
1.8
Sol. 9 Option (D) is correct.
Let v > 0.7 V and diode is forward biased. By applying Kirchoff’s voltage law
10 - i # 1k - v = 0

10 - :v - 0.7 D (1000) - v = 0
500
10 - (v - 0.7) # 2 - v = 0
10 - 3v + 1.4 = 0
v = 11.4 = 3.8 V > 0. 7 (Assumption is true)
3
So, i = v - 0.7 = 3.8 - 0.7 = 6.2 mA
500 500
Sol. 10 Option (C) is correct.
Given ib = 1 + 0.1 cos (1000pt) mA
So, I B = DC component of ib
= 1 mA
In small signal model of the transistor
bVT
rp = VT " Thermal voltage
IC
IC = I
= T = VT = VT
V B
IC / b IB IB b
rp= 25 mV = 25 W
So, VT = 25 mV, IB = 1 mA
1 mA
Sol. 11 Option (A) is correct.
The circuit composed of a clamper and a peak rectifier as shown.
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Clamper clamps the voltage to zero voltage, as shown

The peak rectifier adds +1 V to peak voltage, so overall peak voltage lowers down by
-1 volt.
So, vo = cos wt - 1

Sol. 12 Option (A) is correct.

We put a test source between terminal 1, 2 to obtain equivalent impedance

ZTh = Vtest
I test
Applying KCL at top right node
Vtest + Vtest - 99I = I
b test
9k + 1k 100
Vtest + Vtest - 99I = I ...(i)
b test
10k 100
But Ib =- Vtest =-Vtest
9k + 1k 10k
Substituting Ib into equation (i), we have
Vtest + Vtest + 99Vtest = I
test
10k 100 10k
100Vtest + Vtest = I
3 test
10 # 10 100
2Vtest = I
test
100
ZTh = Vtest = 50 W
I test
Sol. 13 Option (B) is correct.
First we obtain the transfer function.
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

0 - Vi (jw) 0 - Vo (jw)
1 + =0
+ R1 R2
jwC
Vo (jw) - Vi (jw)
R2 = 1
+ R1
jwC
Vi (jw) R 2
Vo (jw) =-
R1 - j 1
wC
At w " 0 (Low frequencies), 1
wC" 3, so Vo = 0
At w " 3 (higher frequencies)
1 " 0, so V (jw) =- R 2 V (jw)
o i
wC R1
The filter passes high frequencies so it is a high pass filter.
H (jw) = Vo = - R2
Vi R1 - j 1
wC
- R R
H (3) = R 1 = R 1
2 2

At 3 dB frequency, gain will be 2 times of maximum gain H6(3) @

H^jw0h = 1 H (3)
2
So, R2 = b R2 l
1
R 12 + w01
2
C2 2 R1
2R 2 = R 2 + 1
w02 C 2
1 1

R12 = 1
w 2C 2
w0 = 1
R1C
Sol. 14 Option (D) is correct.
DC Analysis :

Using KVL in input loop,

GATE SOLVED PAPER - EC ANALOG ELECTRONIC

VC - 100IB - 0.7 = 0
VC = 100IB + 0.7 ...(i)
IC - IE = 13.7 - VC = (b + 1) IB
12k
13.7 - VC = 100I
B ...(ii)
12 # 103
Solving equation (i) and (ii),
IB = 0.01 mA
Small Signal Analysis :
Transforming given input voltage source into equivalent current source.

This is a shunt-shunt feedback amplifier.

Given parameters,
rp = VT = 25 mV = 2.5 kW
IB 0.01 mA
b 100
gm = = = 0.04 s
rp 2.5 # 1000
Writing KCL at output node
v0 + g v + v0 - v p = 0
m p
RC RF
v0 : 1 + 1 D + vp :gm - 1 D = 0
R R R
Substituting RC = 12 kW, RF = 100 kW,
C F F gm = 0.04 s

v 0 (9.33 # 10-5) + v p (0.04) = 0

v0 =- 428.72Vp ...(i)
Writing KCL at input node
v i = v p + v p + v p - vo
Rs R s rp RF
vi = v 1 + 1 + 1 - v0
p:
R R r RD R
v
s i = v p (5.1
v
#p10- F) - 0 F
4
s
Rs RF
Substituting Vp from equation (i)

v i = -5.1 # 10-4 v0 - v 0
Rs 428.72 RF
vi =- 1.16 # 10-6 v 0 - 1 # 10-5 v0
3
Rs = 10 kW (source resistance)
10 # 10
vi =- 1.116 # 10-5
3
10 # 10
1
Av = v0 = - 8.96
vi 10 # 10 # 1.116 # 10-5
3

Sol. 15 Option (A) is correct.

 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

For the parallel RLC circuit resonance frequency is,

wr = 1 = 1 = 10 M rad /s
LC 10 # 10 # 1 # 10-9
- 6

Thus given frequency is resonance frequency and parallel RLC circuit has
maximum impedance at resonance frequency
Gain of the amplifier is gm # (ZC RL) where ZC is impedance of parallel RLC
circuit.
At w = wr , ZC = R = 2 kW = ZCmax .
Hence at this frequency (wr), gain is
Gain w = wr
= gm (ZC R L ) = g m (2k 2k) = gm # 103 which is maximum.
Therefore gain is maximum at wr = 10 M rad / sec .

Sol. 16 Option (D) is correct.

The given circuit is shown below :

From diagram we can write

Ii = Vo + Vo
R 1 sL 1
Transfer function
H (s) = Vo = sR1L 1
I1 R1 + sL 1
jwR1L 1
or H (jw) =
R 1+ jwL 1
At w = 0 H (jw) = 0
At w = 3 H (jw) = R 1 = constan t . Hence HPF.

Sol. 17 Option (C) is correct.

Given circuit is shown below.

For transistor M2,

VGS = VG - VS = Vx - 0 = V x
VDS = VD - VS = Vx - 0 = V x
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Since VGS - VT = Vx - 1 < VDS , thus M 2 is in saturation.

By assuming M1 to be in saturation we have
IDS (M ) = IDS (M )
mn C0x m C
1 2

(4) (5 - Vx - 1) 2 = n 0x 1 ( Vx - 1) 2

2 2
4 (4 - Vx) 2 = ( Vx - 1) 2

or 2 (4 - Vx ) =! ( Vx - 1)
Taking positive root, 8 - 2Vx = Vx - 1
Vx = 3 V
At Vx = 3 V for M1, VGS = 5 - 3 = 2 V < VDS . Thus our assumption is true and
Vx = 3 V.
Sol. 18 Option (D) is correct.
We have a = 0.98
Now b = 1 a = 4.9
-a
In active region, for common emitter amplifier,
IC = bI B + (1 + b) ICO ...(1)
Substituting ICO = 0.6 mA and IB = 20 mA in above eq we have,
IC = 1.01 mA
Sol. 19 Option (C) is correct.
In active region VBEon = 0.7 V
Emitter voltage VE = VB - VBEon =- 5.7 V
Emitter Current IE = V E - (- 10) = -5.7 - (- 10) = 1 mA
4.3k 4.3k
Now IC . IE = 1 mA
Applying KCL at collector
i1 = 0.5 mA
Since i1 = C dV C
dt
1 i dt = i1 t
or VC = # 1 ...(1)
C C

with time, the capacitor charges and voltage across collector changes from 0 towards
negative.

When saturation starts, VCE = 0.7 & VC =+ 5 V (across capacitor)

 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Thus from (1) we get, + 5 = 0.5 mA T

5 mA
-6
or T = 5 # 5 # 10 3 = 50 m sec
0.5 # 10-
Sol. 20 Option (A) is correct.
The current flows in the circuit if all the diodes are forward biased. In forward
biased there will be 0.7 V drop across each diode.
12.7 - 4 (0.7)
Thus IDC = = 1 mA
9900
Sol. 21 Option (B) is correct.
The forward resistance of each diode is
r = VT = 25 mV = 25 W
IC 1 mA
4 (r)
Thus Vac = Vi # e o
4 (r) + 9900
= 100 mV cos (wt) 0.01
= 1 cos (wt) mV

Sol. 22 Option (A) is correct.

The equivalent circuit of given amplifier circuit (when CE is connected, RE is short-
circuited)

Input impedance R i = R B || r p
Voltage gain AV = g m R C
Now, if CE is disconnected, resistance RE appears in the circuit

Input impedance R in = R B || [ rp + ( b + 1)] R E

Input impedance increases
gm RC
Voltage gain AV = Voltage gain decreases.
1 + gm RE
Sol. 23 Option (B) is correct.
Since, emitter area of transistor Q1 is half of transistor Q2, so current
I E = 1 I E and I B = 1 I B
1
2 2 1
2 2

The circuit is as shown below :

GATE SOLVED PAPER - EC ANALOG ELECTRONIC

V B =- 10 - (- 0.7) =- 9.3 V
0 - (- 9.3)
Collector current I1 = = 1 mA
(9.3 kW)
b 1 = 700 (high), So IC . IE 1

Applying KCL at base we have

1 - IE = I B + I B
1 2

1 - (b 1 + 1) I B = I B + I B
1 1 2

IB
1 = (700 + 1 + 1) 2
+ IB
2 2

IB . 2
2
702
I0 = IC = b 2 : I B = 715 # 2 . 2 mA
2 2
702
Sol. 24 Option (A) is correct.
The circuit is as shown below :

So, 0 - Vi + 0 - Vo = 0
R1 R2
or Vo =- R 2
Vi R1
Sol. 25 Option (B) is correct.
By small signal equivalent circuit analysis

Input resistance seen by source vs

R in = vs = Rs + Rs || rs = (1000 W) + (93 kW | | 259 W) = 1258 W
is
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 26 Option (B) is correct.

Cut-off frequency due to C2
1
fo =
2p ( R C + R L) C 2
= 1 -6 = 271 Hz
2 # 3.14 # 1250 # 4.7 # 10
f
Lower cut-off frequency fL . o = 271 = 27.1 Hz
10 10
Sol. 27 Option (B) is correct.
The circuit is as shown below

Current I = 20 - 0 + Vi - 0 = 5 + Vi
4R R R
If I > 0, diode D2 conducts
So, for 5 + VI > 0 & VI > - 5, D2 conducts
2
Equivalent circuit is shown below

Output is Vo = 0. If I < 0, diode D2 will be off

5 + VI < 0 & V < - 5, D is off
I 2
R
The circuit is shown below

0 - Vi + 0 - 20 + 0 - Vo = 0
R 4R R
or Vo =- Vi - 5

At Vi =- 5 V, Vo = 0
At Vi =- 10 V, Vo = 5 V
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 28 Option (A) is correct.

Let diode be OFF. In this case 1 A current will flow in resistor and voltage across
resistor will be V = 1.V
Diode is off, it must be in reverse biased, therefore
Vi - 1 > 0 " Vi > 1
Thus for Vi > 1 diode is off and V = 1V
Option (B) and (C) doesn’t satisfy this condition.
Let Vi < 1. In this case diode will be on and voltage across diode will be zero and
V = Vi
Thus V = min ( Vi, 1)
Sol. 29 Option (A) is correct.
The R2 decide only the frequency.
Sol. 30 Option (D) is correct.
For small increase in VG beyond 1 V the n - channel MOSFET goes into saturation
as VGS "+ ive and p - MOSFET is always in active region or triode region.
Sol. 31 Option (C) is correct.
Sol. 32 Option (D) is correct.
The circuit is shown in fig below

The voltage at non inverting terminal is 5 V because OP AMP is ideal and

inverting terminal is at 5 V.
10 - 5 = 1 mA
Thus IC =
5k
VE = IE RE = 1m # 1.4k = 1.4V IE = IC
= 0.6 + 1.4 = 2V
Thus the feedback is negative and output voltage is V = 2V .
Sol. 33 Option (D) is correct.
The output voltage is
hfe RC
V0 = Ar Vi .- V
hie i
Here RC = 3 W and hie = 3 kW
Thus V0 .- 150 # 3k Vi
3k
.- 150 ( A cos 20t + B sin 106t )
Since coupling capacitor is large so low frequency signal will be filtered out, and best
approximation is
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

V0 .- 150B sin 106 t

Sol. 34 Option (C) is correct.
For the positive half of Vi , the diode D1 is forward bias, D2 is reverse bias and the
zener diode is in breakdown state because Vi > 6.8.
Thus output voltage is
V0 = 0.7 + 6.8 = 7.5 V
For the negative half of Vi, D2 is forward bias thus
Then V0 =- 0.7 V
Sol. 35 Option (B) is correct.
By Current mirror,
W
^ Lh 2
Ix = Ibias
^ WL h1
Since MOSFETs are identical,
W W
Thus b L l = bL l
2 2

Hence Ix = Ibias
Sol. 36 Option (B) is correct.
The circuit is using ideal OPAMP. The non inverting terminal of OPAMP is at
ground, thus inverting terminal is also at virtual ground.

Thus current will flow from -ive terminal (0 Volt) to -1 Volt source. Thus the current I
is
0 - (- 1)
I = = 1
100k 100k
The current through diode is
V
I _ V 0 i= I e
t

Now VT = 25 mV and I0 = 1 mA-1

1
I = 10-6 8e 25 # 10 - 1B = 5
V -3
Thus
10
or V = 0.06 V
Now V0 = I # 4k + V = 1 # 4k + 0.06 = 0.1 V
100k
Sol. 37 Option (B) is correct.
The circuit is using ideal OPAMP. The non inverting terminal of OPAMP is at
ground, thus inverting terminal is also at virtual ground.
Thus we can write
vi = -v
R1 + sL R
sR C + 1
2

2 2

v0 R2
or =-
vi ( R1 + sL)( sR 2C 2 + 1)
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

and from this equation it may be easily seen that this is the standard form of
T.F. of low pass filter
H (s) = K
( R1 + sL)( sR 2C 2 + 1)
and form this equation it may be easily seen that this is the standard form of
T.F. of low pass filter
H (s) = K
as + bs + b
2

Sol. 38 Option (C ) is correct.

The current in both transistor are equal. Thus gm is decide by M1.
Sol. 39 Option (C) is correct.
Let the voltage at non inverting terminal be V1, then after applying KCL at non
inverting terminal side we have
15 - V1 + V0 - V1 = V1 - (- 15)
10 10 10
V0
or V1 =
3
If V0 swings from -15 to + 15 V thenV1 swings between -5 V to + 5 V.
Sol. 40 Option (A) is correct.
For the given DC values the Thevenin equivalent circuit is as follows

The Thevenin resistance and voltage are

10
VTH = #9=3 V
10 + 20
and total RTH = 10k # 20k = 6.67 kW
10k + 20k
Since b is very large, therefore IB is small and can be ignored
Thus IE = VTH - VBE = 3 - 0.7 = 1 mA
RE 2.3k
Sol. 41 Option (D) is correct.
The small signal model is shown in fig below
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

IC
g= = 1m = 1 A/V I .I
m C E
VT 25m 25
Vo =- gm Vp # (3k 3k )
=- 1 Vin (1.5k) Vp = Vin
25
=- 60Vin
or Am = Vo =- 60
Vin
Sol. 42 Option (C) is correct.
The circuit shown in (C) is correct full wave rectifier circuit.

Sol. 43 Option (A) is correct.

In the transconductance amplifier it is desirable to have large input resistance
and large output resistance.
Sol. 44 Option (C) is correct.
We redraw the circuit as shown in fig.

Applying voltage division rule

v+ = 0.5 V
We know that v+ = v-
Thus v- = 0.5 V
Now i = 1 - 0.5 = 0.5 mA
1k
0.5 - v0
and i= = 0.5 mA
2k
or v0 = 0.5 - 1 =- 0.5 V
Sol. 45 Option (B) is correct.
If we assume b very large, then IB = 0 and IE = IC ; VBE = 0.7 V. We assume that
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

BJT is in active, so applying KVL in Base-emitter loop

IE = 2 - VBE = 2 - 0.7 = 1.3 mA
RE 1k
Since b is very large, we have IE = IC , thus
IC = 1.3 mA
Now applying KVL in collector-emitter loop
10 - 10IC - VCE - IC = 0
or VCE =- 4.3 V
Now VBC = VBE - VCE
= 0.7 - (- 4.3) = 5 V
Since VBC > 0.7 V, thus transistor in saturation.
Sol. 46 Option (D) is correct.
Here the inverting terminal is at virtual ground and the current in resistor and diode
current is equal i.e.
IR = ID
or Vi = I eV / V
D T
s
R
or VD = VT 1n Vi
Is R
For the first condition
VD = 0 - Vo1 = VT 1n 2
Is R
For the first condition
VD = 0 - Vo1 = VT 1n 4
Is R
Subtracting above equation
Vo1 - Vo2 = VT 1n 4 - VT 1n 2
Is R Is R
or Vo1 - Vo2 = VT 1n 4 = VT 1n2
2
Sol. 47 Option (D) is correct.
We have Vthp = Vthp = 1 V
WP WN 40mA / V2
and = =
LP LN
From figure it may be easily seen that Vas for each NMOS and PMOS is 2.5 V
mA
Thus ID = K ( Vas - VT ) 2 = 40 2 (2.5 - 1) 2 = 90 m A
V
Sol. 48 Option (C) is correct.
We have VZ = 7 volt, VK = 0, RZ = 10W
Circuit can be modeled as shown in fig below
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Since Vi is lies between 10 to 16 V, the range of voltage across 200 kW

V200 = Vi - VZ = 3 to 9 volt
The range of current through 200 kW is
3 = 15 mA to 9 = 45 mA
200k 200k
The range of variation in output voltage
15m # RZ = 0.15 V to 45m # RZ = 0.45
Thus the range of output voltage is 7.15 Volt to 7.45 Volt
Sol. 49 Option (A) is correct.
The voltage at non-inverting terminal is
V = V =
1
sC 1 V
+
R + sC 1 i 1 + sCR i
Now V- = V+ = 1 V
1 + sCR i
Applying voltage division rule
V+ = R1 ( V + V ) = ( Vo + Vi)
0 i
R1 + R1 2
o + Vi)
or 1 Vi = ( V
1 + sCR 2
or V o
=- 1 + 2
Vi 1 + sRC
V0 = 1 - sRC
Vi 1 + sRC
Sol. 50 Option (C) is correct.
= H (s) = 1 - sRC
V0
Vi 1 + sRC
1 - jwRC
H (jw) =
1 + jwRC
+H (jw) = f =- tan -1 wRC - tan -1
wRC
=- 2 tan wRC -2

Minimum value, fmin = -p (at w " 3)

Maximum value, fmax = 0( at w = 0)

Sol. 51 Option (D) is correct.

In the transconductance amplifier it is desirable to have large input impedance
and large output impedance.
Sol. 52 Option (C) is correct.
Sol. 53 Option (D) is correct.
The voltage at inverting terminal is
V- = V + = 10 V
Here note that current through the capacitor is constant and that is
I = V- = 10 = 10 mA
1k 1k
Thus the voltage across capacitor at t = 1 msec is
# dt = 10 V
Im
V = 1 Idt = 104
# #
1m 1m
= 1 10mdt
C
C0 1m 0 0
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 54 Option (A) is correct.

In forward bias Zener diode works as normal diode.
Thus for negative cycle of input Zener diode is forward biased and it conducts giving
VR = Vin .
For positive cycle of input Zener diode is reversed biased
when 0 < Vin < 6, Diode is OFF and VR = 0
when Vin > 6 Diode conducts and voltage across diode is 6 V. Thus voltage across
is resistor is
VR = Vin - 6
Only option (B) satisfy this condition.
Sol. 55 Option (C) is correct.
The circuit under DC condition is shown in fig below

Applying KVL we have

VCC - RC (IC + IB ) - VCE = 0 ...(1)
and VCC - RB IB - VBE = 0 ...(2)
Substituting IC = bIB in (1) we have
VCC - RC (bIB + IB ) - VCE = 0 ...(3)
Solving (2) and (3) we get
VCE = VCC - VCC - VBE ...(4)
1+ RB
RC (1 + b)
Now substituting values we get
12 - 0.7
VCE = 12 - = 5.95 V
1+ 53
1 + (1 + 60)
Sol. 56 Option (B) is correct.
We have b' = 110 # 60 = 66
100
Substituting b' = 66 with other values in (iv) in previous solutions
12 - 0.7
VCE = 12 - = 5.29 V
1+ 53
1 + (1 + 66)
= 5.29 - 59.5 # 100 =- 4.3%
Thus change is
5.95
Sol. 57 Option (A) is correct.
Sol. 58 Option (C) is correct.
The Zener diode is in breakdown region, thus
V+ = VZ = 6 V = Vin
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Rf
We know that Vo = Vin c1 + m
R1
or Vout = Vo= 6 1 + 12k = 9 V
` 24k j
The current in 12 kW branch is negligible as comparison to 10 W. Thus Current
IC . IE . = Vout = 9 = 0.9 A
RL 10
Now VCE = 15 - 9 = 6 V
The power dissipated in transistor is
P = VCE IC = 6 # 0.9 = 5.4 W
Sol. 59 Option (B) is correct.
If the unregulated voltage increase by 20%, them the unregulated voltage is 18
V, but the VZ = Vin = 6 remain same and hence Vout and IC remain same. There
will be change in VCE
Thus, VCE -18 - 9 = 9 V
IC = 0.9 A
Power dissipation P = VCE IC = 9 # 0.9 = 8.1 W
Thus % increase in power is
8.1 - 5.4 # 100 = 50%
5.4
Sol. 60 Option (B) is correct.
Since the inverting terminal is at virtual ground, the current flowing through the
voltage source is
Is = Vs
10k
Vs = 10 kW = R
or in
Is
Sol. 61 Option (D) is correct.
The effect of current shunt feedback in an amplifier is to decrease the input
resistance and increase the output resistance as :
Rif = Ri
1 + Ab
Rof = R0 (1 + Ab)
where Ri " Input resistance without feedback
Rif " Input resistance with feedback.
Sol. 62 Option (B) is correct.
The CE configuration has high voltage gain as well as high current gain. It
performs basic function of amplifications. The CB configuration has lowest Ri
and highest Ro . It is used as last step to match a very low impedance source and
to drain a high impedance load
Thus cascade amplifier is a multistage configuration of CE-CB
Sol. 63 Option (D) is correct.
Common mode gain
ACM =- RC
2RE
And differential mode gain
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

ADM =- gm RC
Thus only common mode gain depends on RE and for large value of RE it
decreases.
Sol. 64 Option (C) is correct.
VBE -13 0.7
` j
IE = Is e n V - 1 = 10 c
T -3 - 1m = 49 mA
e1 #26 #10
Sol. 65 Option (C) is correct.
The circuit is as shown below

Writing equation for I - have

e 0 - V-
= I-
1M
or e0 = I - (1M) + V- ...(1)
Writing equation for I+ we have
0 - V+ = I
+
1M
or V+ = - I + (1M) ...(2)
Since for ideal OPAMP V+ = V-, from (1) and (2) we have
e0 = I - (1M) - I + (1M)
= (I - - I +) (1M) = IOS (1M)
Thus if e0 has been measured, we can calculate input offset current IOS only.
Sol. 66 Option (C) is correct.
At low frequency capacitor is open circuit and voltage acr s non-inverting terminal
is zero. At high frequency capacitor act as short circuit and all input voltage
appear at non-inverting terminal. Thus, this is high pass circuit.
The frequency is given by
w = 1 = 1 = 1000 rad / sec
RC 3 -6
1 # 10 # 1 # 10
Sol. 67 Option (B) is correct.
The circuit under DC condition is shown in fig below
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Applying KVL we have

VCC - RB IB - VBE - R E I E = 0
or VCC - RB IB - VBE - R E (b + 1)IB = 0 Since IE = IB + bIB
VCC - VBE
or IB =
RB + (b + 1) RE
= 20 - 0.7 = 40mA
430k + (50 + 1)1 k
Now IC = bIB = 50 # 40m = 2 mA
VC = VCC - RC IC = 20 - 2m # 2k = 16 V
Sol. 68 Option (A) is correct.
The maximum load current will be at maximum input voltage i.e.
Vmax = 30 V i.e.
Vmax - VZ = I + I
L Z
1k
or 30 - 5.8 = I = 0.5 m
L
1k
or IL = 24.2 - 0.5 = 23.7 mA
Sol. 69 Option (D) is correct.
Sol. 70 Option (B) is correct.
The small signal model is as shown below

From the figure we have

Zin = 2 MW
20 kW
and Z0 = rd RD = 20k 2k =
11
Sol. 71 Option (A) is correct.
The circuit in DC condition is shown below

Since the FET has high input resistance, gate current can be neglect and we get
VGS =- 2 V
Since VP < VGS < 0, FET is operating in active region
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

VGS 2 (- 2) 2
Now ID = IDSS c1 - m = 10 c1 - m = 5.625 mA
VP (- 8)
Now VDS = VDD - ID RD = 20 - 5.625m#2k = 8.75 V
Sol. 72 Option (B) is correct.
The transconductance is
gm = 2
VP ID IDSS

or, = 2 5.625mA # 10mA = 1.875 mS

8
The gain is A =- gm (rd R D )
So, = 1.875ms # 20 K =- 3.41
11
Sol. 73 Option (B) is correct.
Only one diode will be in ON conditions
When lower diode is in ON condition, then
Vu = 2k Vsat = 2 10 = 8 V
2.5k 2.5
when upper diode is in ON condition
Vu = 2k Vsat = 2 (- 10) =- 5 V
2.5k 4
Sol. 74 Option (B) is correct.
An ideal OPAMP is an ideal voltage controlled voltage source.
Sol. 75 Option (C) is correct.
In voltage series feed back amplifier, input impedance increases by factor (1 + Ab)
and output impedance decreases by the factor (1 + Ab).
Rif = Ri (1 + Ab)
Rof = Ro
(1 + Ab)
Sol. 76 Option (A) is correct.
This is a Low pass filter, because
V0 = 0
At w = 3 Vin
V0 = 1
and at w = 0 V in

Sol. 77 Option (D) is correct.

When IC >> ICO
IC
g= = 1mA = 0.04 = 40 mA / V
m
VT 25mV
b
rp = = 100 = 2.5 kW
gm
40 # 10-3
Sol. 78 Option (A) is correct.
The given circuit is wein bridge oscillator. The frequency of oscillation is
2pf = 1
RC
or C = 1 = 1 =1m
2pRf 3 3 2p
2p # 10 # 10
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 79 Option (A) is correct.

The circuit is as shown below

We know that for ideal OPAMP

V- = V+
Applying KCL at inverting terminal
V- - Vs + V- - V0 = 0
R1 R1
or 2V- - Vo = Vs ...(1)
Applying KCL at non-inverting terminal
V+ V - Vo
+ IL + + =0
R2 R2
or 2V+ - Vo + I L R 2 = 0 ...(2)
Since V- = V+ , from (1) and (2) we have
Vs + IL R2 = 0
or IL =- Vs
R2
Sol. 80 Option (D) is correct.
If IZ is negligible the load current is
12 - Vz = I
L
R
as per given condition
100 mA # 12 - VZ # 500 mA
R
At IL = 100 mA 12 - 5 = 100 mA VZ = 5 V
R
or R = 70W
At IL = 500 mA 12 - 5 = 500 mA VZ = 5 V
R
or R = 14 W
Thus taking minimum we get
R = 14 W
Sol. 81 Option (B) is correct.
Sol. 82 Option (C) is correct.
The Thevenin equivalent is shown below
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

VT = R1 V 1 # 5 = 1V
C =
R1 + R2 4+1
Since b is large is large, IC . IE , IB . 0 and
IE = VT - VBE = 1 - 0.7 = 3 mA
RE 300
Now VCE = 5 - 2.2kIC - 300IE
= 5 - 2.2k # 1m - 300 # 1m = 2.5 V
Sol. 83 Option (B) is correct.
For the different combinations the table is as follows

CE CE CC CB
Ai High High Unity
Av High Unity High
Ri Medium High Low
Ro Medium Low High

Sol. 84 Option (D) is correct.

This circuit having two diode and capacitor pair in parallel, works as voltage doubler.
Sol. 85 Option (B) is correct.
If the input is sinusoidal signal of 8 V (peak to peak) then
Vi = 4 sin wt
The output of comparator will be high when input is higher than Vref = 2 V and will
be low when input is lower than Vref = 2 V. Thus the waveform for input is shown
below

From fig, first crossover is at wt1 and second crossover is at wt2 where
4 sin wt1 = 2V
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Thus wt1 = sin-1 1 = p

2 6
wt2 = p - = p 5p
6 6
5p
- p 1
Duty Cycle = 6 6 =
2p 3
Thus the output of comparators has a duty cycle of 1 .
3
Sol. 86 Option (C) is correct.
CMMR = Ad
Ac
or 20 log CMMR = 20 log Ad - 20 log Ac = 48 - 2 = 46 dB
Where Ad "Differential Voltage Gain
and AC " Common Mode Voltage Gain
Sol. 87 Option (B) is correct.
The gain of amplifier is
-gm
Ai =
gb + jwC
Thus the gain of a transistor amplifier falls at high frequencies due to the
internal capacitance that are diffusion capacitance and transition capacitance.
Sol. 88 Option (A) is correct.
We have Ri = 1kW, b = 0.2, A = 50
Thus, Rif = Ri = 1 kW
(1 + Ab) 11
Sol. 89 Option (A) is correct.
The DC equivalent circuit is shown as below. This is fixed bias circuit operating
in active region.

In first case VCC - IC1R2 - VCE 1 = 0

or 6 - 1.5m R2 - 3 = 0
or R2 = 2kW
IB1 = IC1
= 1.5m = 0.01 mA
b1 150
In second case IB2 will we equal to IB1 as there is no in R1.
Thus IC2 = b2 IB2 = 200 # 0.01 = 2 mA
VCE2 = VCC - IC2 R 2 = 6 - 2m # 2 kW = 2 V
Sol. 90 Option (A) is correct.
The given circuit is a R - C phase shift oscillator and frequency of its oscillation
is
f = 1
2p 6 RC
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 91 Option (C) is correct.

If we see th figure we find that the voltage at non-inverting terminal is 3 V by the zener
diode and voltage at inverting terminal will be 3 V. ThusVo can be get by applying
voltage division rule, i.e.
20 V = 3
20 + 40 o
or V0 = 9 V
Sol. 92 Option (B) is correct.
The circuit is as shown below

8 (3) = 8 kW
V+ =
1+ 8 3
V+ = V- = V 8
3
Now applying KCL at inverting terminal we get
V- - 2 + V- - Vo = 0
1 5
or Vo = 6V- - 10
= 6 # 8 - 10 = 6 V
3
Sol. 93 Option (C) is correct.
The equivalent circuit of 3 cascade stage is as shown in fig.

V2 = 1k 50V1 = 40V1
1k + 0.25k
Similarly V3 = 1k 50V2 = 40V2
1k + 0.25k
or V3 = 40 # 40V1
Vo = 50V3 = 50 # 40 # 40V1
Vo = 50 40 40 = 8000
or AV = # #
V1
or 20 log AV = 20 log 8000 = 98 dB
Sol. 94 Option (D) is correct.
If a constant current is made to flow in a capacitor, the output voltage is integration
of input current and that is sawtooth waveform as below :
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

#
t
V = 1
C idt
C 0
The time period of wave form is
T = 1 = 1 = 2 m sec
f 500
-3
20 #10
1
Thus 3 =
2 # 10 6 0
idt #
or i (2 # 10-3 - 0) = 6 # 10-6
or i = 3 mA
Thus the charging require 3 mA current source for 2 msec.
Sol. 95 Option (C) is correct.
In voltage-amplifier or voltage-series amplifier, the Ri increase and Ro decrease
because
Rif = Ri (1 + Ab)
Rof = Ro
(1 + Ab)
Sol. 96 Option (B) is correct.
Let x be the gain and it is 20 db, therefore
20 log x = 20
or x = 10
Since Gain band width product is 10 6 Hz, thus So,
bandwidth is
6
= 10 = 105 Hz = 100 kHz
6
BW = 10
Gain 10
Sol. 97 Option (A) is correct.
In multistage amplifier bandwidth decrease and overall gain increase. From bandwidth
point of view only options (A) may be correct because lower cutoff frequency must be
increases and higher must be decreases. From following calculation we have
We have fL = 20 Hz and fH = 1 kHz
For n stage amplifier the lower cutoff frequency is
fL 20 = 39.2 . 40 Hz
fLn = 1
= 1
2 n -1 23 - 1
The higher cutoff frequency is
2 2 - 1 = 0.5 kHz
1
fHn = fH
Sol. 98 Option (A) is correct.
As per Barkhousen criterion for sustained oscillations Ab $ 1 and phase shift
must be or 2pn .
V (f)
Now from circuit A = O = 1 + R2
Vf (f) R1
V (f)
b (f) = 1 +0 = f
6 VO (f)
Thus from above equation for sustained oscillation
6 = 1 + R2
R1
or R2 = 5R1
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 99 Option (C) is correct.

Let the gain of OPAMP be AV then we have
20 log AV = 40 dB
or AV = 100
Let input be Vi = Vm sin wt then we have
VO = VV Vi = Vm sin wt
dVO
Now = AV Vm w cos wt
dt
Slew Rate dVO = AV Vm w = AV Vm 2pf
c m
dt max
or Vm = SR = 1
AV V2pf 10 # 100 # 2p # 20 # 103
-6

or VM = 79.5 mV
Sol. 100 Option (A) is correct.
The circuit is shown as below

I = IZ + IL
For satisfactory operations
Vin - V0
> IZ + IL [IZ + IL = I]
R
When Vin = 30 V,
30 - 10 $ (10 + 1) mA
R
or 20 $ 11 mA
R
or R # 1818 W
when Vin = 50 V 50 - 10 $ (10 + 1) mA
R
40 $ 11 # 10-3
R
or R # 3636W Thus R # 1818W
Sol. 101 Option (D) is correct.
We have
IDSS = 10 mA and VP =- 5 V
Now VG = 0
and VS = ID RS = 1 # 2.5W = 2.5 V
Thus VGS = VG - VS = 0 - 2.5 =- 2.5 V
gm = DSS 81 - ` -2.5 j B = 2 mS
2I
Now
VP -5
V0
AV = =- gm RD
Vi
So, =- 2ms # 3k =- 6
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 102 Option (C) is correct.

The current gain of a BJT is
hfe = gm rp
Sol. 103 Option (A) is correct.
The ideal op-amp has following characteristic :
Ri " 3
R0 " 0
and A "3
Sol. 104 Option (C) is correct.
Both statements are correct because
(1) A stable multivibrator can be used for generating square wave, because of its
characteristic
(2) Bi-stable multivibrator can store binary information, and this multivibrator
also give help in all digital kind of storing.
Sol. 105 Option (B) is correct.
If fT is the frequency at which the short circuit common emitter gain attains unity
magnitude then
gm
fT = = 38 # 10-3 = 1.47 # 1010 Hz
2p (Cm + Cp) 2p # (10 + 4 # 10 )
-14 -13

If fB is bandwidth then we have

10
f
fB= T = 1.47 # 10 = 1.64 # 108 Hz
b 90
Sol. 106 Option (C) is correct.
If we neglect current through RB then it can be open circuit as shown in fig.

Maximum power will dissipate in Zener diode when current through it is maximum
and it will occur at Vin = 30 V
I = Vin - Vo = 30 - 10 = 1 A
20 20
I IC + IZ = bIB + IZ Since IC = bIB
= bIZ + IZ = (b + 1) IZ since IB = IZ
I = 1
or IZ = = 0.01 A
b+1 99 + 1
Power dissipated in zener diode is
PZ = VZ IZ = 9.5 # 0.01 = 95 mW
IC = bIZ = 99 # 0.1 = 0.99 A
VCE = Vo = 10 V
Power dissipated in transistor is
PT = VC IC = 10 # 0.99 = 9.9 W
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 107 Option (B) is correct.

From the it may be easily seen that the tank circuit is having 2-capacitors and one-
inductor, so it is colpits oscillator and frequency is
f = 1
2p LCeq
Ceq = C1C2 = 2 # 2 = 1 pF
C1 + C2 4 9
f = 1 = 1 # 10 = 50.3 MHz
2p 10 # 10-6 # 10-12 2p 10
Sol. 108 Option (D) is correct.
The circuit is as shown below

Let V- be the voltage of inverting terminal, since non inverting terminal a at

ground, the output voltage is
Vo = AOL V- ...(1)
Now applying KCL at inverting terminal we have
V- - Vs + V- - V0 = 0 ...(2)
R1 R2
From (1) and (2) we have
VO = A = - R2
CL
Vs R - R 2 + R1
ROL
Substituting the values we have
ACL = - 10k =- 1000 .- 11
1k - 10k + 1k 89
100k
Sol. 109 Option (A) is correct.
The first OPAMP stage is the differentiator and second OPAMP stage is integrator.
Thus if input is cosine term, output will be also cosine term. Only option (A) is
cosine term. Other are sine term. However we can calculate as follows. The circuit
is shown in fig

Applying KCL at inverting terminal of first OP AMP we have

V1 = - wjL = -100 # 10 # 10 -3 = -1
VS R 10 10
- jVS
or V1 = = j cos 100t
10
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Applying KCL at inverting terminal of second OP AMP we have

VO - 1 / jwC
=
V1 100
=- 1 = j10
j100 # 10 # 10-6 # 100
or V0 = j10V2 = j10 (- j cos 100t)
V0 = 10 cos 100t
Sol. 110 Option (C) is correct.
With the addition of R E the DC abis currents and voltages remain closer to
the point where they were set by the circuit when the outside condition such as
temperature and transistor parameter b change.
Sol. 111 Option (A) is correct.
Common mode gain is
AC = aRC
REE
Since source resistance of the current source is infinite REE = 3, common mode
gain AC = 0
Sol. 112 Option (D) is correct.
In positive feed back it is working as OP-AMP in saturation region, and the input
applied voltage is + ve.
So, V0 =+ Vsat = 15 V
Sol. 113 Option (A) is correct.
At high frequency
gm
Ai =-
gbc' +
jw (C)
or, Ai \ 1
Capacitance
and Ai a 1
frequency
Thus due to the transistor capacitance current gain of a bipolar transistor drops.
Sol. 114 Option (C) is correct.
As OP-AMP is ideal, the inverting terminal at virtual ground due to ground at non-
inverting terminal. Applying KCL at inverting terminal
sC (v1sin wt - 0) + sC (V2 sin wt - 0) +sC (V o - 0) = 0
or Vo =- ( V1 + V2) sin wt
Sol. 115 Option (D) is correct.
There is R - C , series connection in parallel with parallel R - C combination.
So, it is a wein bridge oscillator because two resistors R1 and R2 is also in parallel with
them.
Sol. 116 Option (A) is correct.
The given circuit is a differentiator, so the output of triangular wave will be
square wave.
Sol. 117 Option (B) is correct.
In sampling and hold circuit the unity gain non-inverting amplifier is used.
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 118 Option (D) is correct.

The Thevenin equivalent is shown below

VT = R1 V 5 # 15 = 5 V
C =
R1 + R2 10 + 5
Since b is large is large, IC . IE , IB . 0 and
IE = VT - VBE
RE
= 5 - 0.7 = 4.3 = 10 mA
0.430kW 0.430KW
Sol. 119 Option (C) is correct.
The output voltage will be input offset voltage multiplied by open by open loop gain.
Thus
So V0 = 5mV # 10, 000 = 50 V
But V0 =! 15 V in saturation condition
So, it can never be exceeds !15 V
So, V0 =! Vset =! 15V
Sol. 120 Option (A) is correct.
Sol. 121 Option (A) is correct.
Negative feedback in amplifier reduces the gain of the system.
Sol. 122 Option (A) is correct.
By drawing small signal equivalent circuit

by applying KCL at E2
V
g m1 Vp - p = g m2 Vp
2

rp
1 2

at C2 i 0 =- gm2 Vp 2

from eq (1) and (2)

gm1 Vp + i0 =- i0
1
gm2 rp 2

gm1 Vp =- i0 :1 +g1 rD
m2 p
1
2
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

gm2rp = b >> 1
2

so gm1 Vp =- i 0
1

i0 =- g
m1
V 1

pi
0
= gm1 a Vp = Vi
Vi 1

Sol. 123 Option (B) is correct.

Crossover behavior is characteristic of calss B output stage. Here 2 transistor
are operated one for amplifying + ve going portion and other for -ve going
portion.
Sol. 124 Option (C) is correct.
In Voltage series feedback mode input impedance is given by
R in = Ri (1 + bv Av)
where bv = feedback factor ,
Av = openloop gain
and Ri = Input impedance
So, R in = 1 # 103 (1 + 0.99 # 100) = 100 kW
Similarly output impedance is given by
R OUT = R0
R 0 = output impedance
(1 + bv Av)
Thus R OUT = 100 =1W
(1 + 0.99 # 100)
Sol. 125 Option (B) is correct.
Regula tion = V no - load - Vfuel -load
Vfull - load
= 30 - 25 # 100 = 20%
25
Output resistance = 25 = 25 W
1
Sol. 126 Option (D) is correct.
This is a voltage shunt feedback as the feedback samples a portion of output voltage
and convert it to current (shunt).
Sol. 127 Option (A) is correct.
In a differential amplifier CMRR is given by
(1 + b) IQ R 0
CMRR = 1 ;1 + E
2 VT b
So where R 0 is the emitter resistance. So CMRR can be improved by increasing
emitter resistance.
Sol. 128 Option (C) is correct.
We know that rise time (tr ) is
tr = 0.35
fH
where fH is upper 3 dB frequency. Thus we can obtain upper 3 dB frequency it
rise time is known.
Sol. 129 Option (D) is correct.
In a BJT differential amplifier for a linear response Vid < VT .
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Sol. 130 Option (D) is correct.

In a shunt negative feedback amplifier.
Input impedance
Ri
R in =
(1 + bA )
where R i = input impedance of basic amplifier
b = feedback factor
A = open loop gain
So, R in <
Ri
Similarly R0
R OUT =
(1 + bA )

R OUT < R0
Thus input & output impedances decreases.
Sol. 131 Option (A) is correct.
Sol. 132 Option (D) is correct.
Comparator will give an output either equal to + Vsupply or - Vsupply . So output is
a square wave.
Sol. 133 Option (C) is correct.
In series voltage regulator the pass transistor is in common collector
configuration having voltage gain close to unity.
Sol. 134 Option (D) is correct.
In bridge rectifier we do not need central tap transformer, so its less expensive
and smaller in size and its PIV ( Peak inverse voltage) is also greater than the two
diode circuit, so it is also suitable for higher voltage application.
Sol. 135 Option (C) is correct.
In the circuit we have
V2 = I S # R D
2
and V1 = I S # R D
V2 1
V1 = 2
V1 = 2V2
Sol. 136 Option (C) is correct.
Sol. 137 Option (C) is correct.
The equivalent circuit of given amplifier circuit (when CE is connected, RE is short-
circuited)

Input impedance R i = R B || r p
Voltage gain AV = g m R C
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Now, if CE is disconnected, resistance RE appears in the circuit

Input impedance R in = R B || [ rp + ( b + 1)] R E

Input impedance increases
gm RC
Voltage gain AV = Voltage gain decreases.
1 + gm RE
Sol. 138 Option (A) is correct.
In common emitter stage input impedance is high, so in cascaded amplifier common
emitter stage is followed by common base stage.
Sol. 139 Option (C) is correct.
We know that collect-emitter break down voltage is less than compare to collector
base breakdown voltage.
BVCEO < BVCBO
both avalanche and zener break down. Voltage are higher than BVCEO .So BVCEO
limits the power supply.
Sol. 140 Option (C) is correct.

If we assume consider the diode in reverse bias thenVn should be greater than VP .
VP < Vn
by calculating
VP = 410 # 4 = 5 Volt
+4
Vn = 2 # 1 = 2 Volt
here VP > Vn (so diode cannot be in reverse bias mode).

apply node equation at node a

Va - 10 + Va + Va = 2
4 4 1
6Va - 10 = 8
Va = 3 Volt
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

so current Ib = 0 - 3 + 10 - 3
4 4
Ib = 10 - 6 = 1 amp
4
Sol. 141 Option (D) is correct.
Applying node equation at terminal (2) and (3) of OP -amp

Va - Q Va - V0
+ =0
5 10
2Va - 4 + Va - V 0 = 0
V0 = 3Va - 4
Va - V0 + Va - 0 = 0
100 10
Va - V0 + 10Va = 0
11Va = V0
Va = V0
11
So V0 = 3V0 - 4
11
8V
=- 4
0
11
V0 =- 5.5 Volts
Sol. 142 Option (B) is correct.
Circuit with diode forward resistance looks

So the DC current will

IDC = Vm
p ( R f + R L)
Sol. 143 Option (D) is correct.
For the positive half cycle of input diode D1 will conduct & D2 will be off. In negative
half cycle of input D1 will be off & D2 conduct so output voltage wave from across
resistor (10 kW) is –
 GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Ammeter will read rms value of current

so I rms = Vm (half wave rectifier)
pR
= 4 = 0.4 mA
(10 kW) p p
Sol. 144 Option (D) is correct.
In given circuit positive feedback is applied in the op-amp., so it works as a
Schmitt trigger.
Sol. 145 Option (D) is correct.
Gain with out feedback factor is given by
V0 = kVi
after connecting feedback impedance Z

given input impedance is very large, so after connecting Z we have

Ii = Vi - V0 V0 = kVi
Z
-
Ii = i kVi
V
Z
input impedance Zin = Vi = Z
Ii (1 - k)
Sol. 146 Option (A) is correct.
Sol. 147 Option (A) is correct.
For the circuit, In balanced condition It will oscillated at a frequency
w= 1 = 1 = 105 rad / sec
3 6
LC 10 # 10- # .01 # 10-
In this condition
R1 = R 3
R R4
2
5 =R
100 1
R = 20 kW = 2 # 104 W
Sol. 148 Option (C) is correct.
V0 kept constant at V0 = 6 volt
so current in 50 W resistor
9-6
I =
50 W
I = 60 m amp
GATE SOLVED PAPER - EC ANALOG ELECTRONIC

Maximum allowed power dissipation in zener

PZ = 300 mW
Maximum current allowed in zener
PZ = VZ (I Z ) max = 300 # 10-3
& = 6 (I Z ) max = 300 # 10-3
& = (IZ ) max = 50 m amp
Given knee current or minimum current in zener
(IZ ) min = 5 m amp
In given circuit I = IZ + IL
I L = I - IZ
(I L ) min = I - (I Z ) max
= (60 - 50) m amp = 10m amp
(I L ) max = I - (I Z ) min
= (60 - 5) = 55 m amp

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