AMBA PROTCOLS
AHB
ADVANCED HIGH PERFORMANCE BUS
AXI INTERCONNECT IN SOC
AXI INTERCONNECT IN NOC
CLASSIFICATION OF AMBA
AMBA SPECIFICATION (FIRST VERSION) DEFINES TWO BUSES/INTERFACES:
Advanced System Bus (ASB)
Advanced Peripheral Bus (APB)
AMBA 2 SPECIFICATION DEFINES THREE BUSES/INTERFACES:
Advanced High-performance Bus (AHB) - widely used on ARM7, ARM9
and Arm Cortex-M based designs
Advanced System Bus (ASB)
Advanced Peripheral Bus (APB2 or APB)
AMBA 3 SPECIFICATION DEFINES FOUR BUSES/INTERFACES:
Advanced Extensible Interface(AXI3 or AXI v1.0) - widely used on Arm
Cortex-A processors including Cortex-A9
Advanced High-performance Bus Lite (AHB-Lite v1.0)
Advanced Peripheral Bus (APB3 v1.0)
Advanced Trace Bus (ATB v1.0)
THE AMBA 4 SPECIFICATION DEFINES FOLLOWING BUSES/INTERFACES:
AXI Coherency Extensions (ACE) - widely used on the latest Arm Cortex-
A processors including Cortex-A7 and Cortex-A15
AXI Coherency Extensions Lite (ACE-Lite)
Advanced Extensible Interface 4 (AXI4)
Advanced Extensible Interface 4 Lite (AXI4-Lite)
Advanced Extensible Interface 4 Stream (AXI4-Stream v1.0)
Advanced Trace Bus (ATB v1.1)
Advanced Peripheral Bus (APB4 v2.0)
AMBA Low Power Interfaces (Q-Channel and P-Channel)
THE AMBA 5 SPECIFICATION DEFINES THE FOLLOWING BUSES/INTERFACES:
AXI5, AXI5-Lite and ACE5 Protocol Specification
Advanced High-performance Bus (AHB5, AHB-Lite)
Coherent Hub Interface (CHI) [3]
Distributed Translation Interface (DTI)
Generic Flash Bus (GFB)
AHB FEATURES
Burst transfers
Split Transactions
Wider data bus configurations (64/128 bits)
Single-clock edge operation
Single-cycle bus master handover
1 AHB MASTER, 3 AHB SLAVE BLOCK DIAGRAM
MASTER INTERFACE
SLAVE INTERFACE
AXI TRANSFERS
Type of Transfers
Transfer Size
Simple Transfers
Locked Transfers
Burst operation
Waited Transfers
TYPE OF TRANSFERS - HTRANS[1:0]
IDLE (00) – Indicate a new transfer
No data transfer is required
Used when the master is granted the bus without performing transfer
The slave must provide a zero wait state OKAY response
BUSY (01)
Allow master to insert IDLE cycle in the middle of bursts of transfers
Address and control signals must reflect the next transfer in the burst
The slave must provide a zero wait state OKAY response
NONSEQ (10) – Indicate a new transfer
Indicate the first transfer of a burst or a single transfer
Address and control signals are unrelated to previous transfer
SEQ (11)
Indicate a remaining transfer in a burst
Address = Address of previous transfer + size in byte
TYPE OF TRANSFERS - HTRANS[1:0]
IDLE (00) – Indicate a new transfer
No data transfer is required
Used when the master is granted the bus without performing transfer
The slave must provide a zero wait state OKAY response
BUSY (01)
Allow master to insert IDLE cycle in the middle of bursts of transfers
Address and control signals must reflect the next transfer in the burst
The slave must provide a zero wait state OKAY response
NONSEQ (10) – Indicate a new transfer
Indicate the first transfer of a burst or a single transfer
Address and control signals are unrelated to previous transfer
SEQ (11)
Indicate a remaining transfer in a burst
Address = Address of previous transfer + size in byte
TYPE OF TRANSFERS - HTRANS[1:0]
TRANSFER SIZE - HSIZE[2:0]
SIMPLE TRANSFERS
Masters must be granted bus for access before transfer
Masters assert request signals
Arbiter indicates when the master will be granted use of the bus
An AHB-bus transfer
Address phase
A single cycle in which the master drives the address and control signals
Indicate direction, width of transfer, and if the transfer forms part of a burst
Each address correspond to 1-byte data (byte-addressable)
Data phase
One or more cycles controlled by HREADY from slave
The slaves sample and process the data
Address phase and data phase of different transactions are overlapped
WRITE / READ TRANSFERS
WITH WAIT STATES
MULTIPLE TRANSFERS
LOCKED TRANSFERS - HMASTLOCK
If the master requires locked accesses then it must also assert the HMASTLOCK signal. This signal
indicates to any slave that the current transfer sequence is indivisible and must therefore be processed
before any other transfers are processed.
BURST OPERATION
4/8/16-beat bursts, as well as undefined-length bursts
Burst size indicates the number of beats in the burst
Valid data transferred = (# of beats) x (data size in each beat) Data size in each
beat is indicated in HSIZE[2:0]
Incrementing bursts
Access sequential locations with the address of each transfer in the burst being an
increment of the previous address
An incremental burst can be of any length, but the upper limit is set by the fact that
address must not cross a 1KB boundary
Wrapping bursts
If the start address of the transfer is not aligned to the total number of bytes in a
burst (size x beats) then the address of the transfers in the burst will wrap when the
boundary is reached
BURST SIGNAL ENCODING
BURST SIGNAL ENCODING
FOUR-BEAT WRAPPING BURST, WRAP4
FOUR-BEAT INCREMENTING BURST, INCR4
EIGHT-BEAT WRAPPING BURST, WRAP8
EIGHT-BEAT INCREMENTING BURST, INCR8
EXAMPLE OF UNDEFINED LENGTH BURST OPERATION
