Part II: Layout Basics

Inverter Layout
• Features
– VDD & Ground ‘rail’
• using Metal1 layer
– N-well region horizontal
• for pMOS poly
– Active layers
• different n+ and p+
– Contacts
• n+/p+ to metal
• poly to metal
• Alternate layout
– advantage
• simple poly routing vertical
– disadvantage poly
• harder to make W large

ECE 410, Prof. A. Mason Lecture Notes Page 3.18

 Part II: Layout Basics

CMOS Layout Layers

• Mask layers for 1 poly,
2 metal, n-well CMOS process
– Background: p-substrate
– nWell
– Active (nactive and pactive)
– Poly
– pSelect
– nSelect
– Active Contact
– Poly Contact
– Metal1
– Via
– Metal2
– Overglass
• See supplementary power point file for animated CMOS process flow
– should be viewed as a slide show, not designed for printing

ECE 410, Prof. A. Mason Lecture Notes Page 3.19

 Part II: Layout Basics

Series MOSFET Layout

• Series txs
– 2 txs share a S/D junction

• Multiple series transistors

– draw poly gates side-by-side

ECE 410, Prof. A. Mason Lecture Notes Page 3.20

 Part II: Layout Basics

Parallel MOSFET Layout

• Parallel txs
– one shared S/D junction with contact
– short other S/D using interconnect layer (metal1)

• Alternate layout strategy

– horizontal gates

ECE 410, Prof. A. Mason Lecture Notes Page 3.21

 Part II: Layout Basics

NAND/NOR Layouts
• One layout option with horizontal transistors
(L runs horizontally)
– ignore the size (W) for now

2-input NAND 2-input NOR

pMOS pMOS
2 parallel tx 2 series tx

nMOS nMOS
2 series txs 2 parallel txs

ECE 410, Prof. A. Mason Lecture Notes Page 3.22

 Part II: Layout Basics

Layout Cell Definitions

• Cell Pitch = Height of standard cells VDD!
measured between VDD & GND rails
A
– A: 410 lab definition B C
• top of VDD to bottom of GND
– B: interior size, without power rails GND!
– C: textbook definition
• middle of GND to middle of VDD
• Cell Boundary
max extension of any layer (except nwell) VDD!
– set boundary so that cells can be placed
side-by-side without any rule violations
– extend power rails 1.5 (or 2 to be safe)
beyond any active/poly/metal layers
GND!
– extend n-well to cell boundary (or
beyond) to avoid breaks in n-well cell boundary

ECE 410, Prof. A. Mason Lecture Notes Page 3.23

 Part II: Layout Basics

Cell Layout Guidelines

• Internal Routing
– use lowest routing layer possible, typically poly and metal1
– keep all possible routing inside power rails
– keep interconnects as short as possible
• Bulk (substrate/well) Contacts
– must have many contacts to p-substrate and n-well
• at least 1 for each connection to power/ground rails
– consider how signals will be routed in/out of the cells
• don’t block access to I/O signals with substrate/well contacts
• S/D Area Minimization
– minimize S/D junction areas to keep capacitance low
• I/O Pads
– Placement: must be able to route I/O signals out of cell
– Pad Layer: metal1 for smaller cells, metal2 acceptable in larger cells
• Cell Boundary
– extend VDD and GND rail at least 1.5 beyond internal features
– extend n-well to cell boundary to avoid breaks in higher level cells

ECE 410, Prof. A. Mason Lecture Notes Page 3.24

 Part II: Layout Basics

Layout CAD Tools

• Layout Editor
– draw multi-vertices polygons which represent physical design layers
– Manhattan geometries, only 90º angles
• Manhattan routing: run each interconnect layer perpendicular to each other
• Design Rules Check (DRC)
– checks rules for each layer (size, separation, overlap)
–
• Parameter Extraction
– create netlist of devices (tx, R, C) and connections
– extract parasitic Rs and Cs, lump values at each line (R) / node (C)
• Layout Vs. Schematic (LVS)
– compare layout to schematic
– check devices, connections, power routing
• can verify device sizes also
– ensures layout matches schematic exactly
–

ECE 410, Prof. A. Mason Lecture Notes Page 3.25

 Part II: Layout Basics

Layout with Cadence Tools

inv
• Layer Map
CMOS Features CMOS Mask Layers Cadence Layers
n-well n-well nwell
FOX active pactive, nactive
n+ S/D regions n+ doping nselect
p+ S/D regions p+ doping pselect
Gate poly poly
Active/Poly contact Contact cc
Metal 1 Metal 1 metal1
Via VIA via
Metal 2 Metal 2 metal2
in out
• Inverter Example

ECE 410, Prof. A. Mason Lecture Notes Page 3.26

 Part II: Layout Basics

Design Rules: Intro

• Why have Design Rules
– fabrication process has minimum/maximum feature sizes that can be
produced for each layer
– alignment between layers requires adequate separation (if layers
unconnected) or overlap (if layers connected)
– proper device operation requires adequate separation
• “Lambda” Design Rules
– lambda, , = 1/2 minimum feature size, e.g., 0. 6 m process -> =0.3 m
– can define design rules in terms of lambdas
• allows for “scalable” design using same rules
• Basic Rules
– minimum layer size/width

– minimum layer separation

– minimum layer overlap

ECE 410, Prof. A. Mason Lecture Notes Page 3.27

 Part II: Layout Basics

Design Rules: 1
• n-well MOSIS SCMOS rules; =0.3 m for AMI C5N
– required everywhere pMOS is needed
– rules
• minimum width 10
6
• minimum separation to self
• minimum separation to nMOS Active 5
• minimum overlap of pMOS Active

• Active
– required everywhere a transistor is needed
– any non-Active region is FOX
– rules
3
• minimum width 3
• minimum separation to other Active

ECE 410, Prof. A. Mason Lecture Notes Page 3.28

 Part II: Layout Basics

Design Rules: 2
• n/p Select
– defines regions to be doped n+ and p+
– tx S/D = Active AND Select NOT Poly
– tx gate = Active AND Select AND Poly
– rules
• minimum overlap of Active 2
– same for pMOS and nMOS
• several more complex rules available
• Poly
– high resistance conductor (can be used for short routing)
– primarily used for tx gates 2
– rules 2 gate =
Active-Poly-Select
• minimum size
• minimum space to self 1
• minimum overlap of gate
• minimum space to Active 2

ECE 410, Prof. A. Mason Lecture Notes Page 3.29

 Part II: Layout Basics

Design Rules: 3
• Contacts
– Contacts to Metal1, from Active or Poly note: due to contact size
• use same layer and rules for both and overlap rules, min.
– must be SQUARE and MINIMUM SIZED active size at contact will
be 2+1.5+1.5=5
– rules
1.5
• exact size
• minimum overlap by Active/Poly 2 5
• minimum space to Contact 2 2
• minimum space to gate 2

• Metal1
– low resistance conductor used for routing
– rules
• minimum size
3
• minimum space to self 4 2
• minimum overlap of Contact 1
if wide
ECE 410, Prof. A. Mason Lecture Notes Page 3.30
 Part II: Layout Basics

Design Rules: 4
• Vias
– Connects Metal1 to Metal2
– must be SQUARE and MINIMUM SIZED
– rules
• exact size 2 see MOSIS site
• space to self 3 for illustrations
• minimum overlap by Metal1/Metal2 1
• minimum space to Contact 2
• minimum space to Poly/Active edge 2
• Metal2
– low resistance conductor used for routing
– rules
• minimum size
• minimum space to self 3
• minimum overlap of Via 6 3
1
if wide
ECE 410, Prof. A. Mason Lecture Notes Page 3.31
 Part II: Layout Basics

Substrate/well Contacts
• Substrate and nWells must be n+plug
connected to the power supply to VDD
within each cell
– use many connections to reduce
resistance
– generally place
• ~ 1 substrate contact per nMOS tx
• ~ 1 nWell contact per pMOS tx
– this connection is called a tap, or plug
– often done on top of VDD/Ground rails
– need p+ plug to Ground at substrate
– need n+ plug to VDD in nWell

p+plug
to Ground

ECE 410, Prof. A. Mason Lecture Notes Page 3.32

 Part II: Layout Basics

Latch-Up
• Latch-up is a very real, very important factor in circuit design that
must be accounted for
• Due to (relatively) large current in substrate or n-well
– create voltage drops across the resistive substrate/well
• most common during large power/ground current spikes
– turns on parasitic BJT devices, effectively shorting power & ground
• often results in device failure with fused-open wire bonds or interconnects
– hot carrier effects can also result in latch-up
• latch-up very important for short channel devices
• Avoid latch-up by
– including as many substrate/well contacts as possible
• rule of thumb: one “plug” each time a tx connects to the power rail
– limiting the maximum supply current on the chip

ECE 410, Prof. A. Mason Lecture Notes Page 3.33

 Part II: Layout Basics

Multiple Contacts
• Each contact has a characteristic resistance, Rc
• Contact resistances are much higher than the resistance
of most interconnect layers
• Multiple contacts can be used to reduce resistance
– Rc,eff = Rc / N, N=number of contacts

N=6

• Generally use as many contacts as space allows

use several add Vias

Contacts if room
in wide txs allows

ECE 410, Prof. A. Mason Lecture Notes Page 3.34

 Part III: Fabrication

CMOS Fabrication Process

• What is a “process”
– sequence of step used to form circuits on a wafer
– use additive (deposition) and subtractive (etching) steps
• n-well process
– starts with p-type wafer (doped with acceptors)
• can form nMOS directly on p-substrate
– add an n-well to provide a place for pMOS
• Isolation between devices
– thick insulator called Field Oxide, FOX

ECE 410, Prof. A. Mason Lecture Notes Page 3.35