(eases 9 Te PAC) $$ $$$) Microrrocessor ann INTERFACES INTRODUCTION TO MICROPROCESSORS 1 Q Microprocessor A microprocessor is a multipurpose, programmable logic device that reads binary instructions from a storage device called memory, accepts binary data as input and control, instrumentation appliances control ete. come under tle category of microcomputers. A computer with its microprocessor as its CPU iscalled microcomputers. Single chip microcontrollers are known as microcomputers. Present processes data according tothose instructions and provides’ | day microcomputers can, be classified in four groups: results a$ output. Personal (or business) computer (PC), work stations, single The functions of various components of a | boardand single chip computers. croprocessor based system can be summarized asfollows: | 2. Mini Computers : Mini computers are more 1, Memory powerful than micro computers. They are multi-user system. Stores binary instructions, called programs and data. | A minicomputer runs more slowly. It works directly with Provides the instrfictions and datato the microprocessor | sinaller data words (often 32 bit words).They are used for fon request. single scientific calculation and industrial control. + Stores results and data for the microprocessor. 3. Mainframe Computers : These’are high speed 2. Input Device computers, The data storage capacity of these computers Enters data and instructions under the control of } are very large. The word length varies normally from 32 program such as a monitor program, bit to 64 bits, They are multi-user system. They are used 3. Output Device fer scientific calculation. Accepts data from the microprocessor as specified 4, Super Computers : These are more powerful, much in a program. faster and costlier than mainframe computers. They are 4. Bus used for complex analysis and computation. Carries bits between the microprocessor-and memory. Features of 8085 nP and VOs. (1) Itis an 8 bit microprocessor ie. it can accept, OQ Microcontroller process or provide 8 bit data simultaneously. In microprocessor, peripheral devices (VO devices +] (2). Itis asingle chip NMOS device implemented with memory) are fabricated ona single chip then it is called 6500 transistors. microcontroller which is shown in figure. (3) Irequires a single + SV power supply. (4) The maximum clock frequency is 3.07 MHz and | ininimum clock frequency is SOOKHz. (5) It requires two phases, 50% duty cycle, TTL clock. These clock signals are generated by an internal clock generator, (6). Wprovides 74 in modes register, direct, immediate, in implied addressing modes. (7) ‘The data bus is multiplexed with lower address bus, hence it requires external hardware to separate data lines from address lines. (oun) Q Different types of Computers 1, Microcomputers : As the name implies, microcomputers are small computers. They are low cost, small digital computers. Portable computers, personal Computers (PCs) (single: user desktop computers), Computers for dedicated applications such as-industrial Scanned with CamScanner(8) It provides 16 address lines, hence it can access 64 K bytes of memory. nerates 8 bit 1/0 address, hence it ean access 28» 256 input poris and 256 output ports. ) Prob.l What do you mean by input port and ouput port? IRerv.2019), ——————— Sol. In computer hardware, a port serves as an interface between the computer and other computers or peripheral devices. In computer terms, a port generally refers to the Part of a computing device available for connection to Peripherals such as input and output devices, Input/Output Port 1. An VO port is a socket on a computer that a cable is plugged into. The port connects the CPU to a peripheral device via a hardware interface or to the network via a network interface, 2. Ina PC, an I/O port is an address used to transfer data Prob.2 What is the use of ALE signal? R-4.0.2019] SupneenSuneenmeeee ee Sol. ALE : This is a positive going pulse generated every time the 8085 begins an operation; when i {hat the bits on AD, AD, are address bits and when itis low it indicates that bits on AD, ~ AD, are data bits. (10) It provides 5 hardware interrupt: RST6.5, RST7.5, INTR. (11) By providing external hardware (8259 ehipy can increase the interrupt capability of it (12) It provides status and control signals. To reduce complications on microprocessor IC, we multiplexing, eat Prob.4 Define general purpose registers and thelr use IR.U.209, Sol. General Purpose Registers : 8085 has six 84, general-purpose registers to store 8-bit data named x B\C\D,E.H and L. They can be combined to form regis pairs ~ BC, DE and HL to store 16-bits of data, The registers are programmable by user to store/copy any day and used to perform different operations and hence also know, a scratched registers. The HL pair is used to addres members. Prob. What is microprocessor? oR: Explain microprocessor. IRTU.2019 IRTu.207 Sol. Microprocessor : It is a multipurpose, programmale | lock driven, register based electronie device that reads binay instruction from memory, accepts binary data’ as input and Processes them, Arithmetic Logie Ui Prob3 Why —— Sol, Microprocessor is responsi memory access. 8085 microprocessor has 8 dat 16 address lines - (A, ~A,) and eight dat each other to form AD, ~ AD,, If fin ADeAD; lines are multiplexed? \Rv.2019} LE === Memory le for both data transfer and Fig: : Microprocessor a ines and lower order eight address lines | Prob. Write short note on Multiplexer axuattl a lines (D,—D,) are multiplexed with "i we do not multiplex these | Sol, Multiplexer : Multiplexer means to on en we have to add more pins on microprocessor IC. | mulkiplexerisa cirguit used toselectand rose ny one | Scanned with CamScanneroa signal output. A simple example of a wera = it of a multiplexer is a single pole pon electronic ein frultipasition switch, Moltiposition switches are widely used in many electronics circuits, However circuits that operate at high require the multiplexer tobe automatically selected. A chanical Switch cannot perform ‘this task satisfactorily Trerefote: multiplexer used to perform high speed switching are constructed of electronic components. Multiplexer handle two type of data that is analog and aigital. For analog application, multiplexer are built of relays nd transistor switches, For digital application, they are built, fom standard logic gates, ‘The multiplexer used for digital applications, also called digital multiplexer, isa circuit with many input but only one output. By applying control signals, we can steer any input to the output. Few types of multiplexer are 2-to-1, 4-t0-1, 8-t0- 1 and 16-to-1 multiplexer. Following figure shows the general idea of'a multiplexer ‘withn input signal, m control signals and one output signal. Fig. : Mulplexer Pin Diagram — Prob.7 Write short note on De-multiplexer. {R.T.V.2017| Nene mma Sol. De-multiplexer : De-multiplexer means one to many. ‘Ade-multiplexer is a circuit with one input and many outputs. By applying control signal, we can steer any input to the output. Few types of de-multiplexer are 1-to-2, 1-to-4, I-to-B and J-to-16 De-multiplexer. Following figure illustrate the general idea of a de- ‘nutiplexer with | input signal, m control signals, and n output sionals, Fig. : De-multiplexer Pin Diagram = (RT. 207] Prob. Write chart note on Encoder. 0 Sol. Encoder : “An encoder is a combinational logic circuit that essentially performs a ‘reverse’ decoder function. It accepts an active level on one of its inputs representing digit, such as a decimal or octal digit. and converts it to a coded eutput such as binary or BCD.” ; Encoders can also be devised to encode various symbols and alphabetic characters. This process of converting from familiar symbols or numbers 10 a coded format is called Encoding. Encoder has n input lines, only one of which is active at any time and m output lines. In an ‘encoder the number of outpat is less than the number of input. apa noepe ig. + Block Diagram of an Encoder ‘An 8103 encoder has eight active low inputs and three output lines. When the input line 0 goes low, the output is 000, when the input line 5 goes low, the output is 101. For simultaneous inputs, priority encoders are very successful. 7ALS148 is an example of 8 to 3 priority encoder. Encoders are commonly used with keyboards. For each key pressed, the corresponding binary code is placed on the data bus. — Prob.9 Write short note on Decoder. [RT.U. 2017} oe Sol. Decoder : “Decoder is used to detect the presence of a speeified combination of bits (code) on its inputs and to indicate that presence by a specified output fevel.” When generalized, a decoder has n input lines to handle inbits and from one to 2 output line to indicate the presence of one or more n-bit combinations. Decoding is necessary in applications such as data multiplexing, digital display, digital {0 analog converters and memory addressing. For example, if the input to a decoder has 2 binary lines, the decoder will have 4 output lines. The 2 lines can assume four combinations of input signals 00, 01, 10, 11 with each combination identified by the output lines 0 to 3. Ifthe put is (10),, the output line 2 will be at logic 1, and others will remain at logic 0. This is called Decoding. Scanned with CamScannerBreck, AW Sem) CS. Solved p (Greh OY Sem CS. SOT ¢ MPU : » : a Memory | VO « et peor i" ouna of of} iG Peripheral Devices 4 ‘ Fig. 1:2 to 4 Decoder Logie Symbol Example of the decoder can be 3 to 8, 4 to 16, 4 to 10 s f decoders. Decoders have active low enable lines, which decide t when to turn it on. re t J ————— | Prob.l1 Explain address bus. Rta f rt Sol. Adiiress Bus : The address bus is a group of 16 tg! 9 generally’ identified as Ag to A,s. The address busi) th ‘unidirectional : bits flow in one mn from the MPU) peripheral devices. The MPU uses the address bus to perf) the first function : identifying a peripheral ot a memey Fig. 2:3 108 Decoder Logie Symbol with Enable location. i A decoder is commonly used device in interfacing VO peripherals and memory. Decoders are also built internal toa Ae = = =) € memory chip to identity individual memory register. e as as § Basic Binary Decoder : Suppose we wish to determine —- when a binary 1001 occurs on the inputs of a digital circuit. [ sae i = ‘An AND gate can be used as the basic decoding element | | sss P because it produces a HIGH output only when all of its inputs | |” | | | Supe Es are HIGH. Therefore, we must make sure that all of the inputs to the AND gate are HIGH when the binary number, zw < an i s 1001 occurs, this can be done by inverting the 2 middle bits = (the 0s). ° : s \ a ==) ‘ ° z 8 | Fig. : 8085 Bus Structure r — a Zosta In a computer system, each peripheral or memoy} : 7 sae J location is identified by a binary number, called an ade * oan) and the address bus i used to carry a 16-bit address. Ths for 1001 wth an Active-HIIGH Output | similar to the postal address of a house. A house can) * Ais the LSB and D is the MSB. In the representation | identified by various number schemes. For example, the fot| " re, ees rie cies weighted a rsp a fifth house in a lane can be identified by the two digit nunte! : a nent ane the top 1 45 or by the four digit number 0045. The two digit aumet most bit na vertical arrangement, unless speciitd otherwise. | ooo au identify only a hundred houses, fo aa o® Probi0 Explain microcoutrolien IRTUaN TRTU.2017) | Similarly, the number of address lines of the MPU detemiss its capacity to identify different memory locations ( Sol. Microcontroller It is a device that inclades Peripherals). The 8085 MPU with its 16 address i a !microprocessor memory and VO signal lines onasinglechip, | SaPsble of addressing 2° = 65,536 (generally known aso) fabricated using VLSI technology, ‘memory locations, As 1K memory is determined by ou! (a) Reprogrammable system. off 1024 to the nearest thousand, similarly, 65,536 i810 (b) Embedded system. off to 64,000 as a multiple of 1K. i Scanned with CamScanneryr and Interfaces “Tne number of address the designer of a microproces: 1 siderations as availability of pins and intended application sabe processor: FOr example, the Intel 8088 processor has Sy and pentium processor has 32 address lines, a1 Explain data bus. ere) Prot IR-TU.2017], tary, it nivied ‘sor based on such Fi pata Bus: The data bus is a group of eight lines wed fardata fw. These lines are bi-directional, data flows in feindirections between the MPU and memory and peripheral | fevees. The MPU uses the data bus to perform the second “S\ jpution: transferring binary information. 0 The eight data lines enable the MPU to manipulate 8-bit “Sy. ata ranging from 99 to FF (25= 256 number). The largest IG gg jamber that can appear on the data bus is 11111111 (258) 5 buy] he 8085 is known as an 8-bit microprocessoe MPU eroprocessors such as the Intel 8086, Zilog 28000 and Petig) Motorola 68000 have 16 data lines; thus they are known as nen) i6-bit microprocessors. The Intel 80386/486 have 32 data lines; thus they are classified as 32-bit microprocessors Prob.13 Explain role of flag register in Assembly Language Programming also describe various 4) Anes erate in 8085. 1R.7.0.2019, 09] I} 5 _),, Sol Flag Register :Flag register is a 8-bit special purpose ,) register. The role of the flag register in programming is that allihe conditional braiching operations are based on the four fags of the lag register as an example INC “addr” is based cathe carry flag. Ifthe carry flag value is CY = 0 then only tteprogram control will transfer to the given address otherwise thenext instruction will be executed. The flag register and five bits set and reset condition is shown below : Be ple? 14 t J casas Don't care [Fan arithmetic operation re: in carry, a carry flag is set (1). Otherwise it is reset (0). The carry flag also serves as a borrow flag for the sustraction, Thecarry flag solves the dual purpose of showing carry borrow in case of addition and substraction respectively. It is represented by D, bit of flag register. 2, Parity Flag (P): This flag bit (D,) shows the result of the arithmetic operation is having even number of ones (or) add. Since 8085 microprocessor follows even parity system so if the number of ones in accumulation after arithmetic operation is even. This flag is et (1) other wise itis cleared (0). _ 3. Auxiliary Carry Flag (AC):-In an arithmetic ‘operation when a carry is generated by lower nibble and passes toupper nibble, the auxiliary carry flag is set. This flag is used internally for BCD (Binary Coded Decimal) operations Dy bit of flag represents the AC flag. 4. Zero Flag (Z): The zero flag shows that the result of any arithmetic of logical operation is zero or non zero. The zero flagis set (1) when the result is zero otherwise itis reset (0). Zero flag is represented by D, bit of flag register. 5, Sign Flag (S): The sign flag is replica of the D, bit s set (1) if bit 7 of the reset is (1), represented by D, bit of flag register. ee Prob.l4 Explain the role of following in 8085- (@) Program Couiter (6) Stack Pointer IR-T.U.2019] {a) Program Counter : Program is a sequence of instructions, microprocessor fetches these instructions from the memory and executes them sequentially. The program counter is a special purpose register which, at a given time, stores the address of the next instruction to be fetched. Program Counter acts as a pointer to the next instruction. How processor increments program counter depends on the nature of the instruction; for one byte instruction it increments program counter by one, for two byte instruction it increments program counter by two and for three byte instruction it inerements program counter by three such that program counter always points to the address of the next instruction. In case of JUMP and CALL instruction, address followed by JUMP and CALL instructions is placed in the program counter. The processor then fetches the next instruction from the new address specified by JUMP or CALL struction. In conditional JUMP and conditional CALL fied, the processor Mer by three so that it points the Scanned with CamScanner‘struction fiflowed by conditional JUMP or CALL instruction; otherwise processor fetches the next instruction from the new address specified by JUMP or CALL instruct (D) Stack Pointer : It is a register that points to the top of the stack Stack is amemory area meant for specific purpose, This area should not be used for any other purpose. The stack works on Last in First Out basis, The stack pointer will be Aecremented when data or address is stored on the top of the stack. The stack pointer will be incremented whenever ‘he data or address is retrieved from the stack memory, The System makes use of the stack whenever there is a CALL instruction executed RET instruction executed, service ‘interrupt and returns from the interrupt service routine [Link] Explain the address BUS, data BUS and control BUS of 8085 microprocessor. Also draw the flag register, [RU 2015] OR Define and explain the Bus system Raj. Univ.2003, 2001, MREC 1996) OR Explain the function of vario us types of bitses in 8085 microprocessor in brief, IR-T.U. 2013} Sol. Microprocessor ted Operations and 8085 Bus Organization : PReMPU performs primarily out operations 1. Memory read : Reads data (or instruct tions) for Sig Tanster binary information (data and in "ep 3 : Provide timing or Synchronization signal. The 8085 Mpu Performs these functions ‘ation lines called buses struction), Is. es shown as one stem bus. This is called 3 tines G) Address Bus: Refer wp pray once @) Data Bus : - Refer to Prob. 12, 7 GB) Control Bus : The contro} Various signal lines that carry synehroni: to the bottom of the stack. The stack pointer will be- BrTech. (0 Sem) OS. Sale Fa MPU uses such lines to perform the third function : provi, ™ timing signals. nein bus, in relation to the contro signay somewhat confusing. There is no group of lines like adg or data buses, but individual lines that provide a pu}, indicate an MPU operation. The MPU generates Speci control signals for every operation (such as Memory or 10 Write) it performs. These signals are used to : identi a device type with which the MPU intends to comm Wunicate To communicate with a memory for example, toes 2 instruction from a memory location the MPU places 16-bit address on the address bus. The address on the busi decoded by an external logic circuit, and the memory locaton | is identified. The MPU sends a pulse called memory re Ry the contro signal. The pulse activates, the memory chipang | ¢ the contents of the memory location (8-bit data) are lace | on the data bus and brought inside the microprocessor } What happens to the data byte brought int fo the Mpy depends on the internal architecture of the microprocesso, Flag Register : Refer to Prob. 13, Prob.16 State the differences between sta ad BA LM, onthe capa \ M is more expensive to produce but requires lower power than DRAM. SRAM is generall; tower Benerally faster than DRAM must be creators slowly discharge due to salt is leaka: even “non-conducting” t tenga remanence ,j it SRAM Scanned with CamScanner_—— ol Laer ti wr — LT Single DRAM cell ow address Dernax: Selects Row Fig2 DRAM is the main memory (the “RAM”) in personal coniputers, workstations and video game consoles. SRAM exists as the fast “cache” memory in micro-controllers, microprocessors and to store the registers and parts of state- machines used in some microprocessor. a Prob.l7 How will you demultiplex. the address and databus? How can you interface 2048 KB RAM with 8085 microprocessor? Explain. (R.1.U.2014] Sol. On the 8085, pins 19-12(AD, — ADs) constitute the multiplexed address-data bus. Low order 8 bits of the memory (or VO) address appear on the AD bus during the first clock cycle (T; state of a machine cycle). During T, and T;, the ‘AD bus becomes the data bus. The signal ALE (Address Latch Enable) is high during T, and is used to latch these lower 8 address bits, using the on-chip latch of certain peripherals like the 8155. IC chips like the 8155 internally demultiplex the AD bus using the ALE signal. The ALE output of the 8085 is connect to the ALE input of 8155. Since a majority of peripheral devices do not have the internal multiplexing facility, there is external hardware necessary for it. Fig. 1 shows a schematic that uses a latch and the ALE signal to demultiplex the AD bus. AD;~ADp is, connected as input to the latch 74LS373. The ALE signal is, connected to the enable (G) pin of the latch, and the Output Control (OC) signal of the latch is grounded. When ALE 80s high during the T, state of a machine cycle, the latch is transparent in that the output of the latch changes according ‘o the input. The CPU is putting lower-order bits of address during this time. When the ALE goes low, the address bits 821s latched on the output and remain so until the next ALE signal, au AD, 2a hy 20 ; Toothery a2 renphstr AD, BO} An > From was . maisa73 Fig.t ‘The interfacing of 8085 with 2048 KB RAM isiflustrated in Fig. 2. ule LS “ Life ‘Ae input Data son vp -Lgadta. : Tul & .: od vig Ais~Ao, WR, RD, ALE signals are available from 8085. Ajs— Aj, may/may not be used to form CS signal to * select a particular 2048 KB memory. The 74LS373 is used to latch the lower-order address (A, — Ag) during T,. The output data/input data to/from the 8085 is connected to ‘Ag Ay (signals before the 74L$373 latch). Prob.18 Explain through block diagrams the similarities and difference in microprocessor, microcontroller and microcomputer devices, OR ‘Specify the terms microprocessor, microcomputer and microcontroller. —(R.¥.0.2008, Raj. Univ. 2003} OR Is there any difference among microprocessor, microcontroller and microcomputer? Explain. IR-T.U. 2014) Sol. Microprocessor : Refer to Prob.5. Microcomputer : A computer that is designed using a microprocessor as its CPU. It includes microcontroller ‘memory and input. Microprocessor cu Ts Mewory Iapat | Cup Fig. : Microcomputer + Refer to Prob.10, Scanned with CamScanner5 (Girech_ UV Sem CS. Solved Peper) es | Tips The difference between the follow Prob-19Esplain the function of various control andstamns | PT0D20. CMMI TT Mlcracontater signals available on 8085 microprocessor, R:1.2013] (i) Assembler and Compiler | : Gil) High level and low level language Sol. Control & Status Signals © (iv) RAM and ROM F299 There are 2 control signals (RD and WR) 91 | SF=—Thifterence between Microprocessor gy three status signals (10/M, S, Microcontroller: + i 7 of operation and one special signal, A Comparison Benen Miraprcnr and Marci the higher order and lower order addresses. : Microprocessor Le (a) ALE (Address Lateh Enable) : This signal is da : generated in starting of the 8085 operation and is | | 1, |Microprocessor contains | Microcontroller containg used to latch the lower order address from the JALU, general purpose |the circuitry of micro- multiplexed bus and generate a separate set of eigt register, stack pointer, | processor and in addition address lines A, A,, If this is one, address wi!l program counter, clock it has built-in ROM, be passed otherwise data will be passed throug timing circuit and RAM, /O devices, timers AD, ~ AD, : interrupt circui land counters. a 2, [Ithas many instructions |Tthas one or two () RD (Read) : This is an active low signal and is has on = ) bed Go read memory or 70 devie and data wil to move data between structions to move data be available oni data bus. This signal should be low memory and CPU. between memory and to perform the read operation. e CPU. — pea epeaae pas Tehas one or two bit [It has many bit handling (©) WR (Write) : A low on WR indicates that data handling insttutions. [instructions on the data bus which has ben placed on it by th | TTAoss times for memory [Less access mes or | f or VO operation, bias eaclaie : ‘and /O devices are more. |built-ini memory and VO. YO operat . devices. (d) 10/M : This is a status signal used to 5. |Microprocessor based {Microcontroller based between /O and memory operation. IFit is system requires more __ | system requires less operation and if low, memory operatio hardware hardware reducing PCB 1 combined with RD and WR to generate 1/O and |size and increasing the rriemory control signals. reliability (©) S, and §, : These are also status signals and used | |G. ]Mieroprocessor based Less flexible in design to identify various operations, according to the system is more flexible in| point of view. following table : design point of view. 5 Table + 8085 MF his Cae Str & Control Sigal} [7 lIthas single memory It has separate memoy Status ; map for data and code. _|map for data and code. Cyde : ‘ontrol Signals Machine Cycle“ T sg, | Control Signal 8. |Less number of pins are |More number pins are [Opeode Fetch] 0 [a fa multi-functioned, multifunctioned. < o tate 9. |Few bit hiding Many bit hiding information. information, ope 10. [High performance Low performance simple pipeline parallel CPU .|CPU Architecture. [170 Read TT. architecture, [170 Write ulronlaa Assembler and Compiler . Interrupt 1 }ada Ss. “Assembler ‘Compiler p lAcknowledge No. cam [Halt |Z To lo} 1. [Anassembler can be ‘Compiler is a compute to [Hold | z [xi{x and INTA jconsidered as a special —_| program that reads a W [Reset [2 Tx{x type of compiler which - | program written ina te Here Z=Tri-state/high Impedance ; translates only assembly language and translates it X=Unspecified Janguage to machine code. [in to another language. = . —— Scanned with CamScannerit produces an object code| Compiler usually x which might have to be| produces the machine linked using —_linker|executable code, directly program in order to run on| from a higher level machine, guage. Low Level Language Low level language ‘As we know that ®D is a control signal because this 1. [High fevel languages are |LLow level languages are easy to lear cult to lea sipnal is used both for reading memory and for reading as T | These are near toThuman | These are far from input devices. It is necessary to generate two different read language. human language, signals, One for memory read and another for input. Similarly, 3, [These are easy to Program in this language] } two separate write signals must be generated. modify are difficult to modify. “The diagram shows that four different control signals Execution of program is [Execution of program is srent co® = slow. fast. are generated by combining the signals RD, WR and 10/M, S, | These languages are | These languages are normally used to write [normally used to write application program. _|hardware program. ‘The 10/M goes low for the memory operation. This signal is. ANDed with RD and WR signalsby using 74LS32 quadruple the input or gate. The OR gates are functionally connected as negative NAND gates. When both the input signal goes. (x) RAM and ROM S] Feateres | RAM ROM No. | 1. | Elaboration | Random Access) Read Only Memory. low the output of the gates low and generate MEMR (Memory Read) and MEMW (Memory Write) control signals. When the input 10/M goes high, it indicates that L Memory [2] Memory External Memory. pheripheral 1/O operation. Figure shows that this signal is | complemented using hex inverter and ANDed with the 13. inj ¢ ROM onl; ae — — | ina % ne ROM ealy RDE&WR signals to generate TOR (VO Read) and 1OW 1}, (W/O Write) control signals. | | changes to the yr informatie 7 Type [I Static RAM | 7. PROM (SRAM) (Programmable ROM)| 2. Dynamic | 2. EPROM (Erasable RAM (DRAM) | Programmable ROM) 3. EEPROM (Electrically Erasable Programmable ROM) Prob.22 Explain the concept of multiplexing and De-multiptexing of buses. IRTU.2019} ——— Sol. The data bus and the low order address bus on the 8085 microprocessor are multiplexed with each other. This allows 8 pins to be used where 16 would normally be required. The hardware interface is required to de-multiplex the bus by Jatching the low order address in the first T cycle, on the falling edge of ALE. ‘The address bus is multiplexed in 8085, The multiplexing is done with the help of ALE signal. ALE stands for address latch enable. When ALE is High (Logie 1) : upper address -——— Prob.21 There are two types of read and write in ‘microprocessor Interfaces, such as Read and Write from/ 10 input device and ouput device as well as Read and Write fromho memory device. Explain how they are realized by only three pins in 8085, [R-TU, 2009} aeemmiamimmmeemes emma Scanned with CamScannerTines (line 15-8) and lower address lines line 7-0) combinely holds the 16 bits of the address. When ALE is low (Logic 0): Upper address lines (line 15-8) holds the upper 8 bit address. and Lower address lines (line 7-0) holds the "8 bit DATA", Multiplexing is used to reduce the number of pins of 8085, which otherwise would have been a 48 pin chip. But ‘because of multiplexing, extemal hardware is required to dde-multiplex the lower byte address cum data bus. The Pin no= 30 of 8085 is the ALE pin which stands for “Address Latch Enable’, ALE signal is used to de-multiplex the lower order address bus (AD, - AD,). Pins 12 to 19 of 8085 are ADp - AD; which is the multiplexed address-data bus. Multiplexing is done to reduce the number of pins of 8085. Lower byte of address (Ap - A;) are available from ADp- AD; (pins 12 to 19) during T, of machine cycle. But the lower byte of address (Ag - A>), along with the upper byte Ag-Aj5 (pins 21 t0 28) must be available during T) and rest of the machine cycle to access memory location or /O ports. Now ALE signal goes high at the beginning of T, of each machine cycle and goes low at the end of T, and remains ow during the rest of the machine cycle. This high to low transition of ALE signal at the end fT, is used to latch the Jower order address byte (Ag - A>) by the latch IC 74LS373, so that the lower byte Ag - A; is continued to be available tll the end of the machine cycle. The situation is explained in the following figure ; maisa73 (ae) Ank (Lower bye caress tis, ‘valle rom T stato ct each ‘machine cjie) achieved by the H to L. mn Of ALE signal, which occurs at the end of T, ofeach machine cycle ee Prob.23 Draw and explain the functional block diagram Of 8085 microprocessor along with the features in detail. IR.T.U. 2019) OR Draw the architecture diagram of 8085 microprocessor aud explain functions of various registers. [R-T.U.2015 OR Draw and explain the functional block diagram of gay, microprocessor. IRs Univ 2006, 2004 2002, 5, oR Draw the diagram of 8085 microprocessor architectuy, Explain the components. ITU. 2014 ae Lil BRS inea aba NMOS nlaronreosaen fr am Sol. Intel 8085 is an 8 bit, NMOS microprocessor. It isa 4g pin IC package fabricated on a single LSI chip. Control signals Tora Semi] Sonat conta ira tay Feeuna Feapoan] [Sane] rood [OC far [tee epee o [ee uth ashe Tesneton [SH ye Decode [bier sry Lope wit mecnent_|[Porm oer rc) Ince Ting & Cota a Pac Clock tad] Butler ‘Address Butter Fig. : Block diagrani of 8085 MPU ‘The intel 8085 uses a single +5V de supply for its operation. Its clock speed is about 3 MHz. The clock cycleis of 320 ns. The time for the clock cycle of the intel 8085 is 200 ns. It has 80 basic instructions and 246 opcodes, Fig. shows the block diagram of intel 8085. Itconsiss of three main sections, an i and control unit and several regi are described below: 1. ALU The arithmetic and logic unit (ALU), performs the following arithmetic and logic operations. isters. These important sections [Link] 2. Subtraction 3. Logical AND 4. Logical OR 5. Logical Exclusive OR 6. Complement (Logica! NOT) 7. Increment (add 1) 8. Decrement (subtract) 9. Left shift (add input to itself) 2. Register Array a, ‘er is a group of predefined memory locatio® used to store data and result. 8085 has got three types of registers: (a) General Purpose Registers (GPR) : Refer ” Prob.d, 10. Clear Scanned with CamScanner(b) Temporary + Wand Z are temporary registers which are ‘not available for’ user. "To perform arithmetic and logical operations, microprocessor assumes ‘one data is available in accumulator and takes another and then performs operation on the 2:data bytes. Temporary registers are used by microprocessor for internal operations to store operand, immediate operand or address of memory: (© Special Purpose Registers : 8085 microprocessor contains three special purpose registers which are Program Counter (PC), Stack Pointer (SP) and Increment/ Decrement Latch. i) Program Counter (PC) : Refer to Prob, 4(a). il) Stack Pointer (SP) : Refer fo Prob.14(b).. 1, Gil) Increment/Decrement Latch: This is-also a 16-bit register used to inerement or decrement the contents of SP. and PC registers. Address buffer and address/data: buffers are used in co-ordination with these registers. Address buffer is an 8 bit unidirectional buffer used for A,,— A, address lines. When they are not used, buffer is used to’ tri-state these lines. Address/Data buffer is an 8-bit bidirectional buffer for addressidata lines AD,~AD, under certain conditions (reset, hold, halt). 3, Interrupt Control This block is responsible for accepting different interrupt request inputs such as TRAP, RST 7.5, RST 6.5,; RST 5.5 and INTR. Interrupts are generated to interrupt the execution of program. When a valid interrupt request is present, it informs control logic to take action in response to each signal. : 4. Serial /O Control Groups The data transferred via D, to D, lines is parallel data, but under certain condition it is advantageous to use serial data transfer (bit by bit transmission). Microprocessor 8085 uses SID and SOD signals to transmit data serially. The data ‘on these lines is accepted or transferred under software control by serial 1/0 control blocks. 5. Instruction Register, Decoder and Control Group. Instruction Register : When an instruction is fetched from memory, it is loaded in instruction register and that instruction is provided to decoder for decoding. This register is only activated when an instruction code or OPCODE is available on internal data bus. It is a non-programmable register. Instruction Decoder : This accepts a bit pattern from instruction register, decodes it and gives the decoded information to control logic. The information includes what operation is to be performed, who is going to perférm it, how ‘many operand bytes the instruction contains ete. ‘Timing and Control Unit : It contains an oscillator and a controller sequencer. Oscillator is responsible for generating clock signals to synchronize all registers and Peripherals for communication _to_the_microprocessor. Controller sequencer accepts information from instruction decoder and generate control signals for internal or external control. RD and WR are sync pulses indicating the availability of data on the data bus. Prob.24Draw pin diagram of 8085 and explain each pin. IRTU.2017] OR Explain the following pins in relations to 8085 | microprocessor. () ALE (i) READY «, ii), Sy and Sy (iv) 10/M {R-.U. 2015) Sol. PIN Diagram of 8085 Microprocesso microprocesot isa 8 bit general purpose microprocessor h: 40 pins and works on +5V sirigle power supply. Stomp t 40 Wee x, G2 39 [uo aneserour: C] 3 38 Jutpa sop, C4 37 Fetx our so Cs 36 [RESETIN reap [| 6 35 DJREADY reps ]7 34 [om rstes C8 3s: rstss E] 9 32D itr E}i0 uae 31 [WR nm Cu 30 [ate ap, Ez 2» Fs, ap, Es 2a, ap, Elis 2a, ap, C15 26 DA, ap, Efi 23 Da, ap, C17 Pa, ap, Eis 23a, av, Civ 2a Vs C20 aa, 8085 PIN out Fig. PIN Diagram of 8088 Functions of Various Pins 1, Pin No. O1, 02 (X,, X,) : A crystal either RC or an LC network is connected at these two pins. The frequency is internally divided by two. Hence to operate the system at 3MHz, the erystal should have a frequency of 6MHz. Scanned with CamScannerNo. 03 (RESET OUT): This signal indicates that the microprocessor unit is being reset. Th Signal can be used to reset other devices. 3. Pin No, 04, 05 (SOD, SID) : These are the serial input / output ports. The 8085 has two signals to implentent the serial transmission SID (Serial Input Data) and SOD (Serial Output Data). In serial transmission data bits are sent over a single line, one bit ata time such as the transmission over the telephone lines, 4. Pin No. 07, 08, 09 (RST 7.5, RST 6.5, RST rt interrupts, These are vectored interrupts that transfers the program control to specific locations. They have higher priorities than the INTR signal, S. Interrupt : Interrupt is an external signal which is generated by any peripheral. The 8085 mieroprocessor has five interrupt signals that can be used to interrupt a Program execution. The various interrupts are as follows : (@ Pin No. 06 (TRAP) : This active high ifp signal ‘TRAP isnon maskable interrupt and has highest priority. When pin goes high MPU goes to interruption state (stores the ‘execution instruction, + TRAP is atomatically vectored transferred. *+ Program counter will be transferred toa specific memory call location, + Call location of TRAP interrupt is 0024 1. Italso isa active high edge triggered interrupt, Which means I/P should go high and stay high to be 5 acknowledge. Gi) Pin No. 10 (INTR) Interrupt request : This is used as a general purpose interrupt. i) Pin No. 11 (INTA) : This is an output signal and is generated by microprocessor to acknowledge and interrupt. This is known as interrupt acknowledge pin, 6. Pin No. 12 to 19 (Multiplexed Address/Data bus) and Pin No. 21 - 28 A, — A,, (Address Bus) : The 8085 microprocessor has 16 signal lines are used as address but; however, these lines are split into segments A,,~A, and tunidirectional and used forthe most significant bits called higher order address of a 16 bit addres The signal lines AD, = AD, are used for a dual Purpose i. they are used as the lower order address bus 9s well as the data bus. During the later part of the eyele, they are used as data bus (this is known as multiplexing the bus), However, the low-order address bus can be separated from these signals by using a latch, Pin No, 20 (V,,) : Iti foprocessor. mi Pin No. 31 (WR ~ Write) : This is a write contro, memory of input output location, in No. 32 (RD — Read) + This is a read conteoy signal and is active low. This signal in ative condition indicates that the selected inpuvoutput or memory device isto be read and data are available on the data bus. Pin No. 36 (]@ESETIN) : When the signal on this pin goes low, program counter is set to zero, the buses are tristate and the microprocessor unit is reset. Pin No. 37 (CLK OUT : Clock Output) : This signal can be used as the system clock for another devices, Pin No. 38 (IILDA - Hold Acknowledge ) : To respond the HOLD request on PIN 38, the 8085 j1P has one signal called HLDA. This active high O/P signal when MPU receives hold signal from extemal device. It will send a request to device ie. it receives the request and gives the control of buses to external deviee. 1 access. n is used in data transfer through a direct memory P . No, 39 (HOLD) : When the HOLD. pin is Activated by an external signal generated by peripheral, the microprocessor relinquishes the control of address and data buses and allows the requesting peripheral to use them. Pin No. 40 (V,) # Itis a SV power supply for 8085 foprocessor. : Pins in Relations to 8085 Microprocessors : @ ALE : Refer to Prob, (i) Readly + The 8085 microprocessorhas a pin called READY. If the signal at this READY pin is low,.the tnictoprocessor enters into the wait state, The signal is used Primarily to synchronize slower peripherals with the tnictoprocessor. This signal actually delays the microprocessor Read or Write eycles until a slow responding peripheral is ready to see or accept data, i) S, and Sy : These are status signals, These caf identify various operations, but they are rarely used in small systems, (i) 107M This is a status signal aid is used 0 differentiate between inpuvoutput and memory operations ‘This signal is combined with RD (read) and Wie (write)! ‘generate input / output and memory control ignal Scanned with CamScannerProb.25 Define following (a) Program counter (b) Stack pointer (©) General purpose programmable registers = (d) Instruction register (©) HOLD and HLDA pin O Control and status ping (g) Flags (i) PSW n 8085 Microprocessor : Sol(a) Program Counter : Refer to Prob.14(a). (b) Stack Pointer : Refer to Prob.14(b). (©) General Purpose Programmable Re; 10 Prob.d. (@) Instruction Register : Refer to Prob.23. (©) HLDA Pin : ‘Refer to Prob.24, HOLD Pin : Refer to Prob.24. (0 Control and Status Pins (Bus) lata transfer from V/O. (rrsae transfer from memory. by measuring logic one that we can ‘hs find out which machine cycle going ers : Refer 1 lo/M= 2. on inside the microprocessor. 3 WR operation can be performed. 4. RD = 0= read operation can be performed. 5. WR and RD does not operate simultaneously, WR=0) — | Wrong RD=0 WR Ri ‘ Right 6. Mixed directional ‘ALE (Address Lateh Enable) = 1 = Apo ~Ap7 as address pins 0 => Apy — Ap7 as data pins Latch 7418373 D-flip flop buffer ALE = 1 = Apg— Apy as address line ALE = 0.= Apo - Apy as data wer order eight bins of address pins work also as data pins, Fig. : Block diagram showing ALE Action Multiplexing and demultiplexing of lower order eight pins of address pins as data pins is time diversion multiplexing. (g) Flags : Refer to Prob.13. (h) PSW : The program status word consists of five status flags. These are described below : (i) The carry flag (Cy) reflects the final carry out of the most significant bit of any arithmetic operation. Any logic instruction resets or clears the carry flag. This flag is also used by the shift and rotate instructions. The 8085 does not have any CLEAR CARRY instruction. One way of clearing thg carry will be by ORing or ANDing the accumulator with itself. (ii) The parity status flag (P) is setto 1 if arithmetic or logic instruction generates an answer with even parity, that is, containing an even number of | bits. This flag is 0 if the arithmetic or logic instruction generates an answer with odd parity, that is, containing an odd number of Is. Gi) The auxiliary carry flag (Ac) reflects any carry from bit 3 to bit 4 (assuming 8-bit data with bit 0 as the least significant bit and bit 7 as the most significant bit) due to an arithmetic. The auxiliary carry flag (Ac) reflects any carry from bit 3 to bit 4 due to an airthmatic operation. This flag is useful for BCD operations. (iv) The zero flag (Z) is set to 1 whenever an arithmetic of logic operation produces a result of 0. The zero flag és cleared to zero fora non zero result due to arithmetic or logic operation (¥) The sign status flag (S) is set to the value of the arithmetic or logic operation. This provides a range of -128). to +127, (with 0 being considered positive) as the 8085°s data-handling capacity ‘The 8085 does not have an overflow flag. Note that execution of arithmetic or logic instructions in the 8085 affects the flags. All conditional instructions in the 8085 instruction set use one of the status flags as the required condition. SL Scanned with CamScannermultiplexed pins of 8085 Explain with block diagram “ADO-AD7 pins of 8085 Prob.26 (a) Define Microprocessor. Demuttiplexing of using tri state gates. (b) Find memory map of Memory chip. of] anf! Sol.(a) PIN Diagram of 8085 Microprocessor Prob. 24. : Sol.(b) The 2K memories IC have 11 address lines Ayo-Aqy Which are used to locate the memory location where data will be stored or read. The other address lines Ajy-Ays of the microprocessor can be used for the chip select signal. The memory map of 2K memories is given below: ; a o fas ° ar ° S ° Aw] 0 a ° oo ° a ° ay ° a 0 Aw 0 an] ° aw ° ° a ° ° =oonott =onre ————————— Prob.27 Explain the need to demultiplex the bus ADg AD, IR-TU.2015] OR Define and explain the demultiplexing of address-data bus of 8085. [RTU.2010] OR Why are AD,— ADs lines multiplexed? With the help of latching circuit, explain how these lines are demultiplexed. —\R.U.2013, 09,2008, Raj. Univ, 2008, 2002] Sol. Need of Multiplexing : Refer to Prob.3. Demultiplexing the Buses : AD, ~ AD, are used in ‘multiplexed mode, they carry both data and address. Within a fetch eycle the address is sent during the first state of the the following 2 KB, memory location i read and during the third state the conte je transferred into the microprocessor through the same AD,- AD». Jines/pins.. The address/data bus, AD, ~ AD,, is rectional where asthe address bus A, ~A,, is unidirectiong, it In 8085 the higher order address lines are dedicated 19 ‘carry the higher order addréss but the lower order address Tines are multiplexed with data bus. Thus, we can say thatthe need to demiltiplexjhe bus AD,—AD, arises due to following reasons é 1. AD, ~/AD, bus are demultiplexed in 8085 ieroprocessor to provide individual 16-bitaddress lines and S:bit data lines. As these lines are multiplexed, number of pins required are less'so hardware cost is less. 2, Timing : Transfer of byte from memory to MPU diagram, shows that address on the high order bus (20H) remains on the bus for three clock periods. However the low ‘orderbus (50 H)is lost after the first clock period. Thisaddress needs to be latched and used for identifying the memory address. Ifthe bus AD, ~ AD, is used to identify the memory location (2005 H), the address will change to 204FH afterthe first clock period. 3. The need for demultiplexing the bus AD, ~ AD, becomes easier to understand after examining, To do this demultiplexing first we see how long multiplexed address/data is available on AD, - AD, During T, state of every machine cycle AD,-AD, lines camry the address part. In this T state ALE signal is also high to indiete address on these lines. After T,-state microprocessor 8085 will remove the address contents from AD,-AD, lines and use these lines as data lines for next clock cycle onwards. Ot ® re oy, meed 2 es ms won : os soo Me ls _12}-+00, (OE Ouput erase Je, During the second state the content of the specific ygram of D-latch 8282 Scanned with CamScanner3 The demultiplexing of these lines is done gebit D-lateh IC (shown in geshown in Fig. 3, When AL byu 2 )along with the ALE signal ishigh the address signals will get latched in 8-bit Tateh and the output of latch will provide will nes AvA, address contents, When ALE is low for data sable the latch from aceepting contents from AD,-AD, and the same lines ean be used as data lines, - Pep tes rl Fs mat ts Fe = I = = rapt. Demultiplexing of AD,-AD, Here, inthe circuit the D-FF(Flip Flop) are triggered by the ALE signal. When these FFs are triggered their output ‘becomes equal to the input which is nothing [Link] at this moment. Now when even if the ALE signal goes down these FF retain the address component at their output for peripheral addressing. The tri-stated buffers are used just to increase the driving capabilities of the buses. Prob.28 Write comparison between memory mapped VO and peripheral mapped 1/0. [-T.U. 2012), OR Explain the difference between the peripheral YO and the memory mapped 1/0. Define logic and “plain the functions of following devices : “ @ Buffer (6) Decoder, (¢) Encoder (d) Latch IR.T.U, 2008, Raj, Univ, 2002] oR What is Peripheral 1/0 and Memory-Mapped ? Differentiate between them, Raj, Univ.2007, 2004) 80. Peripheral 1/0 and memory mapped 1/0 : The input ‘hniques are applied on input devices. ‘The input devices are the devices through which the MPU com jicates with * user or the outside world. There are two different methods ‘hich input devices ean be identified. 1. Inputs with 8-bit addresses or peripheral ‘mapped input or input mapped input : In this the MPU, uses eight address lines to identify an input oran output device. This is an 8-bit numbering system for inputs used in conjunction with input and output instructions. This is also known as input space separate from memory space, which is a 18-bit numbering system. The eight address lines can have 256 (2 combinations) address, thus, the MPU can identify 256 input devices and 256 output devices with address ranging from 00 to FH. The input and output devices are differentiated by control signals, the MPU uses the input read * control signal for input devices and the output write control signal for output devices. 2. Input with 16-bit address or memory mapped input: In this type of input, the MPU uses 16 address lines to identify an input device. An input is connected as ifét is memory register. The MPU is connected as if't is a memory register. The MPU uses the same control signal (Memory Read or Memory write) and instructions as those of memory. In memory mapped input, the MPU follows the same steps as if itis accessing a memory register. Sequentially from floor to floor instead of moving from floor to floor as requested, the head is moved to access files in the sequence they are located on disk tracks rather than strictly in the sequence they were requested. (@) Buffer : When the output current of a digital device is insufficient to drive another device, which is to be connected to the output terminal of the digital devices, a buffer is used to increase the current rating. A buffer increases the output current. A buffer is represented by a triangle. For an inverting buffer a bubble is put at the output point of the iangle, Sometimes, a change in voltage level is required to interface lamps, relays etc. This is also achieved by suitable buffers/drivers, Thus we see that the function of buffer/driver to change the current/voltage levels. Following table shows important buffer/drivers. Buffer/Driver ICs wo scription 7406, 7816 Hex hiverter Butter/Drivers with open collector outputs. 7407,7417 Hex Butfer/Drivers with open collector outputs 74125 Quad Bus Buffers Gates with 3-state outputs, output is enabled when C is low. 74126 Quad Bus Buffers Gates with 3-state outputs, outputs is enabled when C is high. 74240 Octal buffers/Line Drivers/Line Receivers, inverted 3-state outputs. 74241, 74244 Octal Bulfers/Line Drivers/Line Receivers, Non-inverted 3-state outputs, 1426,7437 Quad 2-i Scanned with CamScannerQuad 2-input NAND Buffers with open collector outputs. 7440 Dual 4-input NAND Buffers. 7428 Quad 2-input NOR Buffer. 7433 Quad 2-input NOR Buffer with open . collector outputs. 74128 Quad 2-input NOR Line Drivers. @® and (© Decoders/Encoders : A digital computer, microprocessor based system or any other digital system uses binary numbers for its operation. They understand information composed of only 0’s and 1’s. The user is allowed to use decimal numbers and alphabetic characters while working ‘ona digital system for his convenience. A suitable interfacing circuit is used to convert decimal numbers alphabetic character to proper binary forms required by the digital system. Various kinds of binary codes are used by digital systems such as BCD (Binary coded decimal), Hexadecimal, Octal, Excess-3, Gray code, ASCII, EBCIDC, etc. The function of an encoder is to generate a binary code, the process of generating binary codes is known as encoding. ‘The decoding is the reverse process of encoding, TCNo. Deseri Taai, Ta14aT BCD to Decimal Decoders? Drivers, open collector outputs, Nixie tube driver. 7442 BCD to Decimal Decoders/ Drivers, totem pole outputs, LED driver, BCD to Decimal Decoders/ Drivers, Open collector outputs, Indicator/Relay driver. BCD to 7-Segment Decoders/ Drivers, active low, open collector outputs, 30V outputs. BCD to 7-Segment Decoders/ Drivers, active low, open collector outputs, 15V outputs. BCD to 7-Segment Decoders/ Drivers, internal pull-up outputs, active high. BCD to 7-Segment Decoders/ Drivers, open collector outputs, . active high, The examples of encoder ICs are 74147 Decimal to BCD encoders. 74148 and 74348 Octal to Binary encoder The hexadecimal to binary encoder is realized using two 74148 and a data selector. Examples of decoders are : BCD to clecimal decoder/driver, BCD to 7-segment decoder, (A) Latch :A flip-flop in its simplest form is ealled a latch. A latch stores a binary bit 1 or 0, the unclocked simple flip-flop 7445, T4145, 74445 7446, 7426 7447, 74247 7448, 74248 7449, 74249 and level-triggered R-S and D flip-flop fall under the cate oflatches, An n-bit latch is composed of n number of tty latches. The n bits of a binary word are transferred to latch simultaneously in parallel. There is no facility to reag contents, The latches are used as temporary storage devi They are ideally suited for storing information bet processing units and V/O devices or indicating devices, Difference between peripheral 1/0 and mapped Yo , ‘Characteraties | Memory Peripheral Mapped 10 [T-Daviee Jie bit address 2. Conwot Signal | MEM TOR TOW for input / Outpt] ex Memonteated Nand OUT instructions such as STAX; MOV. IM. R: ADD M; [SUB M; ANAM. lg Data Transfer [Between any register and vO [Tnsretion Oaly baiween TO and the sccumulatr Iz. Maximum no, [Thewemony map |The /O map is Ja Os posible |(GiK)is shared independent of the’ lpeweem 10s snd | memory map; 286 system mcmory. |impat devices and 256 devies output ean he connected ie Exeswton IS T-siaes [10 Tstates Speed ISTA,LDA of T- as sates (MOV a Ry “TTladware |More hardware [les hardware Requirements |nceded vo decods {needed to decode 8 To-bitadiess [bit addres, Other Peaaves [Anthmetic or [Not availabe logical operation can be drectly petformed with 10 data ——— Prob.29 (a) Why a microprocessor needs ROM and RAM? Write the procedure to communicat with memory by a microprocessor. RT. ) Explain the function of flag register in MP 8085. What is the use of the general purpost registers CY and Z? {R.T.U. 20111 ee Sola) . Memory Organization of 8085 : Microprocess is an useless chip without peripheral and memory ust Memory unit plays an important part in the operation oft roprocessor. Memory refers to any device that stor information for later use. ‘The memory of a computer can be divided into categories, they are 1. Primary or Main Memory 2. Secondary or Mass Storage Device i Primary memories are semiconductor memoti®® Commonly tised Scanned with CamScannerPicoeasor on terface, 7. Read Only Memory (ROM) 2. Programmable Read Only Memory (PROM) 3, Electrically Alterable ROM (EAROM) 4, Random Access Memory (RAM) or Read/Write ‘Memory (RWM) Allthe above memories are random access memories, Any bit stored in these memories may be accessed directly. Memories, in general, are classified on the basis of several attributes. ROM is the acronym for ‘Read Only Memory’ ROM is an internal memory in the computer which used to store critical information required by the computer like booting programs. They are prerecorded and are read only. RAM is the acronym for "Random Access Memory’ : RAMisanother form of internal memory. RAMsiare used to store temporary programs that are currently being executed. They come in large sizes of 4GBs and higher. They are accessible and can be changed. Procedure to Communicate with Memory by a Micro-processor : Generally, a microprocessor performs four different operations : memory read, memory write, input/output read ut/output write. In the memory read operation, data will be read from memory and in the memory write operation, data will be written in the memory. Data input from input devices are 1/0 read and data output to output devices are VO write operations. ove Bevis -——> Meepcossr | (Memory Fig. 2 shows the memory read operacion. Initially, the microprocessor places a 16-bit address on the address bus. ‘Then the external decoder logic circuit decodes the 16-bit address on the address bus and the memory location is identified. Thereafter, the microprocessor sends. MEMR control signal which enables the memory IC. After that, the content of the memory location is placed on the data bus and also sent to the microprocessor. Fig. 3 shows the data flow diagram for data transfer from the memory to microprocessor. The step-by-step procedure of data flow is, aiven below : Teena Re ‘Memory read operation a vrenacan ary Oven [JL Fig, 1: Bus structure of 8085 microprocessor ‘The memory read/write and Input/Output read and write operations are performed as part of communication between the microprocessor and memory or Input/Output devices. Microprocessors communicate with the memory and 1/0, devices through address bus, data bus and control bus as, depicted in fig.1. For this communication, firstly the ‘microprocessor identifies the peripheral devices by proper ‘addressing, Then it sends data and provides control signal for synchronization. Fig, + The 16-bit memory address is stored in the program counter. Therefore, the program counter sends the 16-bit address on the address bus. The memory address decoder is decoded and identifies the specified memory location. + ‘The control unit sends the control signal RD in the next clock cycle and the memory IC is enabled. RD is active for two clock periods. }: Data flow from memory to microprocessor Scanned with CamScanner+ When the memory IC is enabled, the byte from the ‘memory location is placed on the data bus AD,-AD,, After that data is transferred to the microprocessor: Sol.(b) Flag Register : Refer to Prob.13. Prob.30 Define and explain the following : (a) Microprocessor and Microcontroller (®) Machine and Assembly Language |R-T.V.2010] Sol.(a) A semiconductor device (integrated circuit) manufactured by using the LSI techniques. It includes the ALU, register arrays and control circuits on a single chip. ‘The term MPU isalso synonymous with the microprocessor. ig ind Block diagram of a microprocessor pops a 1) Ses ew | Tn t ‘Stack oi Sout ty) painter | S ROM = sou] [tam imate [sx | [se] [ex | [ee | Fig. 2: Block diagram ofa microontoler Microcontroller is a single chip microcomputer. The word lengths of a micro computer may be 8 bit, 16 bit, ‘32 bit, or 64 bit. It is generally used in traffic lights, aeroplanes, and radar etc. A microcontroller differs from a microprocessor in several important ways. Early name for a microcontroller was micro computer. The main difference between a microprocerssor and microcontroller isthe completeness the machine each represents. In order to puta microprocesgy (use the designer required memiory peripheral chips yy serial and parallel ports to make completely funtional com, On the other hand a complete computer based system coy be build using a single chip microcontrollers, with a minim, ofexternal components, Fig. shows simplified block di ‘ofa microprocessor, which consists of an arithmetic and lg, unit (ALU), general purpose registers, stack pointer (Sp) program counter (PC), clock timing circuit and intern, circuit. To make a complete microcomputer system only microprocessor is not sufficient but tis required to add othe peripherals such as read only memory (ROM), readhing memory (RAM), decoders, drivers, number of input/outpy devices to make a complete microcomputer system. [y addition, special purpose devices, such as interrupt controle, programmable timers, programmable I/O devices, DMA controllers may be added to improve the capacity ang performance and flexibility of a microcomputer system. The microcontroller incorporates all the features tht found in microprocessor, apart it has also added features to make a complete microcomputer system on its own. The microcontroller has built-in ROM, RAM, parallel 1/0, seril VO, counters and a clock circuit. Fig.2 shows the simplified block diagram of a microcontroller. fable : Comparisons between Microprocessor and Microcontroller : Refer to Prob.20(). Sol.(b) Machine and Assembly Language Machine language All digital circuits can identify only two possible stats and which can be specified by 0°s and I's. Hence, microprocessor also can be instructed only using combination of 0's and 1’s. Such a language, which comprises of 0'sand -l’sis called machine language. The speed of execution of machine language is fest | | is directly understood by the computer. Programmingis | difficult and time consuming. Programmer has to search et | | the binary code for any task for perform. Assembly Language To overcome the difficulty of machine langues’ assembly language was designed, in which each statewe®! of machine language was written in some set of charaéte’s which are easier to understand called mnemonics. TH program which converts assembly language to machité language is called assembler. 8 ang asi SS Prob.31 What are ASCII code, BCD code, signed unsigned integer ? Clearly specify how do you work ‘these numbers in microprocessors ? RT 2 ee Scanned with CamScanner-ssor and Interfaces ASC and Unicode Data : ASCII (American Standaéd ‘ge for Information Interchange) data represents sposnumei characters inthe memory ofa computer system ‘rable 1). The standard ASCII code is a 7-bit code, with Gecighh and most significant bit used to hold parity in some tigated systems. IF ASCII data are used with a printer, ge most significant bits area 0 for alphanumeric printing and for graphics printing Inthe personal computer, an extended sclicharacter set is selected by placing a1 in the leftmost tit Table 2 shows the extended ASCII character set, using ode SOH-FFH. The extended ASCII characters store some reign letters and punctutation, Greek characters, jathematical characters, box-drawing characters and other special characters. PPiELELEE PEEL TER Fst x0 ‘Second xt X4 XS X6 X7 XB XC XDXE XF = Der rsmee mem © awtenore xa . 3 0 ! a erecwo-m x sg gece qomee gata eee X23 oev sag aca BES 16g ze ey ry ore RNLQRRLRER Auel noone caine ese sue oed mes 8 Note that extended characters can vary from one printer to another. The list provided is designed to be used with the IBM Proprinter, which also matches the special chafacter set found with most word processors. “The ASCII control characters, also listed in Table 1 perform control functions in a computer system, including clear sereen, backspace, line feed, and so on. To enter the control codes through the computer keyboard, hold down the Control key while typing a letter. To obtain the control code O1H, type a Control-A; a 02H is obtained by a Control-B and soon. Note that the control codes appear on the screen, from the DOS prompt, as “A for Control-A, ” B for control-B and $0 forth. Also note that the carriage return code (CR) is the Enter key on most modem key-boards, The purpose of CR is to return the cursor or print head to the left margin. Another code that appears in many programs is the line feed code (LP), which moves the cursor down one line. To use Table | or 2 for converting alphanumeric or control characters inito ASCI characters, first locate the alphanumeric code for conversion. Next, find the first digit of the hexadecimal ASCII code. Then find the second digi For example, the capital letter “A” is ASCII code 41H and the lowercase letter “a” is ASCII code 61H. Many windows- based applications, since Windows 95, use the Unicode system to store alphanumeric data, This system stores each character as 16-bit data. The codes 0000H-OOFFH are the same as standard ASCII code. The remaining codes, 01002H-FFFFH, are used to store all special characters from many world wide character sets. This allows software written for the Windows environment to be used in many countries around the world. BCD (Binary-Coded Decimal) Data Binary-coded decimal (BCD) information is stored in either packed or unpacked forms. Packed BCD data are stored as two digits per byte and unpacked BCD data are stored as cone digit per byte. The range of a BCD digit extends from 0000, to 1001, or 0-9 decimal. Unpacked BCD data are returned from a keypad or keyboard. Packed BCD data are used for some of the instructions included for BCD addition, and subtraction in the instruction set of the microprocessor. Table [Link] some decimal numbers converted to both the packed and unpacked BCD forms. Applications that require BCD data are point-of-sales terminals and almost any device that performs a minimal amount of simple arithmetic. If a system requires complex arithmetic, BCD data are seldom used because there is no simple and efficient method of performing complex BCD arithmetic. ‘Table 3: Packed and unpacked BCD data Decimal Packed Tayockad 12 O00T 0010 ‘600 GOOI ooo COTO 623 00000110 0100011 000110 oo00G010 o0000011 53100000 1001 001.0000 00001001 00000001 _0000 0000 Byte-Sized Data . Byte-sized data are stored as unsigned and signed integers. Figure illustrates both the unsigned and signed forms of the byte-sized integer. The difference in these forms isthe weight of the leftmost bit position. Its value is 128 for the unsigned integer and minus 128 for the signed integer. In the signed integer format, the leftmost bit represents the sign bit of the number, as well as a weight of minus 128, For example, 80H represents a value of 128 as an unsigned number; as a signed number, itrepresents a value of minus 128, Unsigned integers range in value from 00H to FFH (0-255). Signed integers range in value from -128 to 0 to + 127. Although negative signed numbers are represented in this way, they are stored in the 2’s complement form. The, method of evaluating a signed number by using the weights, Scanned with CamScannerof each bit position is much easier than the act of 2's complementing a number to find its value, This is especially ‘rue in the world of calculators designed for programmers. wee ray wets re oO ee knees Some Fig. : The unsigned and signed bytes illustrating the weights of ‘ach binary-bit position ‘Whenever a number is 2's complemented, its sign changes from negative to postive or posite to negat ‘example, the number 00001000 is + 's found by two's complementing the +8. To form a two's complement, fist one's complement the number. To one’s complements number, invert each bit ofa number from zero to one or from one to zero. Once the one’s complement is . For 8. Its negative valive (-8) formed, the two's complement is found by adding a one , the one’s complement. Example 1 shows how numbers ay 2's complemented using this technique. Example 1 +8= 00001000 11110111. (1's complement) + 1 1111000 (2's complement) Another, and probably simpler, technique for 2, complementing a number starts with the rightmost digit, Stay by writing down the number from right to left. Write the number exactly as it appears until the first one. Write dowg the first one and then invert all bits to its left, Example 2 shows this technique with the same number as in example',{g Example 2 i +8=00001000 r 1000 (write nuniber to first 1) F III nvert the remaining bits) ~8=11111000 8 goo 2 So > Sf Jf JZ nO Scanned with CamScannerAssEMBLY LANGUAGE PROGRAMMING 2 Cxapter in A NUTSHELL “| i 5 Assembly Language sg.) Amediumof communication witha computer in-which vo rams are written in mnemonics. An assembly langtiage nie pecifictoa given computer i "a esti \n Set : All the instructions are described fully | ntems of its operation and the operand, including details Example such as number of bytes, machine eycle, T-states hex code | opcode Operand — Byte Mecycle ‘TStates Hexcode and affected flags. ACL S-bitdata 2 2 7 cE ‘The various abbreviation used- Reg. 8080A/:8085 Description : The 8-bit data (operand) and the carry | Register. flag are added to the contents of the accumulator and the Mem = Memory Location result is stored in accumulator. Qq Q Program Structure : These are of 3 types. (i) Sequential : A program with top location approach, without much complexity. (ii) Conditional : Conditions are applied in the form of conditional loops and counters, XX =Random Information (iii) Iterative/ Recursive : Some execution of a 2 Flags : All flags are modified to reflect the result of program counter for a finite number of times. addition. data) can be specified in various ways. It may include 8-bit (or 16-bit) data, an internal register, a memory location, or 8- bit (or 16-bit) address. In some instructions, the operand is implicit. Instruction Set : All the instructions are described fully in terms of its operation and the operand, including details such as number of bytes, machine cycle, T-states hex code and affected flags. The various abbreviation used- Reg. 8080A/ 8085 Register. |Prob.1 Define instruction & instruction set. |R-T.U.2019] —_—————eeeeeeeEeEEeEEEmN Sal Instruction : An instruction is @ command to the icroprocessor to perform a given task on a specified dat | Ech instruction has two parts: one is task to be performed, ‘alled the operation code (opcode), and the second is the 4a to be operated on, called the operand. The operand (or Mem = Memory Location Scanned with CamScannerRy = Register Destination M = Memory () = Contents of XX = Random Information aS Prob.2 What isthe rote of accumulator in Microprocessor? IR. 2019], i Sol. Accuimulator : The accumulator is a 8 bit general purpose register connected to internal data bus and to ALU. Itis also called as a register. It is used in mostof the arithmetic and logical operations. After performing an operation, the ALU places its result on intemal data bus, from there it is generally stored in accumulator. BrFech. 1 Sem) C5. Solved Pepe 10001011 00000110 70010001 ADDB 8B DAA A MOVG, A 1 ac Prob.S Compare the function of the RST and RET, RAY. ——— Sol. Comparison between RST and RET instructions RST Ss. RET No. Prob.3 Find the content of ‘C’ register after execution of the following assembly language program. MYA, 7H Loop: RLC INC Loop: MOVC, A HLT IR-LU. 2016), Sol. 17-000101110 RLC: Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of DO as well as in the Carry flag. CY is modified according to bit D7. Any other bit is not affected. The loop moves 4 times Thus the ‘RLC’ is called 4 times Thus C- 10111000 ————— Prob.4 Find content of register ‘C’ after execution of the following assembly language program. MVIA, 67H MVIB, 24H ADDB DAA MOVCA HLT IR.T.U, 2016), ee Sol. —— 0110¢ Teva ooiebon 24/>B Tooo101 [sp] This instruction is usep to transfer the contro} from the program lexecution to a speci location. Ithas following addressing : [(SP]-1] < [PCH] [(SP}-2] < [Pct] [SP] < [sP}-2 [Pc] 8xn It is also I-byte opeode instruction, Ithas 3 machine eyles as : (a) Opcode fetch-6T states (b) memory read-3T state [PCH] (©) memory read ST state [PCL] RST does not store previous address. 1. [This instruction is used to Return from subroutine to the main program lunconditionally. thas following addressing [PCL] < [SP] [PCH] < [[SP}+1] [SP] — [sP}+2 itis I-byte only opcode instruction. . [Ithas 3 machine eyeles as : (a) Opcode fetch-AT states (b) memory read-3T sates (©) memory read-3T states - [RET saves the address back from the stack pointers to program counter used where subpart oF Progtam is used. It is the type of interrupts. It is used where softwar is required. Prob.6 Compare the function of the JMP and CALL jews Scanned with CamScannericrpronessor and Interfaces SMP and CALL instructions STAX and LDAX IMP CALL S.] ~~ STAX LDAX ris used to Jump the execution of program at any specified address Itis used to execute the | broutine programs truction ‘unconditionally. 7 fits 16-bit address. Tisalso it address, oy 5, |Ithas 3 machine cycles It has 5 machine cycles SS |_ land 10-T states and 18-T states, ay) [a thas Hex code C3 It has Hex Code CDH ee 2 Prob.7 Compare the function of the XTHL and XCHG IRTU.2013] hig | Sol. Comparison of XTHL and XCHG instructions . XTHL XCHG |. | This instruction is used to | This instruction is used lexchange the contents of _|to exchange the contents HL pair to stack pointer’s_ [of HL pair with DE pair. top. | Syntex ¢ Syntex: ic (sP} [HL] © [DE] [H]<[sP+1) Itis -byte instruction. It is also I-byte instruction, Ithas I machine eyeles | land 4-T states as follows. Opcode fetch- AT states. thas 5 tmachine eyles and 16-T states as follows : (a) opcode fetch-4T states (b) memory read-3T states \). memory read-3T states \(d) memory read-3T states memory read-3T states Hex code for XTHL instruction is E3H. | jo zl Hex code for XCHG instruction is EBH. / IRILU.2013) T. | Store the content oF ‘accumulator in memory location whose address is specified in the register pair. Loac the contents of ‘memory location whose address is specified in the register pair to accumulator. 2. | Teuses BA and DE pair. | Its also uses BC and DE pairs. Syntex 3. | Symtex. a 4. | Tthas 2 machine eyele and 7-T state Tthas 2 machine eycle and 7T state. Prob9 Write a program to store hexadecimal data AB in memory locition 2300, split the data in the from of OA and OB, and store them in memory location 2501 and 2502. IR-T.U. 2013] Sol. LXI H, 2300 Load HL with 2300 H MVI M, AB H_ Store AB H in memory location pointed by HL register pair (2300H) MOV BLM Get the data in B-eg MOV A,B Copy the data to A-reg ANI OF H Mask the upper nibble MOV MA STA 2501 Store the lower nibble in memory MOV A,B Get the data in A-reg ANI FOH Bring the upper nibble to lower nibble position RRC RRC RRC RRC MOV M,A STA 2502 _Storethe uppernibblein memory HLT ‘Terminate the program Prob.10 Write contents of all registers after every instruction given program segment. MVIC, 10H LXI H, 2370 H LXI D, 7870 H MOVA,M STAX D MOV M,C LDAX D HLT [RTU.2009] es A 5 DAX. UL | POE Compare the function of the STAX and LDAX, 3 Scanned with CamScannerSol. MVIC, 10H | [EReg] « [Eo] > c=10 2 LNIH, 2370 H — [2370] => HL=2370 HL Reg] = H=23L=70 LXID, 7870 DE = 7870 D=78E=70 MOV AM A © (2370)-load 2370 duta into accumulator TiTech (iV Semi) 65. Solved Papem % Explain the function of following program MVE A, Byte 1 ORA A JM OUT PRT OUT 01H n HLT OQUTPRT : CMA ADI 01H OUT 01H HLT IRT.U, 2004, ee, Prob STAXD A-» (7870) store accumulator data into | Sol. 7 sory bat si Move an immediate data of 7870 memory location MVIA, BYTE. Se tet byt OR (2370) —> (7870) MOV M,C M=(2370)=C=10 ona A 7 eitcitr ir sccumulsor LDax [peed A (7870) load 7870 memory location data into A. HLT i | Stop progam edn ye} if rT eae Ths contens of accomaior ot [Link] For the figure below, specify the entite memory JM, OUT PRT remain same, but the flags will be map and explain the significance of the don't care address hanged, Tine on memory addresses. grow | Tinas to te wedi . cd Our PRT GWA ie OUTFIT bate 83 fan ‘DLOU reel vl come out be poste ‘a Ouran ae mr [Fite vate oFA Ze coy te _— prosenton port Ol fet i postive, Ten conan ova] became Aw Aor aa then complement of data in > fHicx Add [Por accumulator. 00 {PA ots. <4 ‘or por el te ” set ame ‘Add. 01 to the value i.¢.2's Forpon Aad 19 Ire , Complement the umber u1_ Ice] f ter. 2008) | - 04h isthe adress of port B.S | Grote posmme the vale of das pee on pot SL May mapa Be LED wil be dbplyes an lis, bind of he programme To F000 The A,, is not used in the NAND gate logic and not in the add range. .. A,, can be used as (X) don't care, because it is not aking part in the add generator. Therefore, the (X) is used for address variable, ee Prob.13 If the clock frequency is SMHz, how much time is required to execute an instruction of 18 T-States. [RT 2008] Sol. Frequeney = SMHz Time = [05 _| Memory Address => [3000 | Where 05 p> 0000 0304 output Data o> Memory Address => purpose. 1. MVE is used to lond an 8-bit given register immediately (2 Byte instruction) 2, LDA is used to load accumulator direct using 16- bit address (3 Byte instruction) 3, MOVis used to transfer the data from accumulator toregister(any) orregiste{any)to accumulator (1 Byte) 4, RAR is used to shift ‘A’ right with carry (1 Byte instruction) 5, STA‘is used to store data from accumulator into memory direct using 16-bit address (3 Byte instruction) 6... INRis used to increase given register by | (1 Byte instruction) Scanned with CamScannerINC is used to jump to the given step if their is no carry (3 Byte instruction) 8. INZis used to jump to the given step if their is not zero (3 Byte instruction) 9. DCR isused to decrease given register by I (I Byte instruction) 10. HLT is used to halt the program Prob.16 Define direct and indirect addressing modes with ‘appropriate examples, IR-T.U.2016] OR Describe various addressing modes available in 8085 microprocessor with two example of each. S IR-TU.2013} OR ; Explain various addressing modes with example in 8085 assembly language programming. © [RXLU.2013, 10, Raj, Univ, 2001, 2000) OR Explain direct and indirect addressing with suitable examples. IRTU.2014), Sol. Addressing Modes : Each instruction requires certain FE PT Tope Contain 1 TE PLe oy D; B,D, B,D, B, BD. Accumulator after applying RLC Instruction. Accumulator] GD Tet qoy To With CY D,D.D, DD, D, DD, T TEEPE YY 00.0.0, DD, Accumulator and carry bit after RAL execution. RRC (Rotate Accumulator Right shift the contents of accumulator right by one carry, Zero bit of accumulator shift to seventh bit and carry bit Syntex : ]<[B} (a)_Itis 1 byte opcode instruction. (b) Only carry flag is affected. (c) Implicit address mode. (@) thas 1 machine cycle and 4-T state Example : Accumulator contain A7H and carry flag. is reset to 0 pete Loe Tofifolopi tft Execution eit, Ot TYfopfopopiyy t cy ics After execution accumulator contain DEH value. Scanned with CamScannerUse . (1) To divide the numbers by two. 2) To check whether the bit has carry orno carry. (iv) RAR (Rotate Accumulator Right Through Carry) : Rotae of shift the contents of accumulator right by ‘one bit with carry. Zero bit of Accumulator is shift to carry bit and carry bit is shift to seventh bit, Syntex : D.J<—P.u} [EY]-[D,}, - [D,] [ev Ithas same features like RRC instructions. Example : If accumulator contain A7H and carry flag contain 0 bit. ‘[Link]. (IV Sem.) igh order address {10H} bus wear address {00H} on the bus, a0 © AD, and ALE = 1. In Tz state, the RD line goes low, the data 06 H from memory location om Are paceg the data bus. The fetch cycle becomes complete in T, x4. The instruction is decoded in the Ty-state, During Ty the contents of the bus are unknown. With the change ini, status signal, IO/M = 0, S, = 1 and Sp= 0, the 2nd maching cycle is identified as the memory read. The address is 1, andthe data byte [05H] is fetched via the data bus, Bothy, and My perform memory read operation, but the Micali opcode fetch ice, the I machine cycle of each instruction , In Ty-state, Before | 0 tfofifofofafiyt identified asthe opcode fetch eycle. Execution time for qyy Execution “Cy Fi ‘A, 05H ie,, memory read machine eyele and instruction eye is ‘i Mnemonic] Instruction Machine | T-statgy pe t}efoFTopipopolays Byte Cycle Exec cre _ MVIA, — [Opeode lOpeode Fetch 4 ——————— | fost Prob.18 Explain instruction eycle of an instruction MVTA, 05 amelie [Read Immediate” 3H H using timing diagram. - IRT.2016) a Re Sol. Let the actual physical memory location of register Abe 1000H and the machine code for tz same be OGH. The data * isgiven tobe in OSH. Let the actual physical memory location of this data be 1001 H. Clock frequency of 8085 = 3.125 MHz Time (T) for one clock = 1/3,125 MHz = 0. Time for Memory Rea Total Execution time for Instruction = 77 = 790320 8 Mnemonics | Machine Code | Memory Locations 24 WS MVIA, 05H 06H 1000H imple, Write no. of T OSH Tair states and machine cycles involved in it. {R-T.U.2014 Sol. LDAX : Load Accumulator Indirect. This instruction is used to load the contents of a memory location (location wae) nr) indicated by either register pair BC or DE) into the accumulator. : Example: Assume B = 20H, C = SOH and the memory location 2050H = 71H, The instruction "LDAX B' transfers the contents of 2050 H (i.e., 71H) to the accumulator. The complete description of LDAX is: ram for MVIA, OSH The MVIA, 05H instruction requires 2-machine eycles (M, and M,). M, requires 4-states and M, requires 3-states, total of 7-states as shown in figure, Status signals IO/M, S, and Sp specifies the 1* machine cycle as the opcode fetch. |Opcode/Operand] Bytes] NE Hex . cycles, code max[ Bc [a 2 0A DE ar No flags are affected by this instruction. The timing grain for LDAX is shown in Fig, (assume that this opcode ‘LDAX B° is stored in the memory location 1031 EH) Scanned with CamScannerCLK Ay Ae ALE OM ox Oe DQOSERSSLS/-T teenie OR eT PME] RD | /| HM —— eM Opcode Fetch Memory Read Fig, ing diagram of LDAX B es Prob.20 Write an assembly language delay subroutine to provide a time delay of 0.5ms for an 8085 microprocessor operating at 2 MHz frequency, IR, 2012] ee Sol. The delay required is 0.5 millisecond hence an 8-bit register of an 8085 can be used to store a count value. The count is decremented by one and the zero flag is verified, If zero flag is set, then the decrement operation is terminated. The delay routine is written as.a subroutine, as shown below. Delay routine MVID, N ; Load the count value, N in D-register. Loop : DCR D ; Decrement to count. INZ Loop ; If count is not zero go to Loop. RET ; If count is zero return to main program, The following table shows the T-state required for execution ofthe instructions in the subroutine. ‘Table [trasion | Totaterequred or [Name oftines | Taal Paes | ‘execution ofan | thesinstruction is: | Instuction execu CALL ae16 17 T 1 MMI DN 7 1 | Der D 4 Nines ANZ Loop 0 (s-tytimes | 10 + ae1)= 1ON-IO ot 1 T=7 RET 10. wee real equal To aiuine TNT Calculation to find the count value, N External clock frequency = 2 MHz . :xtemal clock _ 2 _ Internal clock frequency = IMHz followii 1 Internal clock frequency 1 1x10" Time period of one T state 8 Required time delay Numberof Tstates required for0.5 ms = = oot ctate 05x10? 10% 00,5 [Link] the total T states required for subroutine and number of T states forthe required time delay the count value, N can be calculated. +. MIN +32= 50046 500-32 =33.42B9 = 34,9 = 22, Count value, N =22,, Ifthe above delay routitie is called by a program and executed with the count value of 22,, then the delay produced will be 0.5 millisecond, ———— — Prob.21 (a) Write a progrant to transfer sixteen bytes of data stored in memory location at C250H to C25FH to new memory locating starting at C270 H. , (b) Specify the register contents and the flag status as the instructions are executed. A B Ss Zz XX SUBA MOV B,A DCR B INR B SUI 01H HLT cy XX X xX Xx [R-T.U, 2008] Sol: (a) Gs) Memory ae ‘New memory locaton oT] (C2srHt Scanned with CamScannerLXTH, C2501 LXTD, €270(H) MVIC. OF (H) Loop: MOV A, M. XCHG OF MOV BM. A MOV M.A. Xx XCHG ox MOV MB. ow DE INXH. a a INXD. XXD aL DE C250. C270 A 8 Go Ga A, 8 ex) A. 8 A 8 sove eye G [ek oy 8 A 8 pen | Gt) Go Gi B A 8B mas |G) Go G4 Al A op SULO1GH} “> Gx] Ga A we |e ca Prob.22 Write the assembly Language program for the following problems : (a) Addition of the two Hexadecimal numbers 3A968A67 and 9B476C8B (Raj. Univ. 2004] (8) Exchange of the 10 data contained from the memory location 2450 opwards (Ist Block) with memory location 2480 onwards (2nd Block). Raj. Univ. 2007, 2001 ————————————— Sol. (a) Addition of two 32- 3A968A67 and 9B476C8B Mnemonics Comments MV] A,67H_ Move 67 H ie. SLSB of first number in the accumulator, MVI -L,8BH_— Move 8B i.e, LSB of second number in the L register, ADD LL | LregisterACA+L MOV CA CeA it hexadecimal numbers MVI 8A H Mv -1L6CH ADDL MOV BA MVI = -A96H MVI—L,47H ADC OL MOV EA MVI—A,3AH MVI L,9 BH ADC OL Mov DA ACI 00H HLT Sol. (b) Mnemonics MVI CAH LXI ‘H, 2450H LXI 'D,2480H Label MOV MOV BA LDA X,D Move MA Move A,B STAX. D “INX H INXX D pc RC JNZ Label Move next 8 LSB of ‘number in the accumu Move next 8 LSB of secong number in the acciimulatge ACALL (catty frog previous sum) BeA Move 96 H to acc, Move 47 H to reg. ACATL + carry of previous sum ECA Move 3A to accumulator Move 9 B to reg L. AcA+L+ cary DHA Ae 00H +cany+A Stop Comments Move counter to reg C. Starting address of the Ist block is stored in the HL pair. Starting address of the second block is stored inthe DE pair A,M Move the data stored in the address, stored in HL pair to accumulator BeA Load the accumulator with the data that is stored in the address, stored in DE pair. Move the data stored in accumulator and the address stored in HL pait: AcB Stored the data in the accumulator in the address that is stored in the DE pait Increment HL Pair Increment DE pair Decrement counter Check if the counters equal to zero if not, then jump label, Stop. Scanned with CamScanner—————————— Prob.23 Explain the instruction format of 8085. Draw the timing diagram of instruction MOV A, M and explain it IRTU.2017) —— Sol. Instruction Format of 8085 : Refer 10 Prob. . Instruction word size : The 8085 instruction set is classified jnto the following three groups according to word « One-word or I-byte instructions + Two-word or 2-byte instructions « Three-word or 3-byte instructions In the 8085, “byte” and “word” are synonymous because itis an 8-bit microprocessor. However, instructions ~ gre commonly referred to in terms of bytes rather than words. 1. One-Byte Instructions : A 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are intemal register and are coded into the instruction Table 1: Example for 1 Byte instruction iz Task Op |Operand] Binary | Hex code Code | Code (Copy the contents of [MOV] C,A | 0100 | 4FH ithe accumulator in the IL register C. [Addthe contents of [ADD] B 1000 | 80H register B to the 000 contents of the accumulator. Invert (compliment) [CMA 0010 | 2FH ach bit in the mu accumulator. These instructions are I-byte instructions performing, three different tasks. In the first instruction, both operand registers are specified. In the second instruction, the operand Bis specified and the accumulator is assumed. Similarly, in the third instruction, the accumulator is assumed to be the implicit operand, These instructions are stored in 8- bit binary format in memory; each requires one memory location. MOV rd, rs rd B rs copies contents of rs into rd. Coded as 01 dddsss __ Where ddd isa code for one of the 7 general registers Which is the destination of the data, sss is the code of the Source register: Example : MOV A,B 11000 = 781 70 octal (octal was ADD r ABA+r 2. Two-Byte Instructions : In a two-byte instruction, the first byte specifies the operation code and the second byte specifies the operand. Source operand is a data byte immediately following the opcode. For examp! Table 2: Example for 2 Byte Instruction Task Op [Operand|Binary| Hex code Code | Code Load an 8-bit |MVI| A, Data | 0011 | 3E | First data byte in the 1110 | Data | Byte accumulator. DATA Second Byte The instruction would require two memory locations to store inmemory. MVI ndata FB data Example: MVIA,30H coded as 3EH 30H as two contiguous bytes. This is an example of immediate addressing. ADI data ABA + data OUT port oot 1110 DATA Where port is an 8-bit device address.(Port) B A. Since the byte is not the data but points where itis located this is called direct addressing. 3. Three-Byte Instructions : In a three-byte i the first byte specifies the opcode, and the following two bytes specify the 16-bit address. Note that the second byte is the low-order address and the third byte is the high-order address. opcode + data byte + data byte Table 3 : Example for 3 Byte Instruction Task | Op [Operand| Binary | Hex code Code _| Code ‘Transfer the [IMP | 2085H |[1100]| C3 | First program ool Byte sequence to 1000|| 85 | Second’ the memory 101 Byte location 0010} | 20 | Third 208SH. 0000 Byte This instruction would require three memory locations tostore Scanned with CamScannerXI rp, datal6 . mp is one of the pairs of registers BC, DE, HI. used as 16-bit registers, The two data bytes are 16-bit data in LH ‘order of significance. rp B datal6 LXIH,0520H coded as 21H 20H SOH in three bytes. This isalso immediate addressing. LDA addr AB (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as 3AH 34H 21H. This is also an example of direct addressing. ‘Timing Diagrain for MOV A,B : The instruction MOV A,B is a I-byte instruction, “Microprocessor takes only one machine cycle (op-code fetch) to complete instruction. Hence, hex code for MOV A,B is passed to the microprocessor. soa] cox = [oe 1 fk Te wae | a Bical sore Fig, Prob.24 Classify the instructions set of 8085 and explain them. {R-1.U.2017] ——— Sol. Instruction Set of 8085 : 8085 Instructions can be classified based on the size they occupy in memory or by the functions they perform, LT F1,DLNOP, RD, stu. Fig. Classification of Instruction Set ‘of 8085 Instructions Based on Size : Based on the size, y instructions can be classified are as follows: _ 1. One byte Instructions: These instructions are of, byte in size and hence occupy one memory locatign RAM. Examples are CMA, RLC, RRC, RAL, Rag STC, CMC ete. These instructions do not require operand to be specified with the instructions, inj the operand is implied in the instructions. ‘Two Byte Instruc These instructions of ty byte(6-bits) in size and hence will occupy two, locations in RAM. Examples of such instructions MVIC0A; ‘Three Byte Instructions: These are of thtee in size and hence occupy three locations jy memory(RAM). Examples of such instructions ay CALL, JMP etc. Instruction Set Based on Function ‘An instruction is a binary pattern designed inside, microprocessor to perform a specific function. The entre group of instructions, called the instruction set, determing what functions the microprocessor can perform. These instructions can be classified into the following five functions categories: data transfer (copy) operations, arithmet ‘operations, logical operations, branching operations, anj machine-control operations. 1, Data Transfer Group : The data transfer instruction move data between registers or between memory ani registers. MOV Move MVI— Move Immediate LDA Load Accumulator Directly from Memory STA Store Accumulator Directly in Memory LHLD Load H & L Registers Directly from Memory SHLD Store H & L Registers Directly in Memoy An‘X’ in thename of a data transfer instruction implis that it deals with a register pair (16-bits); LXI_— Load Register Pair with Imm LDAX Load Accumulator from Address in Regist Pair STAX Store Accumulator in Address in Regist Pair XCHG Exchange H & L with D & E XTHL Exchange Top of Stack with H & L 2. Arithmetic'Group : The arithmetic instructions subtract, increment, or decrement data in registers or memo |, ADD — Add to Accumulator ADI Add Immediate Data to Accumulator ADC Add to Accumulator Using Carry Flag ACI Add immediate data to Accumulator Usift Carry + SUB Subtract from Accumulator SUI Subtract Immediate Data from Accumula®™ Scanned with CamScanner