Introduction to Digital System Design

Z. Navabi

Topic 4

RTL Combinational Components

Zain Navabi

Slides prepared by Katayoon Basharkhah 1

RTL View

5-1 RTL view

5-1-1 Why RTL?
5-1-2 What is RTL?
5-2 Packages
5-3 Combinational Verilog Constructs, a review

Introduction to Digital System Design - Copyright Zainalabedin Navabi 2

 Why RTL?
• Consider you are going to design a circuit for calculating absolute value

Absolute value circuit

8 8
A ABS w
10110010 01001110

• What do you need?

• A big truth table for 8 inputs and 8 outputs

• 8-variable K-Maps for each outputs, w0 to w7

3
Introduction to Digital System Design - Copyright Zainalabedin Navabi
Why RTL?
• Register Transfer Level is a solution
a0 s
a1
a2
a3 w0
a4 w1
0 w2
a5 w3
a6 w4
8 8 a7
A ABS w w5
w6
w7

+1 1

4
Introduction to Digital System Design - Copyright Zainalabedin Navabi
RTL View

5-1 RTL view

5-1-1 Why RTL?
5-1-1 What is RTL?
5-2 RTL combinational components
5-3 Combinational Verilog Constructs, a review

Introduction to Digital System Design - Copyright Zainalabedin Navabi 5

What is RTL?
What is RTL? Register Transfer Level
• One level upper than gate level

• A functional level
Accelerator

2010+
CPU

ES Level
data_bus
dbus_on_data
dbus data_on_dbus
alu_on_dbus 8
8

Register ld_ac AC ld_ir IR

2000
6
6 PC

comparator RT Level

ld_pc
inc_pc
clr_pc
ALU pass
add
6 6

ir_on_adr pc_on_adr
addr_bus 6

1980

Gate Level
1970

Transistor Level

6
Introduction to Digital System Design - Copyright Zainalabedin Navabi
What is RTL?
data_bus
dbus_on_data
dbus data_on_dbus
opcode
alu_on_dbus 8 2

8 ir on adr
Reset clr pc rd mem

wr mem
pc on adr
dbus on data pc on adr
ld_ac AC ld_ir IR data on dbus rd mem
ld ir Fetch data on dbus
6 ld ac ld ir
ld pc inc pc
Controller
6 PC
inc pc
clr pc
padd
Decode
alu on dbus
add
ld pc

ld_pc
inc_pc
clr_pc
ir on adr

ALU pass
Execute dbus on data
ld ac
add alu on dbus
6 6 wr mem

clk
reset

ir_on_adr pc_on_adr
addr_bus 6

7
Introduction to Digital System Design - Copyright Zainalabedin Navabi
What is RTL?
data_bus
dbus_on_data
dbus data_on_dbus
alu_on_dbus 8
8

ld_ac AC ld_ir IR
6
6 PC

ld_pc
inc_pc
clr_pc
ALU pass
add
6 6

ir_on_adr pc_on_adr
addr_bus 6
Combinational component

8
Introduction to Digital System Design - Copyright Zainalabedin Navabi
RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review

Introduction to Digital System Design - Copyright Zainalabedin Navabi 9

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components

Introduction to Digital System Design - Copyright Zainalabedin Navabi 10

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review

Introduction to Digital System Design - Copyright Zainalabedin Navabi 11

RTL Combinational components
Decoder (functionality and gate level)
A0 I0
0
I1
A1 Binary 2-to-4
1 Decoder I2
I3

A0 A1 I0 I1 I2 I3 A0 A1 I0 I1 I2 I3

0 0 1 0 0 0 0 0 0 1 1 1
0 1 0 1 0 0 0 1 1 0 1 1
1 0 0 0 1 0 1 0 1 1 0 1
1 1 0 0 0 1 1 1 1 1 1 0

Active high outputs Active low outputs

Introduction to Digital System Design - Copyright Zainalabedin Navabi 12
RTL Combinational components
Decoder (functionality and gate level)
A1 A0 A0 I0
0
I1
A1 Binary 2-to-4
1 Decoder I2
I0
en I3

I1

en A0 A1 I0 I1 I2 I3
I2
1 0 0 0 1 1 1
1 0 1 1 0 1 1
I3
1 1 0 1 1 0 1
1 1 1 1 1 1 0
0 - - 1 1 1 1
en
Introduction to Digital System Design - Copyright Zainalabedin Navabi 13
RTL Combinational components
Decoder (functionality and gate level)
A1 A0 A0 I0
0
I1
A1 Binary 2-to-4
1 Decoder I2
I0
en I3

I1

en A0 A1 I0 I1 I2 I3
I2
0 0 0 0 1 1 1
0 0 1 1 0 1 1
I3 0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 - - 1 1 1 1
en
Introduction to Digital System Design - Copyright Zainalabedin Navabi 14
RTL Combinational components
Build a 4 to 16 binary decoder
A0 I0
0
I1
A1 Binary 2-to-4
1 Decoder I2
en I3

A0 I0
0
I1
A1 Binary 2-to-4
A0 I0
0 1 Decoder I2
I1 en I3
A1 Binary 2-to-4
1 Decoder I2
en I3
A0 I0
0
I1
A1 Binary 2-to-4
1 Decoder I2
en I3

A0 I0
0
I1
A1 Binary 2-to-4
1 Decoder I2
en I3

Introduction to Digital System Design - Copyright Zainalabedin Navabi 15

RTL Combinational components
A3 A2 A1 A0
Decoder (Cascading) I0
0 I1
Binary 2-to-4
I0 1 Decoder
I2
I1 I3

I2
A0 I3 I4
0 I4 0 I5
Binary 2-to-4
I5 1 Decoder
I6
A1 I6 I7
1 I7
0
A2 Binary 4-to-16 I8 Binary 2-to-4 I8
0
2 Decoder I9 Decoder I9
1 Binary 2-to-4
I10 1 Decoder I10
A3 I11 I11
3 I12
I13 I12
en I14 0 I13
Binary 2-to-4
I15 I14
1 Decoder I15

Introduction to Digital System Design - Copyright Zainalabedin Navabi 16

RTL Combinational components
Decoder (Verilog description)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 17

RTL Combinational components
Decoder (Application)

Address decoding for memory

Introduction to Digital System Design - Copyright Zainalabedin Navabi 18

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review
Introduction to Digital System Design - Copyright Zainalabedin Navabi 19
RTL Combinational components
Multiplexer (Functionality and gate level)
s s

a w
a
0
w
b
b 1

w = 𝑠. 𝑎 + 𝑠. 𝑏

w= (~𝑠 & 𝑎) | (𝑠 & 𝑏)

w= ~𝑠 ? 𝑎 ∶ 𝑏

Introduction to Digital System Design - Copyright Zainalabedin Navabi 20

RTL Combinational components
Multiplexer (Cascading)
s0

a
0 s1
a
00 S1 S0 w
b 11 w 0 0 a b 1

c 0 1 b 0
w
22
d 1 0 c
33 1
1 1 d c
0

d 1

Introduction to Digital System Design - Copyright Zainalabedin Navabi 21

RTL Combinational components
Multiplexer (Cascading)
s0
S1 S0

a
0 s1
a

b 1
0 b
w

1 c
c
0

d
d 1

Introduction to Digital System Design - Copyright Zainalabedin Navabi 22

RTL Combinational components S3 S2 S1 S0
Multiplexer (Cascading)
a

16 to 1 multiplexer b
c
d

Iterative
e
Logic f
g
h

I0
0 I1
Decoder i
1 I2
I3 j
k
l

m
0
n
o
p 0
1

Introduction to Digital System Design - Copyright Zainalabedin Navabi 23

RTL Combinational components
Multiplexer (Verilog description)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 24

RTL Combinational components
Multiplexer – Tri-state

1 S

2
3

Introduction to Digital System Design - Copyright Zainalabedin Navabi 25

RTL Combinational components
Multiplexer – Tri-state
s s

a w
a
0
w
b
b 1

w = 𝑜𝑒 ? ~𝑠 ? 𝑎 ∶ 𝑏 ∶ 1′ 𝑏𝑍

Introduction to Digital System Design - Copyright Zainalabedin Navabi 26

RTL Combinational components c a b

Multiplexer – Tri-state 0

2
2
3 w

5
6
7

S1 S0

Introduction to Digital System Design - Copyright Zainalabedin Navabi 27

RTL Combinational components
Multiplexer – Tri-state (Cascading)
S3 S2 S1 S0

a
b
c
d

e
f
g
h

I0
0 I1
Decoder i
1 I2
I3 j
k
l

m
0
n
o
p 1

Introduction to Digital System Design - Copyright Zainalabedin Navabi 28

RTL Combinational components
Multiplexer – Tri-state (Verilog description)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 29

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-6 Adder
5-2-7 ALU
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review

Introduction to Digital System Design - Copyright Zainalabedin Navabi 30

RTL Combinational components
Mux-based design a b

ab
00
0 0
01 11 10
ci
Ci 1 Co
0 0 0 1 0
0 2 6 4 Ci 2
1 0 1 1 1 1 3
1 3 7 5
co

ab
00 01 11 10
ci

0 0 1 0 1 0 0
0 2 6 4
Ci 1 S
1 1 0 1 0
1 3 7 5 Ci 2
s Ci 3

Introduction to Digital System Design - Copyright Zainalabedin Navabi 31

RTL Combinational components
Mux-based design c a b

1 0

ab 𝑑ҧ 1
cd 00 01 11 10

00 1 1 0 1 𝑑ҧ 2
2

1 0 1 0 𝑑 3 w
01
0 0 1 1 0 4
11
𝑑ҧ 5
10 0 1 0 1
1 6
w
𝑑 7

Introduction to Digital System Design - Copyright Zainalabedin Navabi 32

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review
Introduction to Digital System Design - Copyright Zainalabedin Navabi 33
RTL Combinational components
Parity Circuit

• Odd Parity Circuit: The output is one if odd number of inputs are 1

• Even Parity Circuit: The output is one if even number of inputs are 1

I0 I0
I1 EVEN I1
ODD I2 EVEN
I2
I3 I3 ODD

Introduction to Digital System Design - Copyright Zainalabedin Navabi 34

RTL Combinational components
Parity Circuit – SystemVerilog, Generate

• Odd Parity Circuit: The output is one if odd number of inputs are 1
I0 I0
I1 I1

I2 I2 EVEN
EVEN

I3 ODD I3 ODD

Introduction to Digital System Design - Copyright Zainalabedin Navabi 35

 RTL Combinational components
Parity Circuit – SystemVerilog, Parameters

• Odd Parity Circuit: The output is one if odd number of inputs are 1
I0
I1
I2 EVEN

I3 ODD

Introduction to Digital System Design - Copyright Zainalabedin Navabi 36

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review

Introduction to Digital System Design - Copyright Zainalabedin Navabi 37

RTL Combinational components
Comparator (Functionality, gate level and cascading)
One slice for comparing 2 corresponding bits of a and b

Introduction to Digital System Design - Copyright Zainalabedin Navabi 38

RTL Combinational components
Comparator (Functionality, gate level and cascading)
One slice for comparing 2 corresponding bits of a and b
eq gt

5 ns
5 ns

5 ns

EQ GT
5 ns 10 ns

Introduction to Digital System Design - Copyright Zainalabedin Navabi 39

RTL Combinational components
Comparator (Functionality, gate level and cascading)

eq gt eq gt eq gt eq gt

a3 a2 a1 a0

b3 b2 b1 b0

EQ GT EQ GT EQ GT EQ GT

Introduction to Digital System Design - Copyright Zainalabedin Navabi 40

RTL Combinational components
Comparator (Functionality, gate level and cascading)
Comparator package with the following attributes:

a lt

if (A>B) lt=0, eq=0, gt=1 b

eq
if (A<B) lt=1, eq=0, gt=0 Comparator
if (A=B) lt=l, eq=e, gt=g l gt
g
e

4-bit
Cascadable
Comparator

Introduction to Digital System Design - Copyright Zainalabedin Navabi 41

RTL Combinational components
Comparator (Verilog description)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 42

RTL Combinational components
Comparator (Functionality, gate level and cascading)
Least to most

Q3 Q2 Q1 Q0

Introduction to Digital System Design - Copyright Zainalabedin Navabi 43

RTL Combinational components
Comparator (Application)

Maximum finder circuit

4
a A
b 4 B
lt
eq
0 l gt
1 e
0 g

0 4
Max (a,b)
1

Introduction to Digital System Design - Copyright Zainalabedin Navabi 44

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review
Introduction to Digital System Design - Copyright Zainalabedin Navabi 45
RTL Combinational components
Adder (Functionality and gate level)

10110101
+
00101101

1 11100010

Introduction to Digital System Design - Copyright Zainalabedin Navabi 46

RTL Combinational components
Adder (Functionality and gate level)

ab
00 01 11 10
ci

abci cos 0 0 1 0 1
0 2 6 4
8/ 8/ 000 00
1 1 0 1 0
001 01 1 3 7 5
010 01 s
Adder 011 10 ab
00 01 11 10
100 01 ci
8/ 101 10 0 0 1 0
Co Si 0
0 2 6 4
110 10
111 11 1 0 1 1 1
1 3 7 5
co

Introduction to Digital System Design - Copyright Zainalabedin Navabi 47

RTL Combinational components
Adder (Functionality and gate level)

ab
00 01 11 10
ci
a 0 1 0 1
b Si 0
0 2 6 4
Ci 1 1 0 1 0
1 3 7 5
a s

b ab
00 01 11 10
ci
Co 0 0 1 0
Ci 0
0 2 6 4

1 0 1 1 1
1 3 7 5
co

Introduction to Digital System Design - Copyright Zainalabedin Navabi 48

 RTL Combinational components
Adder (Functionality and gate level)

a Full Adder
b Si Ci bi ai Half Adder
Ci

a Co
b
Co
Ci
Si

Introduction to Digital System Design - Copyright Zainalabedin Navabi 49

RTL Combinational components
Ripple Carry Adder
b3 a3 b2 a2 b1 a1 b0 a0

C3 C2 C1 C0=0
Cout FA FA FA FA

S3 S2 S1 S0

Incrementer
b3 b2 b1 b0 1

Cout HA HA HA HA

S3 S2 S1 S0

Introduction to Digital System Design - Copyright Zainalabedin Navabi 50

RTL Combinational components
Full adder (Verilog description)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 51

RTL Combinational components
8bit adder (Verilog description)

Incrementer (Verilog description)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 52

RTL Combinational components
Adder / Subtractor
We can perform subtraction by simply inverting the bits of one
operand and setting the carry in bit of the operation to 1.
b3 b2 b1 b0
b3 b2 b1 b0

a3 a2 a1 a0 a3 a2 a1 a0

Cin 1
Adder Adder Cin

𝑎 − 𝑏 = 𝑎 + (−𝑏) = 𝑎 + (𝑏 + 1)

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 53

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review
Introduction to Digital System Design - Copyright Zainalabedin Navabi 54
RTL Combinational components
ALU
• An ALU is a component that can do both arithmetic and logic operations
on its inputs.
• It can also have a comparator inside that gives outputs such as overflow
flag, zero flag, etc as well as its operation results.
f2 f1 f0 w

0 0 0 A+B
0 0 1 A*2
0 1 0 Max(A,B)
0 1 1 A&B
1 0 0 A|B
1 0 1 2’s complement
of input A
1 1 0 A
1 1 1 ~A

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 55

RTL Combinational components
MUX (Verilog description); Using an always statement)

a
00
b 11 w
c
First, let’s talk about a
22 new construct in
d
33 Verilog:
The always statement

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 56

RTL Combinational components
ALU (Verilog description); Using an always statement)

f2 f1 f0 w

0 0 0 A+B
0 0 1 A*2
0 1 0 Max(A,B)
0 1 1 A&B
1 0 0 A|B
1 0 1 A 2’s cmp
1 1 0 A
1 1 1 ~A

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 57

RTL Combinational components
ALU (Verilog description)

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 58

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU – A case study
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review
Introduction to Digital System Design - Copyright Zainalabedin Navabi 59
RTL Combinational components
Case Study (Maximum Finder)

Maximum finder circuit

4
a A
b 4 B
lt
eq
0 l gt
1 e
0 g

0 4
Max (a,b)
1

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 60

RTL Combinational components
Case Study (Maximum Finder)
Verilog description

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 61

RTL Combinational components
Case Study (Maximum Finder)
Testbench

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 62

RTL Combinational components
Case Study (Maximum Finder)
Testbench

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 63

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU – A case study
5-2-8 Fast adders
5-3 Combinational Verilog Constructs, a review
Introduction to Digital System Design - Copyright Zainalabedin Navabi 64
RTL Combinational components
Ripple Carry Adder

• nth full adder must wait until all (n-1) full adders have completed their
operations.

• This causes a delay and makes ripple carry adder extremely slow.

• The situation becomes worst when the value of n becomes very large.

• Carry look ahead can be a solution

• We need a design where each cell can predict its own carry instead of
waiting for carry.

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 65

Combinational components
Carry lookahead adder

p0

g0

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 66

Combinational components
Carry lookahead adder

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 67

RTL Combinational components
Carry lookahead adder

• Carry look ahead logic uses the concepts of generating and propagating
carries.
ci+1 = ai  bi + ai  ci + bi  ci
si = ai  bi  ci
ci+1 = (ai + bi)  ci + ai  bi= pi  ci + gi

pi = ai + bi
gi = ai  bi

c1 = p0  c0 + g0
c2 = p1  c1 + g1 = p1  p0  c0 + p1  g0 + g1
c3 = p2  c2 + g2 = p2  p1  p0  c0 + p2  p1  g0 + p2  g1 + g2
c4 = p3  c3 + g3
= p3  p2  p1  p0  c0 + p3  p2  p1  g0 + p3  p2  g1 + p3  g2 + g3

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 68

Combinational components
Group Propagate (PG) and Group Generate (GG) for
an 8-bit CLA

8 8 8 8 8 8 8 8

C32 C24 C16 C8 C0

8 8 8 8

• Ripple carry between blocks

• Carry look ahead inside blocks

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 69

Combinational components
Group Propagate (PG) and Group Generate (GG) for
an 8-bit CLA

8 8 8 8 8 8 8 8

C32 C24 C16 C8 C0

8 8 8 8

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 70

Combinational components
Group Propagate (PG) and Group Generate (GG) for
an 8-bit CLA

C8 = g7 + p7g6 + p7p6g5 + p7p6p5g4 + p7p6p5p4g3 + p7p6p5p4p3g2 + p7p6p5p4p3p2g1 +

p7p6p5p4p3p2p1g0 + p7p6p5p4p3p2p1p0C0

P0 = p7p6p5p4p3p2p1p0
G0 = g7 + p7g6 + p7p6g5 + p7p6p5g4 + p7p6p5p4g3 + p7p6p5p4p3g2 + p7p6p5p4p3p2g1 +
p7p6p5p4p3p2p1g0

C8 = G0 + P0C0
C16 = G1 + P1C8 = G1 + P1G0 + P1P0C0
C24 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C32 = G3 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

Advanced Digital System Design with FPGAs- Copyright Zainalabedin Navabi 71

RTL Combinational components
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU (Verilog always statement)
5-2-8 Fast adders
5-3 Combinational Verilog constructs
Introduction to Digital System Design - Copyright Zainalabedin Navabi 72
RTL Combinational components
5-3 Combinational Verilog constructs
Numbers

Introduction to Digital System Design - Copyright Zainalabedin Navabi 73

RTL Combinational components
5-3 Combinational Verilog constructs
Transistors, primitive instances

Introduction to Digital System Design - Copyright Zainalabedin Navabi 74

RTL Combinational components
5-3 Combinational Verilog constructs
Gates, gate primitive instances

Introduction to Digital System Design - Copyright Zainalabedin Navabi 75

RTL Combinational components
5-3 Combinational Verilog constructs
assign, Boolean, ?:

Introduction to Digital System Design - Copyright Zainalabedin Navabi 76

RTL Combinational components
5-3 Combinational Verilog constructs
assign, Boolean, ?:, vectors, module instances

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RTL Combinational components
5-3 Combinational Verilog constructs
assign, Boolean, ?:, vectors, module instances

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RTL Combinational components
5-3 Combinational Verilog constructs
always

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RTL Combinational components
5-3 Combinational Verilog constructs
Testbenches

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Conclusion
We have covered these topics:
5-1 RTL view
5-2 RTL combinational components
5-2-1 Decoder
5-2-2 Multiplexer
5-2-3 Mux-based design
5-2-4 Parity circuit
5-2-5 Comparator
5-2-6 Adder
5-2-7 ALU (Verilog always statement)
5-2-8 A case study
5-3 Combinational Verilog constructs
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Conclusion
We have covered these topics:

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