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Low Order Memory Interleaving Example

The document describes a memory system with a 256 byte main memory divided into 4 byte blocks and cached in 4-way set associative cache. It asks to: 1) Draw a low order memory interleaving diagram assigning addresses to each bank. 2) Draw the timing diagram showing address and data cycles. 3) Calculate the time to retrieve 4 consecutive bytes given the processor cycle time is 10ns.

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Osama Tahan
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217 views2 pages

Low Order Memory Interleaving Example

The document describes a memory system with a 256 byte main memory divided into 4 byte blocks and cached in 4-way set associative cache. It asks to: 1) Draw a low order memory interleaving diagram assigning addresses to each bank. 2) Draw the timing diagram showing address and data cycles. 3) Calculate the time to retrieve 4 consecutive bytes given the processor cycle time is 10ns.

Uploaded by

Osama Tahan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

A memory of 256 byte is used with a cache of 4 byte block.

Assume the following steps are


required to load data from the main memory to the cache memory:
one cycle to send the address to the RAM,3 cycles to access RAM, one cycle to return the data
from the RAM.
1. Draw a low order memory interleaving and assign addresses to each bank.
2. Draw the timing diagram.
3. If the processor cycle time equals to 10ns. What time is required to retrieve 4 consecutive
bytes?

Solution
1. Designing a low order memory interleaving
a) 256 byte can be addressed by using 8-bits or n=8
b) 4 cache block means that the four way interleaving or m=2
c) Then 𝑀 = 2𝑚 = 22 = 4
d) n-m=8-2=6,then M memory address registers(MAR) of 6-bits are required
e) also M data address registers(DAR) of one byte wide are required
f) the indices of banks are 0,1,2,2𝑚 − 1 = 0,1,2,22 − 1 = 0,1,2,3
2. Timing diagram
1ns 3ns 1ns
A0 D0
A1 D1
A2 D2
A3 D3
A0

A0 can be used again

Then four banks are required

3. To retrieve 4 consecutive bytes


1+3+(4*1)=8cycles
Miss penalty time=8*10ns=80ns

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