MCP19110/11

MCP19110/11 Flash Memory Programming Specification

This document includes the 1.1 Hardware Requirements
programming specification for the This family of devices requires one power supply for
following devices: VIN, see Table 6-1. The VDD that is used to bias all
• MCP19110 internal circuitry is internally generated and regulated
• MCP19111 to 5V. A 1 µF ceramic capacitor must be placed
between the VDD and PGND pins.
1.0 PROGRAMMING THE 1.2 Program/Verify Mode
MCP19110/11 DEVICES
The Program/Verify mode for this family of devices
The MCP19110/11 devices are programmed using a allows programming of user program memory, user ID
serial method. The Serial mode will allow these devices to locations, the Calibration Word and the Configuration
be programmed while in the user’s system. These Word.
programming specifications apply to all of the above
devices in all packages.

FIGURE 1-1: PIN DIAGRAM – 24-PIN QFN (MCP19110)

+VSEN
-VSEN
GPB1
GPB2

+ISEN

-ISEN
24

23

22

21

20

19

GPA0 1 18 VDD

GPA1 2 17 BOOT

GPA2 3 16 HDRV
MCP19110
GPA3 4 15 PHASE

GPA7/ICSPCLK 5 14 VDR
EXP-25
GPA6/ICSPDAT 6 13 LDRV
10

12
11
9
7

8
GPA5/MCLR

GPA4

GPB0

VIN

PGND
GND

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MCP19110/11
TABLE 1-1: PIN DESCRIPTIONS IN PROGRAM/VERIFY MODE: MCP19110
During Programming
Pin Name
Function Pin Type Pin Description

GPA7 ICSPCLK I Clock Input – Schmitt Trigger Input

GPA6 ICSPDAT I/O Data Input/Output – Schmitt Trigger Input

MCLR (1)
Program/Verify mode P Program Mode Select
VIN VIN P Device Power Supply Input
VDD VDD P Power Supply Output
GND VSS P Ground
Legend: I = Input, O = Output, P = Power
Note 1: In the MCP19110, the programming high voltage is internally generated. To activate the Program/Verify
mode, voltage of VIHH and a current of IIHH (see Table 6-1) need to be applied to the MCLR input.

FIGURE 1-2: 28-PIN DIAGRAM FOR MCP19111

GPB5/ICSPCLK/ICDCLK

QFN
GPB2

GPB1

24 +VSEN
25 -VSEN

23 +ISEN

22 -ISEN
28

27

26

GPA0 1 21 GPB6

GPA1 2 20 VDD

GPA2 3 19 BOOT

GPB4/ICSPDAT/ICDDAT 4 MCP19111 18 HDRV

GPA3 5 17 PHASE

GPA7 6 16 VDR
EXP-29
GPA6 7 15 LDRV
10

12

13

14
11
8

9
GPA4

GPB0
GPA5/MCLR

GPB7

VIN

PGND
GND

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 MCP19110/11
TABLE 1-2: PIN DESCRIPTIONS IN PROGRAM/VERIFY MODE: MCP19111
During Programming
Pin Name
Function Pin Type Pin Description

GPB5 ICSPCLK I Clock Input – Schmitt Trigger Input

GPB4 ICSPDAT I/O Data Input/Output – Schmitt Trigger Input

MCLR (1)
Program/Verify mode P Program Mode Select
VIN VIN P Device Power Supply Input
VDD VDD P Power Supply Output
GND VSS P Ground
Legend: I = Input, O = Output, P = Power
Note 1: In the MCP19111, the programming high voltage is internally generated. To activate the Program/Verify
mode, voltage of VIHH and a current of IIHH (see Table 6-1) need to be applied to the MCLR input.

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MCP19110/11
NOTES:

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 MCP19110/11
2.0 MEMORY DESCRIPTION 2.3 Calibration Word
For all of the devices covered in this document,
2.1 Program Memory Map Calibration Words are included to allow for storing
The user memory space extends from 0x0000 to the trim values for various analog peripherals (i.e.,
0x1FFF. In Program/Verify mode, the program memory INTOSC module) at final test. These values are
space extends from 0x0000 to 0x3FFF, with the first stored in the Calibration Words 0x2080, 0x2081,
half (0x0000-0x1FFF) being user program memory and 0x2082 and 0x2083. See the applicable device data
the second half (0x2000-0x3FFF) being configuration sheet for more information.
memory. The Program Counter (PC) will increment The Calibration Words do not necessarily participate in
from 0x0000 to 0x1FFF and wrap to 0x0000. If the PC the erase operation, unless a specific procedure is
is between 0x2000 to 0x3FFF, it will wrap-around to executed. Therefore, the device can be erased without
0x2000 (not to 0x0000). Once in configuration memory, affecting the Calibration Words. This simplifies the
the highest bit of the PC stays a ‘1’, thus always erase procedure, since these values do not need to be
pointing to the configuration memory. The only way to read and restored after the device is erased.
point to user program memory is to reset the part and
re-enter Program/Verify mode as described in
Section 3.0 “Program/Verify Mode”.
For all of the devices covered in this document, the
configuration memory space, 0x2000 to 0x208F, is
physically implemented. However, only locations
0x2000 to 0x2003, 0x2007 and 0x2080 to 0x2083
are available. Other locations are reserved.

2.2 User ID Locations

A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped in 0x2000 to 0x2003. It is recommended that
the user use only the seven Least Significant bits
(LSbs) of each user ID location. The user ID locations
read out normally, even after code protection is
enabled. It is recommended that ID locations are
written as ‘xx xxxx xbbb bbbb’, where ‘bbb bbbb’
is the user ID information.
The 14 bits may be programmed, but only the seven
LSbs are read and displayed by the MPLAB®
Integrated Development Environment (IDE).

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MCP19110/11
FIGURE 2-1: MCP19110/11 PROGRAM MEMORY MAPPING

4 kW

Implemented

0FFF
Program Memory

2000 User ID Location

Maps to
0-FFF
2001 User ID Location

1FFF
2002 User ID Location
2000
Implemented
208F
2003 User ID Location 2090 Unimplemented
2100
2004 ICD Instruction

2005 Manufacturing Codes

Maps to Configuration Memory
2006 Device ID 2000-20FF

2007 Configuration Word

2008-207F Reserved

2080-208F Calibration Words 3FFF

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 MCP19110/11
3.0 PROGRAM/VERIFY MODE FIGURE 3-2: VDD-FIRST PROGRAM/
Two methods are available to enter the Program/Verify VERIFY MODE ENTRY
mode. “VPP-first” is entered by holding ICSPDAT and THLD0 TPPDP
ICSPCLK low while raising the MCLR pin from VIL to
VIHH (high voltage), then applying VDD and data. This
method can be used for any Configuration Word
selection and must be used if the internal MCLR option
VPP
is selected (MCLRE = 0). The VPP-first entry prevents
the device from executing code prior to entering the
Program/Verify mode. See the timing diagram in VDD
Figure 3-1.
ICSPDAT
The second entry method, “VDD-first”, is entered by
applying VDD, holding ICSPDAT and ICSPCLK low, ICSPCLK
then raising the MCLR pin from VIL to VIHH (high volt-
Note: This method of entry is valid if the
age), followed by data. This method can be used for
internal MCLR is not selected.
any Configuration Word selection, except when the
internal MCLR option is selected (MCLRE = 0). This
programming technique is also useful when program- FIGURE 3-3: PROGRAM/VERIFY
ming the device with VDD already applied, for it is not MODE EXIT
necessary to disconnect the VDD to enter the Pro- THLD0
gram/Verify mode. See the timing diagram in
Figure 3-2. VPP

Once in Program/Verify mode, the program memory

and configuration memory can be accessed and
programmed in a serial fashion. ICSPDAT and VDD
ICSPCLK are Schmitt Trigger inputs in this mode.
The sequence that enters the device into the Pro-
ICSPDAT
gram/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at VIL). Therefore, all
ICSPCLK
I/Os are in the Reset state (high-impedance inputs) and
the PC is cleared.
To prevent a device configured with internal MCLR
3.1 Program/Erase Algorithms
from executing after exiting Program/Verify mode, the The MCP19110/11 program memory may be written in
VDD needs to power-down before VPP. See Figure 3-3 two ways. The fastest method writes four words at a
for the timing. time. However, one-word writes are also supported.
The MCP19110/11’s VDD is internally generated by The four-word algorithm is used to program the
applying voltage to the VIN pin. See Table 6-1 for the program memory only. The one-word algorithm can
appropriate range for VIN. To remove VDD, VIN must be write any available memory location (i.e., program
removed. memory, configuration memory and calibration
memory).
FIGURE 3-1: VPP-FIRST PROGRAM/
VERIFY MODE ENTRY After writing the array, the PC may be reset and read
back to verify the write. It is not possible to verify
TPPDP THLD0
immediately following the write because the PC can
only increment, not decrement.
A device Reset will clear the PC and set the address
VPP to ‘0’. The Increment Address command will increment
the PC. The Load Configuration command will set the
PC to 0x2000. The available commands are shown in
VDD
Table 3-1.
ICSPDAT

ICSPCLK
Note: This method of entry is valid,
regardless of Configuration Word
selected.

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MCP19110/11
3.1.1 FOUR-WORD PROGRAMMING 3.1.2 ERASE ALGORITHMS
The MCP19110/11 program memory can be written The MCP19110/11 devices will erase different memory
four words at a time using the four-word algorithm. locations depending on the PC and CP. The following
Configuration memory (addresses >0x2000) and sequences can be used to erase noted memory
non-aligned (addresses modulo 4 not equal to zero) locations. To erase the program memory and
starting addresses must use the one-word Configuration Word (0x2007), the following sequence
programming algorithm. must be performed. Note the Calibration Words
This algorithm writes four sequential addresses in (0x2080 to 0x208F) and user ID (0x2000-0x2003) will
program memory. The four addresses must point to a not be erased.
four-word block which address modulo 4 of 0, 1, 2 and 1. Do a Bulk Erase Program Memory command.
3. For example, programming addresses 4 through 7 2. Wait TERA to complete erase.
can be programmed together. Programming addresses
To erase the user ID (0x2000-0x2003), Configuration
2 through 5 will create an unexpected result.
Word (0x2007) and program memory, use the following
The sequence for programming four words of program sequence. Note that the Calibration Words (0x2080 to
memory at a time is: 0x208F) will not be erased.
1. Load a word at the current program memory 1. Perform Load Configuration with dummy data to
address using the Load Data For Program Mem- point the PC to 0x2000.
ory command. This location must be address 2. Perform a Bulk Erase Program Memory
modulo 4 equal to 0. command.
2. Issue an Increment Address command to point 3. Wait TERA to complete erase.
to the next address in the block.
3. Load a word at the current program memory 3.1.3 SERIAL PROGRAM/VERIFY
address using the Load Data For Program OPERATION
Memory command.
The ICSPCLK pin is used as a clock input, and the
4. Issue an Increment Address command to point ICSPDAT pin is used for entering command bits and
to the next address in the block. data input/output during serial operation. To input a
5. Load a word at the current program memory command, ICSPCLK is cycled six times. Each
address using the Load Data For Programming command bit is latched on the falling edge of the clock
Memory command. with the LSb of the command being input first. The data
6. Issue and Increment Address command to point input onto the ICSPDAT pin is required to have a
to the next address in the book. minimum setup and hold time (see Table 6-1), with
7. Load a word at the current program memory respect to the falling edge of the clock. Commands that
address using the Load Data For Programming have data associated with them (Read and Load) are
Memory command. specified to have a minimum delay of 1 µs between the
8. Issue a Begin Programming command command and the data. After this delay, the clock pin is
externally timed. cycled 16 times with the first cycle being a Start bit and
the last cycle being a Stop bit.
9. Wait TPROG1.
10. Issue End Programming. During a read operation, the LSb will be transmitted
onto the ICSPDAT pin on the rising edge of the second
11. Wait TDIS.
cycle. For a load operation, the LSb will be latched on
12. Issue an Increment Address command to point the falling edge of the second cycle. A minimum 1 µs
to the start of the next block of addresses. delay is also specified between consecutive
13. Repeat steps 1 through 12 as required to write commands, except for the End Programming
the desired range of program memory. command, which requires a 100 µs (TDIS).
See Table 3-12 for more information. All commands and data words are transmitted LSb first.
Data is transmitted on the rising edge and latched on
the falling edge of the ICSPCLK. To allow for decoding
of commands and reversal of data pin configuration, a
time separation of at least 1 µs (TDLY1) is required
between a command and a data word.
The commands that are available are described in
Table 3-1.

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 MCP19110/11
TABLE 3-1: COMMAND MAPPING FOR MCP19110/11
Command Mapping (MSb … LSb) Data
Load Configuration x x 0 0 0 0 0, data (14), 0
Load Data for Program Memory x x 0 0 1 0 0, data (14), 0
Read Data from Program Memory x x 0 1 0 0 0, data (14), 0
Increment Address x x 0 1 1 0
Begin Programming x 1 1 0 0 0 Externally Timed
End Programming x 0 1 0 1 0
Bulk Erase Program Memory x x 1 0 0 1 Internally Timed
Row Erase Program Memory x 1 0 0 0 1 Internally Timed

3.1.3.1 Load Configuration

The Load Configuration command is used to access
the Configuration Word (0x2007), user ID
(0x2000-0x2003) and Calibration Words (0x2080 to
0x208F). This command sets the PC to address
0x2000 and loads the data latches with one word of
data.
To access the configuration memory, send the Load
Configuration command. Individual words within the
configuration memory can be accessed by sending
Increment Address commands and using load or read
data for program memory.
After the 6-bit command is input, the ICSPCLK pin is
cycled an additional 16 times for the Start bit, 14 bits of
data and the Stop bit (see Figure 3-4).
After the configuration memory is entered, the only way
to get back to the program memory is to exit the
Program/Verify mode by taking MCLR low (VIL).

FIGURE 3-4: LOAD CONFIGURATION COMMAND

TDLY3

1 2 3 4 5 6 1 2 3 4 5 15 16
ICSPCLK

0 00 0 0 X X strt_bit LSb MSb stp_bit

ICSPDAT
TDLY1 TSET1
THLD1

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MCP19110/11
3.1.3.2 Load Data For Program Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described in Section 3.1.3.1 “Load Configuration”.
A timing diagram of this command is shown in
Figure 3-5.

FIGURE 3-5: LOAD DATA FOR PROGRAM MEMORY COMMAND

TDLY2
1 2 3 4 5 6 1 2 3 4 5 15 16
ICSPCLK

0 1 0 0 X X strt_bit LSb MSb stp_bit

ICSPDAT
TSET1 TDLY1 TSET1
THLD1 THLD1

3.1.3.3 Read Data From Program Memory

After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently accessed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge.
If the program memory is code-protected (CP = 0), the
data is read as zeros.
A timing diagram of this command is shown in Figure 3-6.

FIGURE 3-6: READ DATA FROM PROGRAM MEMORY COMMAND

TDLY3

1 2 3 4 5 6 1 2 3 4 5 15 16
ICSPCLK
TDLY3
10 0 1 0 X X MSb stp_bit
ICSPDAT strt_bit
LSb
TSET1
THLD1 TDLY1

input output input

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 MCP19110/11
3.1.3.4 Increment Address
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 3-7. Incrementing past 0x07FF in the program
memory rolls the program counter to ‘0’. Incrementing
past 203Fh in test memory returns the program counter
to 2000h.
It is not possible to decrement the address counter. To
reset this counter, the user should exit and re-enter
Program/Verify mode.

FIGURE 3-7: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

TDLY2
Next Command
1 2 3 4 5 6 1 2
ICSPCLK

0 1 1 0 X X X 0
ICSPDAT
TSET1
THLD1
TDLY1

3.1.3.5 Begin Programming

(Externally Timed)
A Load command must be given before every Begin
Programming command. Programming of the
appropriate memory (program memory, configuration or
calibration memory) will begin after this command is
received and decoded. Programming requires (TPROG)
time and is terminated using an End Programming
command. A timing diagram for this command is shown
in Figure 3-8.
The addressed locations are not erased before
programming.

FIGURE 3-8: BEGIN PROGRAMMING (EXTERNALLY TIMED)

VIHH
MCLR TPROG
End Programming Command
1 2 3 4 5 6 1 2
ICSPCLK

ICSPDAT 0 0 0 1 1 X X 0
TSET1
THLD1

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MCP19110/11
3.1.3.6 End Programming
After this command is performed, the write procedure
will stop. A timing diagram of this command is shown in
Figure 3-9.

FIGURE 3-9: END PROGRAMMING (SERIAL PROGRAM/VERIFY)

VIHH
MCLR
Next Command
1 2 3 4 5 6 1 2
ICSPCLK

ICSPDAT 0 1 0 1 0 X X 0
TDIS
TSET1
THLD1

3.1.3.7 Bulk Erase Program Memory

After this command is performed, the entire program
memory and the Configuration Word (0x2007) are
erased. The user ID and calibration memory may also
be erased, depending on the value of the PC. See
Section 3.1.2 “Erase Algorithms” for erase
sequences. A timing diagram for this command is
shown in Figure 3-10.

FIGURE 3-10: BULK ERASE PROGRAM MEMORY COMMAND

TERA
Next Command
1 2 3 4 5 6 1 2
ICSPCLK

1 0 0 1 X X X 0
ICSPDAT
TSET1 TSET1
THLD1 THLD1

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 MCP19110/11
3.1.3.8 Row Erase Program Memory To perform a Row Erase Program Memory, the
following sequence must be performed:
This command erases the 16-word row of program
memory pointed to by PC<11:4>. If the program 1. Execute a Row Erase Program Memory
memory array is protected (CP = 0), the command is command.
ignored. 2. Wait TERA to complete a row erase.

FIGURE 3-11: ROW ERASE PROGRAM MEMORY COMMAND

TERA
Next Command
1 2 3 4 5 6 1 2
ICSPCLK

1 0 0 0 1 x x 0
ICSPDAT

FIGURE 3-12: ONE-WORD PROGRAMMING FLOWCHART

Start

Bulk Erase
Program Program Cycle
Memory (1,2)
Load Data
for
One-word Program Memory
Program Cycle

Begin
Read Data Programming
from Command
Program Memory (Externally timed)

Report
No Programming
Data Correct? Wait TPROG
Failure
Yes

Increment End
No All Locations
Address Programming
Done?
Command
Yes
Program
User ID/Config. bits Wait TDIS

Done

Note 1: This step is optional if the device has already been erased or has not been previously programmed.
2: If the device is code-protected or must be completely erased, then bulk erase the device per Figure 3-15.

 2013 Microchip Technology Inc. DS20002336B-page 13

MCP19110/11
FIGURE 3-13: FOUR-WORD PROGRAMMING FLOWCHART

Program Cycle
Load Data
for
Program Memory

Increment
Address
Start Command

Bulk Erase
Load Data
Program
for
Memory(1,2) Program Memory

Four-word Increment
Program Cycle Address
Command

Increment Load Data

No All Locations
Address for
Done?
Command Program Memory
Yes
Increment
Program
Address
User ID/Config. bits
Command

Done Load Data

for
Program Memory

Begin
Programming
Command
(Externally timed)

Wait TPROG

End
Programming

Wait TDIS

Note 1: This step is optional if the device is erased or not previously programmed.
2: If the device is code-protected or must be completely erased, then bulk erase the device per Figure 3-15.

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 MCP19110/11
FIGURE 3-14: PROGRAM FLOWCHART – CONFIGURATION MEMORY

Start

PROGRAM CYCLE
Load
Configuration Load Data
for
Program Memory
One-word
Program Cycle
(User ID) Begin
Programming
Command
Read Data (Externally timed)
From Program
Memory Command

Wait TPROG
No Report
Data Correct? Programming
Failure
End
Yes Programming
Increment
Address
Command
Wait TDIS
Increment
No Address = Yes
Address
0x2004? Command

Increment
Address
Command

Increment
Address
Command

One-word
Program Cycle
(Config. bits)

Read Data
From Program
Memory Command

Report
No
Data Correct? Programming
Failure
Yes
Done

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MCP19110/11
FIGURE 3-15: PROGRAM FLOWCHART – ERASE FLASH DEVICE

Start

Load Configuration

Bulk Erase (1)

Program Memory

Done

Note 1: See Section 3.1.3.7 “Bulk Erase Program Memory” for more information on the Bulk Erase
procedure.

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 MCP19110/11
4.0 CONFIGURATION WORD
The MCP19110/11 devices have several Configuration
bits. These bits can be programmed (reads ‘0’) or left
unchanged (reads ‘1’), to select various device
configurations.

REGISTER 4-1: CONFIG: CONFIGURATION WORD (ADDRESS: 2007h)

R/W-1 U-1 R/W-1 R/W-1 U-1 U-1
DBGEN — WRT1 WRT0 — —
bit 13 bit 8

U-0 R/W-1 R/W-1 R/W-1 R/W-1 U-1 U-1 U-1

— CP MCLRE PWRTE WDTE — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13 DBGEN: ICD Debug bit

1 = ICD Debug mode disabled
0 = ICD Debug mode enabled
bit 12 Unimplemented: Read as ‘1’
bit 11-10 WRT<1:0>: Flash Program Memory Self-Write Enable bit
11 = Write protection off
10 = 000h to 3FFh write protected, 400h to FFFh may be modified by PMCON1 control
01 = 000h to 7FFh write protected, 800h to FFFh may be modified by PMCON1 control
00 = 000h to FFFh write protected, the entire program memory is write-protected
bit 9-7 Unimplemented: Read as ‘1’
bit 6 CP: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is external read and write-protected
bit 5 MCLRE: MCLR Pin Function Select bit
1 = MCLR pin is MCLR function and weak internal pull-up is enabled
0 = MCLR pin is alternate function, MCLR function is internally disabled
bit 4 PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0 Unimplemented: Read as ‘1’
Note 1: Bit is reserved and not controlled by user.

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MCP19110/11
4.1 Device ID Word
The device ID word for the MCP19110/11 is loaded at
2006h. This location cannot be erased.

TABLE 4-1: DEVICE ID VALUES

Device ID Values
Device
Dev Rev
MCP19110 00 0111 111 0 0010
MCP19111 10 1111 100 0 0010

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 MCP19110/11
5.0 CODE PROTECTION 5.3 Checksum Computation
For the MCP19110/11, once the CP bit is programmed The checksum is calculated by two different methods
to ‘0’, all program memory locations read all ‘0’s. The user dependent on the setting of the CP Configuration bit.
ID locations and the Configuration Word read out in an
unprotected fashion. Further programming is disabled for 5.3.1 PROGRAM CODE PROTECTION
the entire program memory. DISABLED
The user ID locations and the Configuration Word can With the program code protection disabled, the
be programmed regardless of the state of the CP bit. checksum is computed by reading the contents of the
program memory locations and adding up the program
5.1 Disabling Code Protection memory data starting at address 0x0000h, up to the
maximum user addressable location. Any Carry bit
It is recommended to use the procedure in Figure 3-15 exceeding 16 bits is ignored. Additionally, the relevant
to disable code protection of the device. This sequence bits of the Configuration Words are added to the
will erase the program memory, Configuration Word checksum. All unimplemented Configuration bits are
(0x2007) and user ID locations (0x2000-0x2003). The masked to ‘0’.
Calibration Words (0x2080 to 0x2083) will not be
erased.

5.2 Embedding Configuration Word

and User ID Information in the Hex
File
To allow portability of code, the programmer is required
to read the Configuration Word and user ID locations
from the hex file when loading it. If Configuration Word
information was not present in the hex file, a simple
warning message may be issued. Similarly, while
saving a hex file, Configuration Word and user ID
information must be included. An option to not include
this information may be provided.
Microchip Technology Inc. feels strongly that this
feature is important for the benefit of the end customer.

EXAMPLE 5-1: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED

(CP = 1), MCP19110 AND MCP19111 BLANK DEVICES
Sum of Memory addresses 000h-0FFFh F000h 1
Configuration Word 3FFFh 2
Configuration Word mask 2C78h 3
Checksum = F000h + (3FFFh and 2C78h) 4
= F000h + 2C78h
= 1C78h

Note 1: This value is obtained by taking the total number of program memory locations (0x000h to 0x0FFFh, which
is 0x1000h) and multiplying it by the blank memory value of 0x3FFF to get the sum of 3FF F000h. Then
truncate to 16 bits, thus having a final value of F000h.
2: This value is obtained by making all bits of the Configuration Word a ‘1’, then converting it to hex, thus
having a value of 3FFFh.
3: This value is obtained by making all used bits of the Configuration Word a ‘1’, then converting it to hex,
thus having a value of 2C78h.
4: This value is obtained by ANDing the Configuration Word value with the Configuration Word Mask value
and adding it to the sum of memory addresses (3FFFh and 2C78) + F000h = 11C78h. Then truncate to
16 bits, thus having a final value of 1C78h.

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MCP19110/11
5.3.2 PROGRAM CODE PROTECTION
ENABLED
With the program code protection enabled, the
checksum is computed in the following manner. The
Least Significant nibble of each user ID is used to
create a 16-bit value. The masked value of user ID
location 2000h is the Most Significant nibble. This sum
of user IDs is summed with the Configuration Word (all
unimplemented Configuration bits are masked to ‘0’).

EXAMPLE 5-2: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED

(CP = 0), MCP19110 AND MCP19111 BLANK DEVICES
Configuration Word 3FBFh(1)
Configuration Word mask 2C38h(2)
User ID (2000h) 0006h(3)
User ID (2001h) 0007h(3)
User ID (2002h) 0001h(3)
User ID (2003h) 0002h(3)
Sum of User IDs = (0006h and 000Fh) << 12 + (0007h and 000Fh) << 8 +
(0001h and 000Fh) << 4 + (0002h and 000Fh)(4)
= 6000h + 0700h + 0010h + 0002h
= 6712h
Checksum = (3FBFh and 2C38h) + Sum of User IDs(5)
= 2C38h + 6712h
= 934Ah

Note 1: This value is obtained by making all bits of the Configuration Word a ‘1’, but the code protection bit is ‘0’
(thus, enabled), then converting it to a hex, thus having a value of 3FBFh.
2: This value is obtained by making all used bits of the Configuration Word a ‘1’, but the code protection bit
is ‘0’ (thus, enabled), then converting to hex, thus having a value of 2C38h.
3: These values are picked at random for this example; they can be any 16-bit value.
4: In order to calculate the sum of user IDs, take the 16-bit value of the first user ID location (0006h), AND
the address to (000Fh), thus masking the MSB. This gives you the value 0006h, then shift left 12 bits, giv-
ing you 6000h. Do the same procedure for the 16-bit value of the second user ID location (0007h), except
shift left eight bits. Also do the same for the third user ID location (0001h), except shift left four bits. For
the fourth user ID location, do not shift. Finally, add up all four user ID values to get the final sum of user
IDs of 6712h.
5: This value is obtained by ANDing the Configuration Word value with the Configuration Mask value and
adding it to the sum of user IDs: (3FBFh and 2C38h) + (6712h) = 934Ah.

DS20002336B-page 20  2013 Microchip Technology Inc.

 MCP19110/11
6.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 6-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
Standard Operating Conditions (unless otherwise stated)
AC/DC CHARACTERISTICS Operating Temperature: -40°C  TA +85°C
Operating Voltage: 4.5V  VDD 5.5V
Sym. Characteristics Min. Typ. Max. Units Conditions/Comments
General
VIN VIN level for read/write operations, 4.5 — 32 V
program and data memory
VIN level for Bulk Erase operations, 4.5 — 32 V
program and data memory
VIHH High voltage on MCLR for VDD + 3.5 — 13 V VDD regulated internally
Program/Verify mode entry to 5V
IIHH MCLR current during programming — 300 1000 µA Current into the MCLR pin
TVHHR MCLR rise time (VSS to VHH) for — — 1.0 µs
Program/Verify mode entry
TPPDP Hold time after VPPchanges 5 — — µs
VIH1 (ICSPCLK, ICSPDAT) input high level 0.8 VDD — — V Schmitt Trigger input
VIL1 (ICSPCLK, ICSPDAT) input low level 0.2 VDD — — V Schmitt Trigger input
TSET0 ICSPCLK, ICSPDAT setup time before 100 — — ns
MCLR (Program/Verify mode selec-
tion pattern setup time)
THLD0 Hold time after VDD changes 5 — — µs
Serial Program/Verify
TSET1 Data in setup time before clock 100 — — ns
THLD1 Data in hold time after clock 100 — — ns
TDLY1 Data input not driven to next clock input 1.0 — — µs
(delay required between command/data
or command/command)
TDLY2 Delay between clockto clockof next 1.0 — — µs
command or data
TDLY3 Clock to data out valid (during a Read — — 80 ns
Data command)
TERA Erase cycle time — 5 6 ms
TPROG Programming cycle time 3 — — ms +10°C  TA +40°C
TDIS Time delay from program to compare 100 — — µs
(HV discharge time)

 2013 Microchip Technology Inc. DS20002336B-page 21

MCP19110/11
NOTES:

DS20002336B-page 22  2013 Microchip Technology Inc.

 MCP19110/11
APPENDIX A: REVISION HISTORY

Revision B (July 2013)

The following is the list of modifications:
1. Adding new device MCP19110 to the family and
the related information throughout the
document.
2. Added pinout diagram for MCP19110 device in
Figure 1-1.
3. Added Table 1-1 containing the pin descriptions
in Program/Verify mode for MCP19110 device.
4. Updated Table 4-1.
5. Fixed minor typographical errors.

Revision A (March 2013)

• Original release of this document.

 2013 Microchip Technology Inc. DS20002336B-page 23

MCP19110/11
NOTES:

DS20002336B-page 24  2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of
devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries.
the buyer’s risk, and the buyer agrees to defend, indemnify and
Analog-for-the-Digital Age, Application Maestro, BodyCom,
hold harmless Microchip from any and all damages, claims,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
suits, or expenses resulting from such use. No licenses are
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
conveyed, implicitly or otherwise, under any Microchip
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
intellectual property rights.
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-299-7

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2013 Microchip Technology Inc. DS20002336B-page 25

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DS20002336B-page 26  2013 Microchip Technology Inc.