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Max 78002

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Max 78002

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MAX78002 Artificial Intelligence Microcontroller with

Low-Power Convolutional Neural Network
Accelerator
General Description Benefits and Features
Artificial intelligence (AI) requires extreme computational ● Dual-Core, Low-Power Microcontroller
horsepower, but Analog Devices is cutting the power cord • Arm Cortex-M4 Processor with FPU up to 120MHz
from AI insights. The MAX78002 is a new breed of AI • 2.5MB Flash, 64KB ROM, and 384KB SRAM
microcontroller that enables neural networks to execute • Optimized Performance with 16KB Instruction
at ultra-low power and live at the edge of the IoT. This Cache
device combines the most energy-efficient AI processing • Optional Error Correction Code (ECC SEC-DED)
with Analog Devices' proven ultra-low-power microcon- for SRAM
trollers. Our hardware-based CNN accelerator enables • 32-Bit RISC-V Coprocessor up to 60MHz
battery-powered applications to execute AI inferences • Up to 60 General-Purpose I/O Pins
while expending only millijoules of energy. • MIPI Camera Serial Interface 2 (MIPI CSI-2)
The MAX78002 is an advanced system-on-chip featuring Controller V2.1 – Support for Two Data Lanes
an Arm® Cortex®-M4 with FPU CPU for efficient system • 12-Bit Parallel Camera Interface
control with an ultra-low-power deep neural-network ac- • I2S Controller/Target for Digital Audio Interface
celerator. The CNN engine has a weight storage memory • Secure Digital Interface Supports SD 3.0/SDIO 3.0/
of 2MB, and can support 1-, 2-, 4-, and 8-bit weights (sup- eMMC 4.51
porting networks of up to 16 million weights). The CNN ● Convolutional Neural Network (CNN) Accelerator
weight memory is SRAM-based so that AI network up- • Highly Optimized for Deep CNNs
dates can be made on the fly. The CNN engine also has • 2 Million 8-Bit Weight Capacity with 1-, 2-, 4-, and
1.3MB of data memory. The CNN architecture is highly 8-bit Weights
flexible, allowing networks to be trained in conventional • 1.3MB CNN Data Memory
toolsets like PyTorch® and TensorFlow®, then converted • Programmable Input Image Size up to 2048 x 2048
for execution on the MAX78002 using tools provided by Pixels
Analog Devices. • Programmable Network Depth up to 128 Layers
In addition to the memory in the CNN engine, the • Programmable per Layer Network Channel Widths
MAX78002 has large on-chip system memory for the mi- up to 1024 Channels
crocontroller core with 2.5MB flash and up to 384KB • 1- and 2-Dimensional Convolution Processing
SRAM. Multiple high-speed and low-power communica- • Capable of Processing VGA Images at 30fps
tions interfaces are supported, including I2S, MIPI® ● Power Management for Extending Battery Life
CSI-2® serial camera, parallel camera (PCIF), and SD 3.0/ • Integrated Single-Inductor Multiple-Output (SIMO)
SDIO 3.0/eMMC 4.51 secure digital. Switch-Mode Power Supply (SMPS)
The device is available in a 144 CSBGA, 12mm x 12mm, • 2.85V to 3.6V Supply Voltage Range
0.8mm pitch package. • Support of Optional External Auxiliary CNN Power
Supply
• Dynamic Voltage Scaling Minimizes Active Core
Applications Power Consumption
● Factory Robot and Drone Navigation • 23.9μA/MHz While Loop Execution at 3.3V from
● Industrial Sensors and Process Control Cache (CM4 only)
● Inline Quality Assurance Vision Systems • Selectable SRAM Retention in Low-Power Modes
● Smart Security Cameras with Real-Time Clock (RTC) Enabled
● Portable Medical Diagnostics Equipment
● Security and Integrity
Arm and Cortex are registered trademarks of Arm Limited. • Available Secure Boot
Coremark is a registered trademark of EEMBC. • AES 128/192/256 Hardware Acceleration Engine
CSI-2 and MIPI are registered trademarks of MIPI Al- • True Random Number Generator (TRNG) Seed
liance, Inc. Generator

PyTorch is a registered trademark of Facebook, Inc.

TensorFlow is a registered trademark of Google, Inc.

Ordering Information appears at the end of the data sheet. 19-101571; Rev 0; 6/22

One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2022 Analog Devices, Inc. All rights reserved.
MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
Simplified Block Diagram

MAX78002
200MHz (IPLL_CNN)
HFXOUT
25MHz (ERFO) VCNN0
HFXIN
100MHz (IPLL) Arm Cortex-M4 WITH
FPU VCNN0RAM
120MHz (IPO)
120MHz (CM4)
7.3728MHz (IBRO)
VCNN1
32.768kHz (ERTCO) ÷2 NVIC
8kHz (INRO)
VCNN1RAM
EXTERNAL CLOCK CONVOLUTIONAL NEURAL NETWORK
2M WEIGHT AI ACCELERATOR
60MHz (ISO) 32-BIT RISC-V (RV32)
VCNN2
32KIN RTC WITH
VCNN2RAM
32KOUT WAKEUP TIMER
MEMORY
VCNN3
POWER-ON RESET, BROWNOUT FLASH 2.5MB
RSTN MONITOR, SUPPLY VOLTAGE
MONITORS SRAM 384KB VCNN3RAM

SRAM0 SERIAL WIRE DEBUG

VREGI 32KB + ECC
VBAT
SRAM1 SD3.0/SDIO3.0/

Tx/Rx
FIFO
VDDA
32KB eMMC 4.51 HOST
VSSPWR
VSS SRAM2 GPIO/
I2S CONTROLLER/
Tx/Rx
VSSA FIFO ALTERNATE
MULTILAYER BUS MATRIX – AHB/APB

64KB TARGET
LXA FUNCTION
SHARED PAD
LXB SRAM3 UP TO 60
3 × HIGH-SPEED I2C FUNCTIONS
Tx/Rx
FIFO

VBST 64KB
CONTROLLER
VREGO_A SRAM4 TIMERS/PWM
SIMO VOLTAGE REGULATION,
VREGO_B 64KB CAPTURE/
DYNAMIC VOLTAGE SCALING,
Tx/Rx
FIFO

VREGO_C 4-WIRE UART COMPARE

AND SRAM5
VCNN0_EN POWER CONTROL LPTIMERS
VCNN0RAM_EN 64KB SERIAL WIRE
Tx/Rx
FIFO

2 x 2-WIRE UART DEBUG

VCNN1_EN SRAM6
VCNN1RAM_EN 48KB
VCNN2_EN SPI
Tx/Rx
FIFO

SRAM7 2-WIRE LPUART

VCNN2RAM_EN I2 C
VCNN3_EN 16KB UART
VCNN3RAM_EN 2 x SPI CONTROLLER/ LPUART
Tx/Rx
FIFO

CACHE 16KB TARGET PARALLEL

VDDIO
VDDIOH CAMERA
1-Wire CONTROLLER (OWM) INTERFACE
VCOREA 64KB BOOT ROM
1-Wire
VCOREB 4 × PULSE TRAIN ENGINES
SD/SDIO/eMMC
I/O I/O DIGITAL/ ANALOG 16KB USER OTP 12-BIT SAR ADC
MEMORIES 4 × 32-BIT TIMERS
WAKEUP TIMER MICROPOWER
CSI_CKP COMPARATORS
4-CH DMA 2 × 32-BIT LPTIMERS
CSI_CKN
2 × WATCHDOG TIMER EXTERNAL
CSI_D0P MIPI CSI-2 PARALLEL CAMERA INTERRUPTS
CSI_D0N CAMERA UNIQUE ID INTERFACE
SERIAL
CSI_D1P INTERFACE 4 MICROPOWER COMPARATORS
CSI_D1N
VCSI2P5 4

DP 4 8
DM
USB 2.0 HI-SPEED 8
PHY

VDDB CONTROLLER VCOREA

VSSB VCOREB
VUSB0P9 12-BIT 1MSPS 2.5V LDO
ADC (SAR) 0.9V LDO
SECURITY VDDA TEMPERATURE
AES-128/192/256 SECURE NV KEY SECURE BOOT SENSOR
VBAT
32-BIT CRC TRUE RANDOM NUMBER VDDB
ACCELERATOR GENERATOR (TRNG) VSS
VREF

[Link] Analog Devices | 2

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
144 CSBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics—I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical Characteristics—SD/SDIO/SDHC/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Electrical Characteristics—SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Electrical Characteristics—I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Electrical Characteristics—PCIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Electrical Characteristics—1-Wire Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
144 CSBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Arm Cortex-M4 with FPU Processor and RISC-V RV32 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Convolutional Neural Network Accelerator (CNN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Internal Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Internal SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Dynamic Voltage Scaling (DVS) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General-Purpose I/O (GPIO) and Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
MIPI Camera Serial Interface 2 (MIPI CSI-2) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Parallel Camera Interface (PCIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Single-Inductor Multiple-Output Switch-Mode Power Supply (SIMO SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ACTIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
LOW POWER Mode (LPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MICRO POWER Mode (μPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STANDBY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
BACKUP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

[Link] Analog Devices | 3

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
TABLE OF CONTENTS (CONTINUED)
POWER DOWN Mode (PDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Wakeup Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Programmable Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
32-Bit Timer/Counter/PWM (TMR, LPTMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pulse Train Engine (PT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Serial Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
High-Speed USB Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I2C Interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I2S Interface (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
UART (UART, LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1-Wire Controller (OWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Standard DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
True Random Number Generator (TRNG) Non-Deterministic Random Bit Generator (NDRBG) . . . . . . . . . . . . . 53
CRC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Secure Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Debug and Development Interface (SWD, JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Bootloader Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

[Link] Analog Devices | 4

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
LIST OF FIGURES
Figure 1. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2. SD/SDIO/SDHC/MMC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3. SPI Controller Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4. SPI Target Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. I2S Target ModeTiming Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 6. I2S Controller Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7. Parallel Camera Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. 1-Wire Controller Data Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

[Link] Analog Devices | 5

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
LIST OF TABLES
Table 1. BACKUP Mode SRAM Retention Block Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 2. Wakeup Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 3. Timer Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 4. Watchdog Timer Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 5. SPI Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 6. UART Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 7. Common CRC Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 8. Bootloader Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

[Link] Analog Devices | 6

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Absolute Maximum Ratings

VCOREA, VCOREB ............................................... -0.3V to +1.21V HFXIN, HFXOUT ................................... -0.3V to VCOREA + 0.2V
VCNN0, VCNN1, VCNN2, VCNN3 .......................... -0.3V to +1.21V CSI_CKP, CSI_CKN, CSI_D0P, CSI_D0N, CSI_D1P,
VCNN0RAM, VCNN1RAM, VCNN2RAM, VCNN3RAM ...........-0.3V to CSI_D1N ............................................................ -0.3V to VCSI2P5
+1.21V VDDIO Combined Pins (sink) .............................................100mA
VUSB0P9 .............................................................. -0.3V to +1.21V VDDIOH Combined Pins (sink) ...........................................100mA
VCSI2P5 ............................................................... -0.3V to +2.75V VSSA ..................................................................................100mA
VDDB (with respect to VSSB) ................................. -0.3V to +3.6V VSS ...........................................................................................6A
VDDIO .................................................................. -0.3V to +1.89V VSSPWR .............................................................................100mA
VDDIOH .................................................................. -0.3V to +3.6V Output Current (sink) by any GPIO Pin................................25mA
VBAT ...................................................................... -0.3V to +3.6V Output Current (source) by any GPIO Pin ......................... -25mA
VREGI .................................................................... -0.3V to +3.6V Continuous Package Power Dissipation CSBGA (multilayer
VDDA ................................................................... -0.3V to +1.89V board) TA = +70°C (derate 39.37mW/°C above +70°C)(Note
VREF ............................................................ -0.3V to VBAT + 0.3V 1) ................................................................................3149.61mW
DM, DP (with respect to VSSB).............................. -0.3V to +3.6V Operating Temperature Range ...........................-40°C to +105°C
GPIO (VDDIO) ............................................ -0.3V to VDDIO + 0.5V Storage Temperature Range ..............................-65°C to +125°C
RSTN, GPIO (VDDIOH) ............................-0.3V to VDDIOH + 0.5V Soldering Temperature ..................................................... +260°C
32KIN, 32KOUT ......................................... -0.3V to VDDA + 0.2V
Note 1: Continuous Package Power Dissipation CSBGA can be exceeded with special cooling considerations.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Package Information
144 CSBGA
Package Code X14422+2C
Outline Number 21-0163
Land Pattern Number 90-0185
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 25.4°C/W
Junction to Case (θJC) 5.6°C/W
For the latest package outline information and land patterns (footprints), go to [Link]/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to [Link]/
thermal-tutorial.

Electrical Characteristics
(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at
TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
VREGI, VBAT, and VDDIOH must be
Input Supply Voltage,
VBAT connected together at the circuit-board 2.85 3.3 3.6 V
Battery
level.

[Link] Analog Devices | 7

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

[Link] Analog Devices | 8

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at
TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Dynamic, IPO enabled, fSYS_CLK(MAX) =
120MHz, total current into VREGI pin,
VREGI = 3.3V, VCOREA = VCOREB =
1.1V, CM4 in Active mode executing
CoreMark®, RV32 in ACTIVE mode
32
executing While(1), ECC disabled, all
CNN quadrants disabled, all CNN
memory disabled; inputs tied to VSS,
VDDIO, or VDDIOH; outputs source/sink
0mA
Dynamic, IPO enabled, fSYS_CLK(MAX) =
120MHz, total current into VREGI pin,
VREGI = 3.3V, VCOREA = VCOREB =
1.1V, CM4, and RV32 in ACTIVE mode
executing While(1), ECC disabled, all 27.7
CNN quadrants disabled, all CNN
memory disabled; inputs tied to VSS,
VDDIO, or VDDIOH; outputs source/sink
IREGI_DACT 0mA μA/MHz
Dynamic, IPO enabled, fSYS_CLK(MAX) =
120MHz, total current into VREGI pin,
VREGI = 3.3V, VCOREA = VCOREB =
VREGI Current, ACTIVE
1.1V, CM4 in ACTIVE mode executing
Mode
While(1), RV32 in SLEEP mode, ECC 23.9
disabled, all CNN quadrants disabled, all
CNN memory disabled; inputs tied to
VSS, VDDIO, or VDDIOH; outputs source/
sink 0mA
Dynamic, total current into VREGI pin,
VREGI = 3.3V, VCOREA = VCOREB =
1.1V, fSYS_CLK = ISO; CM4 in SLEEP
mode, RV32 in ACTIVE mode running
from PCLK executing While(1), ECC 20.9
disabled, all CNN quadrants disabled, all
CNN memory disabled; inputs tied to
VSS, VDDIO, or VDDIOH; outputs source/
sink 0mA
Fixed, IPO enabled, ISO enabled, total
current into VREGI, VREGI = 3.3V,
VCOREA = VCOREB = 1.1V, CM4 in
ACTIVE mode 0MHz, RV32 in ACTIVE
IREGI_FACT 823 μA
mode 0MHz, all CNN quadrants disabled,
all CNN memory disabled; inputs tied to
VSS, VDDIO, or VDDIOH; outputs source/
sink 0mA

[Link] Analog Devices | 9

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at
TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Dynamic, IPO enabled, fSYS_CLK(MAX) =
120MHz, ISO enabled, total current into
VREGI pins, VREGI = 3.3V, VCOREA =
VCOREB = 1.1V, CM4 in SLEEP mode,
RV32 in SLEEP mode, ECC disabled, all
IREGI_DSLP 11.8 μA/MHz
CNN quadrants disabled, all CNN
memory disabled, standard DMA with 2
channels active; inputs tied to VSS,
VREGI Current, SLEEP VDDIO, or VDDIOH; outputs source/sink
Mode 0mA
Fixed, IPO enabled, ISO enabled, total
current into VREGI pins, VREGI = 3.3V,
VCOREA = VCOREB = 1.1V, CM4 in
SLEEP mode, RV32 in SLEEP mode,
IREGI_FSLP 1.3 mA
ECC disabled, all CNN quadrants
disabled, all CNN memory disabled;
inputs tied to VSS, VDDIO, or VDDIOH;
outputs source/sink 0mA
Dynamic, ISO enabled, total current into
VREGI pins, VREGI = 3.3V, VCOREA =
VCOREB = 1.1V, CM4 powered off, RV32
in ACTIVE mode executing While(1),
IREGI_DLP 18.9 μA/MHz
fSYS_CLK(MAX) = 60MHz, all CNN
quadrants disabled, all CNN memory
disabled; inputs tied to VSS, VDDIO, or
VREGI Current, LOW VDDIOH; outputs source/sink 0mA
POWER Mode
Fixed, ISO enabled, total current into
VREGI pins, VREGI = 3.3V, VCOREA =
VCOREB = 1.1V, CM4 powered off, RV32
IREGI_FLP in ACTIVE mode 0MHz, all CNN 393 μA
quadrants disabled, all CNN memory
disabled; inputs tied to VSS, VDDIO, or
VDDIOH; outputs source/sink 0mA
Dynamic, ERTCO enabled, IBRO
enabled, total current into VREGI pins,
VREGI = 3.3V, VCOREA = VCOREB =
VREGI Current, MICRO 1.1V, LPUART active, fLPUART =
IREGI_DMP 230 μA
POWER Mode 32.768kHz, all CNN quadrants disabled,
all CNN memory disabled; inputs tied to
VSS, VDDIO, or VDDIOH; outputs source/
sink 0mA
Fixed, total current into VREGI pins,
VREGI = 3.3V, VCOREA = VCOREB =
VREGI Current, 1.1V, all CNN quadrants disabled, all
IREGI_STBY 9.8 μA
STANDBY Mode CNN memory disabled; inputs tied to
VSS, VDDIO, or VDDIOH; outputs source/
sink 0mA

[Link] Analog Devices | 10

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at
TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Total current into All SRAM retained 8.2
VREGI pins, VREGI No SRAM retention 3
= 3.3V, VCOREA =
VCOREB = 1.1V, SRAM0 retained 3.5
RTC disabled, all SRAM0 and
VREGI Current, CNN quadrants 4
IREGI_BK SRAM1 retained μA
BACKUP Mode disabled, all CNN
memory disabled;
inputs tied to VSS, SRAM0, SRAM1,
VDDIO, or VDDIOH; and SRAM2 4.8
outputs source/sink retained
0mA
Total current into VREGI pins, VREGI =
VREGI Current, POWER
IREGI_PDM 3.3V; inputs tied to VSS, VDDIO, or 0.76 μA
DOWN Mode
VDDIOH; outputs source/sink 0mA
VREGO_A Output VREGO_A_RA
VREGI ≥ VREGO_A + 200mV 0.5 1.8 1.85 V
Voltage Range NGE
VREGO_B Output VREGO_B_RA
VREGI ≥ VREGO_B + 200mV 0.5 1.0 1.25 V
Voltage Range NGE
VREGO_C Output VREGO_C_RA
VREGI ≥ VREGO_C + 200mV 0.5 1.0 1.25 V
Voltage Range NGE
VREGO_A Output VREGO_A_IOU
VREGO_A output current 5 50 mA
Current T
VREGO_B Output VREGO_B_IOU
VREGO_B output current 5 50 mA
Current T
VREGO_C Output VREGO_C_IOU
VREGO_C output current 10 100 mA
Current T
VREGO_X Output VREGO_X_IOU
All three VREGO_X outputs combined 20 100 mA
Current Combined T_TOT
VREGI = 3.3V, VREGO_X = 1.1V,
VREGO_X Efficiency VREGO_X_EFF 90 %
load = 30mA
SLEEP Mode Resume Time from power mode exit to execution
tSLP_ON 0.74 μs
Time of first user instruction
LOW-POWER Mode Time from power mode exit to execution
tLP_ON 1.62 μs
Resume Time of first user instruction
MICROPOWER Mode Time from power mode exit to execution
tMP_ON 17.4 μs
Resume Time of first user instruction
STANDBY Mode Time from power mode exit to execution
tSTBY_ON 29.6 μs
Resume Time of first user instruction
BACKUP Mode Resume Time from power mode exit to execution
tBKU_ON 1.9 ms
Time of first user instruction
POWER-DOWN Mode Time from power mode exit to execution
tPDM_ON 5 ms
Resume Time of first user instruction

[Link] Analog Devices | 11

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

External Low Power

fEXT_LPTMR2_
Timer2 Clock Input LPTMR2_CLK selected 8 MHz
Frequency CLK

[Link] Analog Devices | 12

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

[Link] Analog Devices | 13

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at
TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IVCNN_ALL_F 117
ICNN0RAM_F 24.5
200MHz clock rate, CNN active current,
ICNN1RAM_F max power network, random data, and 0.132
ICNN2RAM_F random mask configuration, CNN 0.131
CNN Current Mode F mA
ICNN3RAM_F quadrant 0 enabled, CNN quadrant 1/2/3 0.128
disabled, all CNN quadrants and SRAMs
ICOREA_F powered 7.9
ICNN_TOTAL_
150
F
IVCNN_ALL_G 242
ICNN0RAM_G 16
ICNN1RAM_G 10.4
200MHz clock rate, CNN active current,
ICNN2RAM_G 9.5
CNN Current Mode G all CNN quadrants and SRAMs powered, mA
ICNN3RAM_G unet_v5 functional test 9.5
ICOREA_G 7.9
ICNN_TOTAL_
295
G
IVCNN_ALL_H 1060
ICNN0RAM_H 94
ICNN1RAM_H 200MHz clock rate, CNN active current, 94
max processing configuration, max power
ICNN2RAM_H 94
CNN Current Mode H network, random data, and random mask mA
ICNN3RAM_H configuration, all CNN quadrants and 94
ICOREA_H SRAMs powered 8.2
HICNN_TOTAL
1440
_7
IVCNN_ALL_J 1450
ICNN0RAM_J 99
ICNN1RAM_J 200MHz clock rate, CNN active current, 99
ICNN2RAM_J max processing configuration, max power 99
CNN Current Mode J mA
ICNN3RAM_J network, data, mask configuration, all 99
CNN quadrants and SRAMs powered
ICOREA_J 8.4
ICNN_TOTAL_
1852
J
GENERAL-PURPOSE I/O
Input Low Voltage for All
VDDIO selected as I/O supply; P3.0 and 0.3 ×
GPIOs Except P3.0 and VIL_VDDIO V
P3.1 can only use VDDIOH as I/O supply VDDIO
P3.1
Input Low Voltage for All 0.3 ×
VIL_VDDIOH VDDIOH selected as I/O supply V
GPIOs VDDIOH

[Link] Analog Devices | 14

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at
TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Low Voltage for 0.5 x
VIL_RSTN V
RSTN VDDIOH
Input High Voltage for
VDDIO selected as I/O supply; P3.0 and 0.7 ×
All GPIOs Except P3.0 VIH_VDDIO V
P3.1 can only use VDDIOH as I/O supply VDDIO
and P3.1
Input High Voltage for 0.7 ×
VIH_VDDIOH VDDIOH selected as I/O supply V
All GPIOs VDDIOH
Input High Voltage for 0.5 x
VIH_RSTN V
RSTN VDDIOH
VDDIO selected as
I/O supply,
VDDIO = 1.71V, 0.2 0.4
GPIOn_DS_SEL[1:
0] = 00, IOL = 1mA
VDDIO selected as
I/O supply,
VDDIO = 1.71V, 0.2 0.4
GPIOn_DS_SEL[1:
Output Low Voltage for P3.0 and P3.1 can 0] = 01, IOL = 2mA
All GPIOs Except P3.0 VOL_VDDIO only use VDDIOH V
and P3.1 as I/O supply VDDIO selected as
I/O supply,
VDDIO = 1.71V, 0.2 0.4
GPIOn_DS_SEL[1:
0] = 10, IOL = 4mA
VDDIO selected as
I/O supply,
VDDIO = 1.71V, 0.2 0.4
GPIOn_DS_SEL[1:
0] = 11, IOL = 8mA
VDDIOH selected as I/O supply, VDDIOH
= 2.85V, GPIOn_DS_SEL[1:0] = 00, IOL 0.2 0.4
= 1mA
VDDIOH selected as I/O supply, VDDIOH
= 2.85V, GPIOn_DS_SEL[1:0] = 01, IOL 0.2 0.4
Output Low Voltage for = 2mA
VOL_VDDIOH V
All GPIOs VDDIOH selected as I/O supply, VDDIOH
= 2.85V, GPIOn_DS_SEL[1:0] = 10, IOL 0.2 0.4
= 4mA
VDDIOH selected as I/O supply, VDDIOH
= 2.85V, GPIOn_DS_SEL[1:0] = 11, IOL 0.2 0.4
= 8mA
Combined IOL, All
IOL_TOTAL 48 mA
GPIOs

[Link] Analog Devices | 15

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at
TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDDIO selected as
I/O supply,
VDDIO -
VDDIO = 1.71V,
0.4
GPIOn_DS_SEL[1:
0] = 00, IOL = -1mA
VDDIO selected as
I/O supply,
VDDIO -
VDDIO = 1.71V,
0.4
GPIOn_DS_SEL[1:
Output High Voltage for P3.0 and P3.1 can 0] = 01, IOL = -2mA
All GPIOs Except P3.0 VOH_VDDIO only use VDDIOH V
and P3.1 as I/O supply VDDIO selected as
I/O supply,
VDDIO -
VDDIO = 1.71V,
0.4
GPIOn_DS_SEL[1:
0] = 10, IOL = -4mA
VDDIO selected as
I/O supply,
VDDIO -
VDDIO = 1.71V,
0.4
GPIOn_DS_SEL[1:
0] = 11, IOL = -8mA
VDDIOH selected as I/O supply, VDDIOH
VDDIOH
= 2.85V, GPIOn_DS_SEL[1:0] = 00, IOL
- 0.4
= -1mA
VDDIOH selected as I/O supply, VDDIOH
VDDIOH
= 2.85V, GPIOn_DS_SEL[1:0] = 01, IOL
Output High Voltage for - 0.4
= -2mA
All GPIOs Except P3.0 VOH_VDDIOH V
and P3.1 VDDIOH selected as I/O supply, VDDIOH
VDDIOH
= 2.85V, GPIOn_DS_SEL[1:0] = 10, IOL
- 0.4
= -4mA
VDDIOH selected as I/O supply, VDDIOH
VDDIOH
= 2.85V, GPIOn_DS_SEL[1:0] = 11, IOL
- 0.4
= -8mA
Output High Voltage for VDDIOH = 2.85V, GPIOn_DS_SEL[1:0] VDDIOH
VOH_VDDIOH V
P3.0 and P3.1 fixed at 00, IOL = -1mA - 0.4
Combined IOH, All
IOH_TOTAL -48 mA
GPIOs
Input Hysteresis
VHYS 300 mV
(Schmitt)
VDDIO = 1.89V, VDDIOH = 3.6V,
Input Leakage Current
IIL VDDIOH selected as I/O supply, VIN = 0V, -200 +200 nA
Low
internal pull-up disabled

[Link] Analog Devices | 16

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at
TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH
IIH selected as I/O supply, VIN = 3.6V, -1000 +1000 nA
internal pull-down disabled
Input Leakage Current
VDDIO = 0V, VDDIOH = 0V, VDDIO
High IOFF -1 +1
selected as I/O supply, VIN < 1.89V
μA
VDDIO = 1.71V, VDDIOH = 2.85V, VDDIO
IIH3V -2 +2
selected as I/O supply, VIN = 3.6V
Input Pull-up Resistor
RPU_R Pull-up to VDDIOH 25 kΩ
RSTN
Input Pull-up/Pull-down RPU1 Normal resistance, P1M = 0 25 kΩ
Resistor for All GPIO RPU2 Highest resistance, P1M = 1 1 MΩ
12-BIT SAR ADC
Resolution 12 bits
ADC_CLKCTRL.clksel = 11; AINx input
Effective Number of Bits ENOB 10 bits
pk--pk = VREF - 10mV
External Reference
VREF VREF ≤ VDDIOH 2.048 VDDIOH V
Voltage
MCR_ADC_CFG0.ext_ref = 0,
VINT_REF 1.25
Internal Reference MCR_ADC_CFG0.ref_sel = 0
V
Voltage MCR_ADC_CFG0.ext_ref = 0,
VINT_REF 2.048
MCR_ADC_CFG0.ref_sel = 1
ADC Clock Rate fACLK 1 MHz
ADC Clock Period tACLK 1/fACLK μs
MCR_ADCCFG2.c VSSA +
VREF
hX = 00 0.05
MIN(2 x
AIN[7:0], MCR_ADCCFG2.c VSSA +
VREF,VD
Input Voltage Range VAIN ADC_DATA.chan = hX = 01 0.05 V
[7:0] DIOH)
MIN(2 x
MCR_ADCCFG2.c VSSA +
VREF,VD
hX = 10 0.05
DIOH)
MCR_ADCCFG2.chX = 01 5
Input Impedance RAIN kΩ
MCR_ADCCFG2.chX = 10 50
Analog Input Fixed capacitance to VSSA 2 pF
CAIN
Capacitance Dynamically switched capacitance 1.2 pF
Integral Nonlinearity INL ±1.5 LSb
Differential Nonlinearity DNL ±0.75 LSb
Chopping disabled ±9
Offset Error VOS LSb
Chopping enabled ±0.2

[Link] Analog Devices | 17

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

[Link] Analog Devices | 18

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.
Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at
TA = +105°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
USB
USB Transceiver Supply
VDDB 3.0 3.3 3.6 V
Voltage
Pin Capacitance (DP,
CIN_USB Pin to VSSB 8 pF
DM)
Driver Output
RDRV Steady state drive 44 ±10% Ω
Resistance
USB / FULL SPEED
Single-Ended Input High
VIH_USB 2.1 V
Voltage (DP, DM)
Single-Ended Input Low
VIL_USB 0.5 V
Voltage (DP, DM)
Output High Voltage RL = 1.5kΩ from DP and DM to VSSB,
VOH_USB 2.8 VDDB V
(DP, DM) IOH = -4mA
Output Low Voltage
VOL_USB RL = 1.5kΩ from DP to VDDB, IOL = 4mA VSS 0.3 V
(DP, DM)
Differential Input
VDI |DP to DM| 0.2 V
Sensitivity
Common-Mode Voltage
VCM Includes VDI range 0.8 2.5 V
Range
Transition Time (Rise/
tRF CL = 50pF 4 20 ns
Fall) DP, DM
Pull-up Resistor on
RPU 1.05 1.5 1.95 kΩ
Upstream Ports
USB / HI-SPEED
Hi-Speed Data Signaling
Common-Mode Voltage VHSCM -50 +500 mV
Range
Hi-Speed Squelch Squelch detected 100
VHSSQ mV
Detection Threshold No squelch detected 200
Hi-Speed Idle Level
VHSOI -10 +10 mV
Output Voltage
Hi-Speed Low-Level
VHSOL -10 +10 mV
Output Voltage
Hi-Speed High-Level
VHSOH 400 ±40 mV
Output Voltage
Chirp-J Output Voltage 900
VCHIRPJ mV
(Differential) ±200
Chirp-K Output Voltage -700
VCHIRPK mV
(Differential) ±200

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

[Link] Analog Devices | 20

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics (continued)

Electrical Characteristics—I2C
(TIming specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STANDARD-MODE
Standard-mode, from VIH(MIN) to
Output Fall Time tOF 150 ns
VIL(MAX)
SCL Clock Frequency fSCL 0 100 kHz
Low Period SCL Clock tLOW 4.7 μs
High Time SCL Clock tHIGH 4.0 μs
Setup Time for
Repeated Start tSU;STA 4.7 μs
Condition
Hold Time for Repeated
tHD;STA 4.0 μs
Start Condition
Data Setup Time tSU;DAT 300 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and
tR 800 ns
SCL
Fall Time for SDA and
tF 200 ns
SCL
Setup Time for a Stop
tSU;STO 4.0 μs
Condition
Bus Free Time Between
a Stop and Start tBUS 4.7 μs
Condition
Data Valid Time tVD;DAT 3.45 μs
Data Valid Acknowledge
tVD;ACK 3.45 μs
Time

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics—I2C (continued)

(TIming specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FAST-MODE
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 150 ns
Pulse Width Suppressed
tSP 75 ns
by Input Filter
SCL Clock Frequency fSCL 0 400 kHz
Low Period SCL Clock tLOW 1.3 μs
High Time SCL Clock tHIGH 0.6 μs
Setup Time for
Repeated Start tSU;STA 0.6 μs
Condition
Hold Time for Repeated
tHD;STA 0.6 μs
Start Condition
Data Setup Time tSU;DAT 125 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and
tR 30 ns
SCL
Fall Time for SDA and
tF 30 ns
SCL
Setup Time for a Stop
tSU;STO 0.6 μs
Condition
Bus Free Time Between
a Stop and Start tBUS 1.3 μs
Condition
Data Valid Time tVD;DAT 0.9 μs
Data Valid Acknowledge
tVD;ACK 0.9 μs
Time
FAST-MODE PLUS
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 80 ns
Pulse Width Suppressed
tSP 75 ns
by Input Filter
SCL Clock Frequency fSCL 0 1000 kHz
Low Period SCL Clock tLOW 0.5 μs
High Time SCL Clock tHIGH 0.26 μs
Setup Time for
Repeated Start tSU;STA 0.26 μs
Condition
Hold Time for Repeated
tHD;STA 0.26 μs
Start Condition
Data Setup Time tSU;DAT 50 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and
tR 50 ns
SCL
Fall Time for SDA and
tF 30 ns
SCL

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics—I2C (continued)

(TIming specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Setup Time for a Stop
tSU;STO 0.26 μs
Condition
Bus Free Time Between
0.5
a Stop and Start tBUS μs
Condition
Data Valid Time tVD;DAT 0.45 μs
Data Valid Acknowledge
tVD;ACK 0.45 μs
Time

Electrical Characteristics—SD/SDIO/SDHC/MMC
(TIming specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Clock Frequency in Data
fSDHC_CLK 0 fPCLK MHz
Transfer Mode
1/fSDHC
Clock Period tCLK ns
_CLK
Clock Low Time tWCL 7 ns
Clock High Time tWCH 7 ns
Input Setup Time tISU 5 ns
Input Hold Time tIHLD 1 ns
Output Valid Time tOVLD 5 ns
Output Hold Time tOHLD 6 ns

Electrical Characteristics—SPI
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CONTROLLER MODE
SPI Controller Operating fSYS_CLK = 120MHz,
fMCK0 60 MHz
Frequency for SPI0 fMCK0(MAX) = fSYS_CLK/2
SPI Controller Operating fSYS_CLK = 120MHz,
fMCK1 30 MHz
Frequency for SPI1 fMCK1(MAX) = fSYS_CLK/4
SPI Controller SCK
tMCKX 1/fMCKX ns
Period
SCK Output Pulse-
tMCH, tMCL tMCKX/2 ns
Width High/Low
MOSI Output Hold Time
tMOH tMCKX/2 ns
After SCK Sample Edge
MOSI Output Valid to
tMOV tMCKX/2 ns
Sample Edge
MOSI Output Hold Time
tMLH tMCKX/2 ns
After SCK Low Idle

[Link] Analog Devices | 23

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics—SPI (continued)

(Timing specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MISO Input Valid to
SCK Sample Edge tMIS 5 ns
Setup
MISO Input to SCK
tMIH tMCKX/2 ns
Sample Edge Hold
TARGET MODE
SPI Target Operating
fSCK 60 MHz
Frequency
SPI Target SCK Period tSCK 1/fSCK ns
SCK Input Pulse-Width
tSCH, tSCL tSCK/2 ns
High/Low
SSx Active to First Shift
tSSE 10 ns
Edge
MOSI Input to SCK
Sample Edge Rise/Fall tSIS 3 ns
Setup
MOSI Input from SCK
Sample Edge Transition tSIH 3 ns
Hold
MISO Output Valid After
SCLK Shift Edge tSOV 10 ns
Transition
SCK Inactive to SSx
tSSD 10 ns
Inactive
SSx Inactive Time tSSH 1/fSCK ns
MISO Hold Time After
tSLH 10 ns
SSx Deassertion

Electrical Characteristics—I2S
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TARGET
Bit Clock Frequency fBCLKS 25 MHz
Bit Clock Period tBCLKS 1/fBCLKS μs
1
BCLK High Time tWBCLKHS 0.5 × μs
fBCLKS

1
BCLK Low Time tWBCLKLS 0.5 × μs
fBCLKS

Setup Time for LRCLK tLRCLK_BLCKS 20 ns

Delay Time, BCLK to
tBCLK_SDOS 20 ns
SD (Output) Valid
Setup Time for SD
tSU_SDIS 10 ns
(Input)
Hold Time SD (Input) tHD_SDIS 10 ns

[Link] Analog Devices | 24

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics—I2S (continued)

(Timing specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CONTROLLER
Source only from I2S_EXTCLK (P0.14
Bit Clock Frequency fBCLKM 80 MHz
Alternate Function 2)
1/fBCLK
Bit Clock Period tBCLKM μs
M
1
BCLK High Time tWBCLKHM 0.5 × μs
fBCLKM

1
BCLK Low Time tWBCLKLM 0.5 × μs
fBCLKM

Delay Time BCLK to tBLCK_LRCLK

20 ns
LRCLK Valid M
Delay Time, BCLK to
tBCLK_SDOM 20 ns
SD (Output) Valid
Setup Time for SD
tSU_SDIM 10 ns
(Input)
Hold Time SD (Input) tHD_SDIM 10 ns

Electrical Characteristics—PCIF
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PCIF
PCIF Operating
fCLK 10 MHz
Frequency
PCIF Clock Period tCLK 1/fCLK ns
PCIF_PCLK Output
tWCH, tWCL tCLK/2 ns
Pulse-Width High/Low
PCIF_VSYNC,
PCIF_HSYNC Setup tSSU 5 ns
Time
PCIF_VSYNC,
PCIF_HSYNC Hold tSHLD 5 ns
Time
PCIF_D0-PCIF_D11
tDSU 5 ns
Setup TIme
PCIF_D0-PCIF_D11
tDHLD 5 ns
Hold Time

Electrical Characteristics—1-Wire Controller

(Timing specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Standard 60
Write 0 Low Time tW0L μs
Overdrive 8

[Link] Analog Devices | 25

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Electrical Characteristics—1-Wire Controller (continued)

(Timing specifications are guaranteed by design and not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Standard 6
Write 1 Low Time tW1L Standard, Long Line mode 8 μs
Overdrive 1
Standard 70
Presence Detect
tMSP Standard, Long Line mode 85 μs
Sample
Overdrive 9
Standard 15
Read Data Value tMSR Standard, Long Line mode 24 μs
Overdrive 3
Standard 10
Recovery Time tREC0 Standard, Long Line mode 20 μs
Overdrive 4
Standard 480
Reset Time High tRSTH μs
Overdrive 58
Standard 600
Reset Time Low tRSTL μs
Overdrive 70
Standard 70
Time Slot tSLOT μs
Overdrive 12

START STOP START

START
REPEAT tBUS

SDA
tOF tR
tSU;STO
tSP
tSU;DAT tSU;STA tHIGH

SCL
tHD;STA
tHD;DAT
tLOW
tVD;ACK
tVD;DAT

Figure 1. I2C Timing Diagram

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

tCLK

tWCH tWCL

SDHC_CLK

tOVLD
tOHLD
SDHC_DATx,
SDHC_CMD NOT NOT
(OUTPUT) VALID VALID

tIHLD
tISU
SDHC_DATx,
SDHC_CMD NOT NOT
(INPUT) VALID VALID

Figure 2. SD/SDIO/SDHC/MMC Timing Diagram

SHIFT SAMPLE SHIFT SAMPLE

SSx
(SHOWN ACTIVE LOW)
tMCK
SCK
CKPOL/CKPHA
0/1 OR 1/0
SCK tMCH tMCL
CKPOL/CKPHA
0/0 OR 1/1
tMOH
tMOV tMLH
MOSI/SDIOx
(OUTPUT) MSB MSB-1 LSB

tMIS tMIH
MISO/SDIOx
(INPUT) MSB MSB-1 LSB

Figure 3. SPI Controller Mode Timing Diagram

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

SHIFT SAMPLE SHIFT SAMPLE

SSx tSSE
tSSH
(SHOWN ACTIVE LOW)
tSSD
SCK tSCK
CKPOL/CKPHA
0/1 OR 1/0
tSCH tSCL
SCK
CKPOL/CKPHA
0/0 OR 1/1

tSIS tSIH
MOSI/SDIOx
(INPUT) MSB MSB-1 LSB

tSOV tSLH
MISO/SDIOx MSB MSB-1 LSB
(OUTPUT)

Figure 4. SPI Target Mode Timing Diagram

tBCLKS
tWBCLKHS tWBCLKLS

BCLK

tLRCLK_BCLKS

LRCLK

tBCLK_SDOS
SD
LSB MSB LSB MSB
(OUTPUT)
tHD_SDIS
tSU_SDIS
SD
(INPUT) LSB MSB LSB MSB

WORD N-1 RIGHT CHANNEL WORD N LEFT CHANNEL WORD N RIGHT CHANNEL

CONDITIONS: I2S_CTRL0CH0.ws_pol = 0; I2S_CTRL0CH0.ch_mode = 3; I2S_CTRL0CH0.lsb_first = 0; I2S_CTRL0CH0.stereo = 0; I2S_CTRL1CH0.en = 1

Figure 5. I2S Target ModeTiming Diagram

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

tBCLKM
tWBCLKHM tWBCLKLM

BCLK

tBCLK_LRCLKM

LRCLK

tBCLK_SDOM
SD LSB MSB LSB MSB
(OUTPUT)
tHD_SDIM
tSU_SDIM

SD LSB MSB LSB MSB

(INPUT)

WORD N-1 RIGHT CHANNEL WORD N LEFT CHANNEL WORD N RIGHT CHANNEL

CONDITIONS: I2S_CTRL0CH0.ws_pol = 0; I2S_CTRL0CH0.ch_mode = 0; I2S_CTRL0CH0.lsb_first = 0; I2S_CTRL0CH0.stereo = 0; I2S_CTRL1CH0.en = 1

Figure 6. I2S Controller Timing Diagram

tCLK

tWCH tWCL

PCIF_PCLK
tSHLD
tSSU
PCIF_VSYNC,
PCIF_HSYNC
tDHLD
tDSU
PCIF_D0– NOT NOT
PCIF_D11 VALID VALID

Figure 7. Parallel Camera Interface Timing Diagram

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

INITIALIZATION RESET AND PRESENCE PULSE

tRSTH

OWM_IO

tRSTL tPDH tPDL

WRITE TIME SLOTS

WRITE 0 SLOT WRITE 1 SLOT
tSLOT tSLOT

tLOW0 tREC tLOW1

OWM_IO

READ TIME SLOTS

READ 0 SLOT READ 1 SLOT
tSLOT tSLOT

tLOW1 tREC tLOW1

OWM_IO

tRDV tRDV

LEGEND
BOTH CONTROLLER TARGET DEVICE RESISTOR
1-Wire CONTROLLER
AND TARGET ACTIVE LOW PULL-UP
ACTIVE LOW
DEVICE ACTIVE LOW

Figure 8. 1-Wire Controller Data Timing Diagram

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Pin Configuration
144 CSBGA

TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13

A P0.21 VSS HFXIN VREF VSS CSI_CKN CSI_D1N VCOREA 32KIN VBAT VREGO_C LXB VSSPWR A

B P0.22 P0.5 HFXOUT VSSA VSS CSI_CKP CSI_D1P VCOREB 32KOUT VDDA VREGO_A VBST LXA B

C P0.23 P0.6 P2.7 P2.3 VSS CSI_D0N CSI_D0P VCSI2P5 VSS RSTN VREGO_B VSSB VREGI C

D VDDIO P0.7 P2.6 P2.2 VSS P0.17 P0.16 P0.11 P0.10 P3.1 P3.0 VDDB DM D

E VDDIOH P0.8 P2.5 P2.1 P0.3 P0.2 VUSB0P9 DP E

F VSS P0.9 P2.4 P2.0 VSS VSS VSS VSS F

G VSS VSS VSS VSS MAX78002 P0.15 P0.14 VSS VSS G

H VCNN1 VCNN1 VCNN1 P0.4 P0.18 VCNN3 VCNN3 VCNN3 H

J VCNN1RAM VCNN1RAM P0.12 P0.20 P0.19 P1.15 VCNN3RAM VCNN3RAM J

K P0.24 P1.0 P0.13 P1.8 P0.30 P0.0 VSS P1.6 VCNN0_EN VCNN2RAM_EN P1.11 P1.13 P1.10 K

L P0.25 P1.1 P1.2 P1.9 P0.31 P0.1 VSS P1.7 VCNN0RAM_EN VCNN2_EN P1.12 P1.14 P1.17 L

M VCNN0RAM VCNN0RAM P1.3 P1.4 P0.26 VSS VSS P0.28 VCNN1_EN VCNN3RAM_EN P1.16 VCNN2RAM VCNN2RAM M

N VCNN0 VCNN0 VCNN0 P1.5 P0.27 VSS VSS P0.29 VCNN1RAM_EN VCNN3_EN VCNN2 VCNN2 VCNN2 N

1 2 3 4 5 6 7 8 9 10 11 12 13

144 CSBGA
12mm x 12mm

[Link] Analog Devices | 31

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Pin Description
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
POWER (See the Applications Information section for bypass capacitor recommendations.)
Battery Power Supply. Bypass device pin A10
with a 1μF capacitor placed as close as possible
A10 VBAT — — — to this pin and the VSSPWR pin. This pin must
be connected to VREGI and VDDIOH at the
circuit board level.
Battery Power Supply for the SIMO Switch-
Mode Power Supply (SMPS). Bypass this pin
with 2 x 47μF capacitors placed as close as
C13 VREGI — — — possible to this pin and the VSSPWR pin. This
pin must be connected to VBAT and VDDIOH. If
the power to the device is cycled, the voltage
applied to this pin must reach VREGI_POR.
1.8V Analog Power Supply. Bypass this pin with
a 1μF capacitor placed as close as possible to
B10 VDDA — — —
this pin and VSSA. This device pin must be
connected to VDDIO.
USB Transceiver Supply Voltage. Bypass this
D12 VDDB — — — pin to VSSB with a 1.0μF capacitor as close as
possible to the package.
ADC External Reference Input. Bypass this pin
with a 1μF capacitor placed as close as possible
to this pin and VSSA as possible. This is the
A4 VREF — — — reference input for the analog-to-digital
converter (ADC). If the external reference is not
used, tie this pin to VSSA through a 500Ω
resistor.
Digital Core Supply Voltage A. Bypass this pin
A8 VCOREA — — — to VSS with a 1μF capacitor placed as close to
this pin as possible.
Digital Core Supply Voltage B. Bypass this pin
B8 VCOREB — — — to VSS with a 1μF capacitor placed as close to
this pin as possible.
Boosted Supply Voltage for the Gate Drive of
B12 VBST — — — High-Side Switches. Bypass VBST to LXB with a
3.3nF capacitor.
Buck Converter A Voltage Output. Bypass this
B11 VREGO_A — — — pin with a 22μF capacitor to VSS placed as
close as possible to this pin.
Buck Converter B Voltage Output. Bypass this
C11 VREGO_B — — — pin with a 22μF capacitor to VSS placed as
close as possible to this pin.
Buck Converter C Voltage Output. Bypass this
A11 VREGO_C — — — pin with a 22μF capacitor to VSS placed as
close as possible to this pin.
GPIO Supply Voltage. Bypass this pin to VSS
D1 VDDIO — — — with a 1.0μF capacitor placed as close as
possible to the package.

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

144 CSBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
GPIO Supply Voltage, High. VDDIOH ≥ VDDIO.
Bypass this pin to VSS with a 1.0μF capacitor
E1 VDDIOH — — — placed as close as possible to the package. This
device pin must be connected to VREGI and
VBAT.
Bypass with 1μF capacitor to VSSB. Do not
E12 VUSB0P9 — — — connect this device pin to any other external
circuitry.
Bypass with 1μF capacitor to VSS. Do not
C8 VCSI2P5 — — — connect this device pin to any other external
circuitry.
F1, G1,
A2, G2,
G3, G4,
A5, B5,
C5, D5,
M6, N6,
K7, L7,
M7, N7, VSS — — — Digital Ground.
C9,
F10,
F11,
F12,
G12,
F13,
G13
Analog Ground. This pin is the return path for
B4 VSSA — — —
VREF and VDDA.
Ground for the SIMO Switch-Mode Power
A13 VSSPWR — — — Supply (SMPS). This device pin is the return
path for the VREG.
C12 VSSB — — — USB Transceiver Ground.
Switching Inductor Input A. Connect a 2.2μH
B13 LXA — — —
inductor between LXA and LXB.
Switching Inductor Input B. Connect a 2.2μH
A12 LXB — — —
inductor between LXA and LXB.
Voltage Supply for CNN x16 Processor
Quadrant 0. Bypass this pin with 3 x 1μF
N1, N2,
VCNN0 — — — capacitors as close to this pin as possible and a
N3
22μF capacitor as close as possible to the
package.
Voltage Supply for CNN x16 Processor
Quadrant 1. Bypass this pin with 3 x 1μF
H1, H2,
VCNN1 — — — capacitors as close to this pin as possible and a
H3
22μF capacitor as close as possible to the
package.

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

144 CSBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
Voltage Supply for CNN x16 Processor
N11, Quadrant 2. Bypass this pin with 3 x 1μF
N12, VCNN2 — — — capacitors as close to this pin as possible and a
N13 22μF capacitor as close as possible to the
package.
Voltage Supply for CNN x16 Processor
H11, Quadrant 3. Bypass this pin with 3 x 1μF
H12, VCNN3 — — — capacitors as close to this pin as possible and a
H13 22μF capacitor as close as possible to the
package.
Voltage Supply for the RAM for the CNN x16
Processor Quadrant 0. Bypass this pin with 2 x
M1, M2 VCNN0RAM — — — 1μF capacitors as close to this pin as possible
and a 22μF capacitor as close as possible to the
package.
Voltage Supply for the RAM for the CNN x16
Processor Quadrant 1. Bypass this pin with 2 x
J1, J2 VCNN1RAM — — — 1μF capacitors as close to this pin as possible
and a 22μF capacitor as close as possible to the
package.
Voltage Supply for the RAM for the CNN x16
Processor Quadrant 2. Bypass this pin with 2 x
M12,
VCNN2RAM — — — 1μF capacitors as close to this pin as possible
M13
and a 22μF capacitor as close as possible to the
package.
Voltage Supply for the RAM for the CNN x16
Processor Quadrant 3. Bypass this pin with 2 x
J12,
VCNN3RAM — — — 1μF capacitors as close to this pin as possible
J13
and a 22μF capacitor as close as possible to the
package.
Enable Output for the Voltage Supply for CNN
K9 VCNN0_EN — — —
x16 Processor Quadrant 0.
Enable Output for the Voltage Supply for CNN
M9 VCNN1_EN — — —
x16 Processor Quadrant 1.
Enable Output for the Voltage Supply for CNN
L10 VCNN2_EN — — —
x16 Processor Quadrant 2.
Enable Output for the Voltage Supply for CNN
N10 VCNN3_EN — — —
x16 Processor Quadrant 3.
VCNN0RAM_E Enable Output for the Voltage Supply for the
L9 — — —
N RAM for the CNN x16 Processor Quadrant 0.
VCNN1RAM_E Enable Output for the Voltage Supply for the
N9 — — —
N RAM for the CNN x16 Processor Quadrant 1.
VCNN2RAM_E Enable Output for the Voltage Supply for the
K10 — — —
N RAM for the CNN x16 Processor Quadrant 2.
VCNN3RAM_E Enable Output for the Voltage Supply for the
M10 — — —
N RAM for the CNN x16 Processor Quadrant 3.

[Link] Analog Devices | 34

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

144 CSBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
RESET AND CONTROL
Active-Low, External System Reset Input. The
device remains in reset while this pin is in its
active state. When the pin transitions to its
C10 RSTN — — — inactive state, the device performs a POR reset
(resetting all logic on all supplies except for RTC
circuitry) and begins execution. This pin has an
internal pull-up to the VDDIOH supply.
CLOCK
B9 32KOUT — — — 32kHz Crystal Oscillator Output.
32kHz Crystal Oscillator Input. Connect a 32kHz
crystal between 32KIN and 32KOUT for RTC
A9 32KIN — — — operation. Optionally, this pin can be configured
as the input for an external CMOS-level clock
source.
25MHz Crystal Oscillator Input. Connect a
25MHz crystal between HFXIN and HFXOUT.
A3 HFXIN — — —
Optionally, this pin can be configured as the
input for an external CMOS-level clock source.
B3 HFXOUT — — — 25MHz Crystal Oscillator Output.
GPIO AND ALTERNATE FUNCTION (See the Applications Information section for GPIO and Alternate Function Matrices.)
UART0 Receive Port Map A. See Bootloader
K6 P0.0 P0.0 UART0A_RX — Activation for details on this pin's usage and
suggested pull-up.
L6 P0.1 P0.1 UART0A_TX — UART0 Transmit Port Map A.
Timer0 I/O 32 Bits or Lower 16 Bits Port Map A;
E11 P0.2 P0.2 TMR0A__IOA UART0B_CTS
UART0 Clear to Send Port Map B.
External Clock for Use as SYS_OSC/Timer0 I/O
E10 P0.3 P0.3/EXT_CLK TMR0A_IOB UART0B_RTS Upper 16 Bits Port Map A; UART0 Request to
Send Port Map B.
SPI0 Port Map A Target Select 0; Timer0
H4 P0.4 P0.4 SPI0A_SS0 TMR0B_IOAN
Inverted Output Port Map B.
SPI0 Port Map A Controller-Out Target-In Serial
B2 P0.5 P0.5 SPI0A_MOSI TMR0B_IOBN Data 0; Timer0 Inverted Output Upper 16 Bits
Port Map B.
SPI0 Port Map A Controller-In Target-Out Serial
C2 P0.6 P0.6 SPI0A_MISO OWM_IO
Data 1; 1-Wire Controller Data I/O.
SPI0 Port Map A Clock; 1-Wire Controller Pull-
D2 P0.7 P0.7 SPI0A_SCK OWM_PE
up Enable Output.
SPI0 Port Map A Data 2 I/O; Timer0 I/O 32 Bits
E2 P0.8 P0.8 SPI0A_SDIO2 TMR0B_IOA
or Lower 16 Bits Port Map B.
SPI0 Port Map A Data 3 I/O; Timer0 I/O Upper
F2 P0.9 P0.9 SPI0A_SDIO3 TMR0B_IOB
16 Bits Port Map B.
D9 P0.10 P0.10 I2C0A_SCL SPI0_SS2 I2C0 Port Map A Clock; SPI0 Target Select 2.
I2C0 Port Map A Serial Data; SPI0 Target
D8 P0.11 P0.11 I2C0A_SDA SPI0_SS1
Select 1.

[Link] Analog Devices | 35

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

144 CSBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
UART1 Receive Port Map A; Timer1 Inverted
J3 P0.12 P0.12 UART1A_RX TMR1B_IOAN
Output Port Map B.
UART1 Transmit Port Map A; Timer1 Inverted
K3 P0.13 P0.13 UART1A_TX TMR1B_IOBN
Output Upper 16 Bits Port Map B.
Timer1 I/O 32 Bits or Lower 16 Bits Port Map A;
G11 P0.14 P0.14 TMR1A_IOA I2S_CLKEXT
I2S External Clock Input.
Timer1 I/O Upper 16 Bits Port Map A; Parallel
G10 P0.15 P0.15 TMR1A_IOB PCIF_VSYNC
Camera Interface Vertical Sync.
D7 P0.16 P0.16 I2C1A_SCL PT2 I2C1 Port Map A Clock; Pulse Train 2.
D6 P0.17 P0.17 I2C1A_SDA PT3 I2C1 Port Map A Serial Data; Pulse Train 3.
H10 P0.18 P0.18 PT0 OWM_IO Pulse Train 0; 1-Wire Controller Data I/O.
Pulse Train 1; 1-Wire Controller Pull-up Enable
J10 P0.19 P0.19 PT1 OWM_PE
Output.
SPI1 Port Map A Target Select 0; Parallel
J4 P0.20 P0.20 SPI1A_SS0 PCIF_D0
Camera Interface Data 0.
SPI1 Port Map A Controller-Out Target-In Serial
A1 P0.21 P0.21 SPI1A_MOSI PCIF_D1
Data 0; Parallel Camera Interface Data 1.
SPI1 Port Map A Controller-In Target-Out Serial
B1 P0.22 P0.22 SPI1A_MISO PCIF_D2
Data 1; Parallel Camera Interface Data 2.
SPI1 Port Map A Clock; Parallel Camera
C1 P0.23 P0.23 SPI1A_SCK PCIF_D3
Interface Data 3.
SPI1 Port Map A Data 2; Parallel Camera
K1 P0.24 P0.24 SPI1A_SDIO2 PCIF_D4
Interface Data 4.
SPI1 Port Map A Data 3; Parallel Camera
L1 P0.25 P0.25 SPI1A_SDIO3 PCIF_D5
Interface Data 5.
Timer2 I/O 32 Bits or Lower 16 Bits Port Map A;
M5 P0.26 P0.26 TMR2A_IOA PCIF_D6
Parallel Camera Interface Data 6.
P0.27/ USB External Clock/Timer2 I/O Upper 16 Bits
N5 P0.27 TMR2A_IOB PCIF_D7
USB_EXTCLK Port Map A; Parallel Camera Interface Data 7.
Serial Wire Debug Data I/O. Following any
M8 P0.28 P0.28/SWDIO — —
reset, this device pin defaults to AF1 SWDIO.
Serial Wire Debug Clock. Following any reset,
this device pin defaults to AF1 SWDCLK. See
N8 P0.29 P0.29/SWDCLK — —
Bootloader Activation for details on this pin's
usage and suggested pullup.
I2C2 Port Map A Clock; Parallel Camera
K5 P0.30 P0.30 I2C2A_SCL PCIF_D8
Interface Data 8.
I2C2 Port Map A Serial Data; Parallel Camera
L5 P0.31 P0.31 I2C2A_SDA PCIF_D9
Interface Data 9.
UART2 Receive Port Map A; 32-bit RISC-V Test
K2 P1.0 P1.0 UART2A_RX RV_TCK
Port Clock.
UART2 Transmit Port Map A; 32-bit RISC-V
L2 P1.1 P1.1 UART2A_TX RV_TMS
Test Port Select.
I2S0 Port Map A Bit Clock; 32-bit RISC-V Test
L3 P1.2 P1.2 I2S0A_SCK RV_TDI
Port Data Input.

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

144 CSBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
I2S0 Port Map A Left/Right Clock; 32-bit RISC-V
M3 P1.3 P1.3 I2S0A_WS RV_TDO
Test Port Data Output.
I2S0 Port Map A Serial Data Input; Timer3 I/O
M4 P1.4 P1.4 I2S0A_SDI TMR3B_IOA
32 Bits or Lower 16 Bits Port Map B.
I2S0 Port Map A Serial Data Output; Timer3 I/O
N4 P1.5 P1.5 I2S0A_SDO TMR3B_IOB
Upper 16 Bits Port Map B.
Timer3 I/O 32 Bits or Lower 16 Bits Port Map A;
K8 P1.6 P1.6 TMR3A_IOA PCIF_D10
Parallel Camera Interface Data 10.
Timer3 I/O Upper 16 Bits Port Map A; Parallel
L8 P1.7 P1.7 TMR3A_IOB PCIF_D11
Camera Interface Data 11.
Parallel Camera Interface Horizontal Sync; CM4
K4 P1.8 P1.8 PCIF_HSYNC RXEV0
Rx Event Input.
Parallel Camera Interface Pixel Clock; CM4 Tx
L4 P1.9 P1.9 PCIF_PCLK TXEV0
Event Output.
Secure Digital Interface Card Present; ADC
K13 P1.10 P1.10 SDHC_CDN ADC_CLK_EXT
External Clock Input.
K11 P1.11 P1.11 SDHC_DAT3 — Secure Digital Interface Data Bus Bit 3.
ADC_HW_TRIG Secure Digital Interface Data Bus Bit 2; ADC
L11 P1.12 P1.12 SDHC_DAT2
_A Trigger Input A.
ADC_HW_TRIG Secure Digital Interface Data Bus Bit 1; ADC
K12 P1.13 P1.13 SDHC_DAT1
_B Trigger Input B.
ADC_HW_TRIG Secure Digital Interface Data Bus Bit 0; ADC
L12 P1.14 P1.14 SDHC_DAT0
_C Trigger Input C.
J11 P1.15 P1.15 SDHC_WP — Secure Digital Interface Write Protect.
M11 P1.16 P1.16 SDHC_CMD — Secure Digital Interface Bus Command.
L13 P1.17 P1.17 SDHC_CLK — Secure Digital Interface Clock.
F4 P2.0 P2.0 AIN0/AIN0N — ADC Input 0/Comparator 0 Negative Input.
E4 P2.1 P2.1 AIN1/AIN0P — ADC Input 1/Comparator 0 Positive Input.
D4 P2.2 P2.2 AIN2/AIN1N — ADC Input 2/Comparator 1 Negative Input.
C4 P2.3 P2.3 AIN3/AIN1P — ADC Input 3/Comparator 1 Positive Input.
ADC Input 4/Comparator 2 Negative Input; Low-
F3 P2.4 P2.4 AIN4/AIN2N LPTMR0B_IOA
Power Timer0 I/O Port Map B.
ADC Input 5/Comparator 2 Positive Input; Low-
E3 P2.5 P2.5 AIN5/AIN2P LPTMR1B_IOA
Power Timer1 I/O Port Map B.
Low-Power Timer0 External Clock Input/ADC
P2.6/
D3 P2.6 AIN6/AIN3N LPUARTB_RX Input 6/Comparator 3 Negative Input; Low-
LPTMR0_CLK
Power UART0 Receive Port Map B.
Low-Power Timer1 External Clock Input/ADC
P2.7/
C3 P2.7 AIN7/AIN3P LPUARTB_TX Input 7/Comparator 3 Positive Input; Low-Power
LPTMR1_CLK
UART Transmit Port Map B.
P3.0/PDOWN/ Power-Down Output; Wakeup Input. This device
D11 P3.0 — —
WAKEUP pin can only be powered by VDDIOH.
P3.1/SQWOUT/ RTC Square-Wave Output; Wakeup Input. This
D10 P3.1 — —
WAKEUP device pin can only be powered by VDDIOH.

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

144 CSBGA
FUNCTION MODE
PIN NAME Primary Signal Alternate Alternate FUNCTION
(Default) Function 1 Function 2
USB
USB DP Signal. This bidirectional pin carries the
positive differential data or single-ended data.
E13 DP — — —
This pin is weakly pulled high internally when
the USB is disabled.
USB DM Signal. This bidirectional pin carries
the negative differential data or single-ended
D13 DM — — —
data. This pin is weakly pulled high internally
when the USB is disabled.
MIPI CSI-2
MIPI CSI-2 receiver differential clock positive
B6 CSI_CKP — — —
input.
MIPI CSI-2 receiver differential clock negative
A6 CSI_CKN — — —
input.
MIPI CSI-2 receiver differential data lane 0
C7 CSI_D0P — — —
positive input.
MIPI CSI-2 receiver differential data lane 0
C6 CSI_D0N — — —
negative input.
MIPI CSI-2 receiver differential data lane 1
B7 CSI_D1P — — —
positive input.
MIPI CSI-2 receiver differential data lane 1
A7 CSI_D1N — — —
negative input.

[Link] Analog Devices | 38

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Detailed Description
Artificial intelligence (AI) requires extreme computational horsepower, but Analog Devices is cutting the power cord from
AI insights. The MAX78002 is a new breed of AI microcontroller built to enable neural networks to execute at ultra-low
power and live at the edge of the IoT. This product combines the most energy-efficient AI processing with Analog Devices'
proven ultra-low-power microcontrollers. Our hardware-based convolutional neural network (CNN) accelerator enables
battery-powered applications to execute AI inferences while spending only microjoules of energy.
The MAX78002 is an advanced system-on-chip featuring an Arm Cortex-M4 with FPU CPU for efficient system control
with an ultra-low-power deep neural network accelerator. The CNN engine has a weight storage memory of 2MB, and
can support 1-, 2-, 4-, and 8-bit weights (supporting networks of up to 16 million weights). The CNN weight memory is
SRAM-based so that AI network updates can be made on the fly. The CNN engine also has 1.3MB of data memory. The
CNN architecture is highly flexible, allowing networks to be trained in conventional toolsets like PyTorch and TensorFlow,
then converted for execution on the MAX78002 using tools provided by Analog Devices.
In addition to the memory in the CNN engine, the MAX78002 has large on-chip system memory for the microcontroller
core, with 2.5MB flash and up to 384KB SRAM. Multiple high-speed and low-power communications interfaces are
supported, including I2S, MIPI CSI-2 serial camera, parallel camera (PCIF), and SD 3.0/SDIO 3.0/eMMC 4.51 secure
digital.

Arm Cortex-M4 with FPU Processor and RISC-V RV32 Processor

The Arm Cortex-M4 with FPU processor (CM4) is ideal for AI system control. The architecture combines high-efficiency
signal processing functionality with low power, low cost, and ease of use.
The Arm Cortex-M4 with FPU DSP supports single instruction, multiple data (SIMD) path DSP extensions, providing:
● Four parallel 8-bit add/sub
● Floating point single precision
● Two parallel 16-bit add/sub
● Two parallel MACs
● 32- or 64-bit accumulate
● Signed or unsigned data with or without saturation
The addition of a 32-bit RISC-V coprocessor (RV32) provides the system with ultra-low power consumption signal
processing.

Convolutional Neural Network Accelerator (CNN)

The CNN accelerator consists of 64 parallel processors with 1.31MB of SRAM-based storage. Each processor includes a
pooling unit and a convolutional engine with dedicated weight memory. Four processors share one data memory. These
are further organized into groups of 16 processors that share common controls. A group of 16 processors operates as
a peripheral to another group or independently. Data is read from SRAM associated with each processor and written to
any data memory located within the accelerator. Any given processor has visibility of its dedicated weight memory and
the data memory instance it shares with the three others.
The features of the CNN accelerator include:
● Data storage
• 1.31MB SRAM-based data storage
• Configured as 20Kx8-bit integers x64 channels or 80Kx8-bit integers x4 channels for input layers
• Input data format – 8-bit signed values
• Selectable output data format – 8-bit signed integer or 32-bit signed integer for last layer
• Arm AMBA APB accessible
• Hardware CNN results data unload assist
● Weight storage
• SRAM based with selectable data retention mode
• Configurable from 2M 8-bit integer weights to 16M 1-bit logical weights

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
• Optional 4x processing mode splits each weight memory into four parallel memories with a common address
generating 4x the number of masks each cycle
• All processors include the following dedicated weight storage:
• 1x processing mode
• 4096x9x8-bit weights
• 8192x9x4-bit weights
• 16384x9x2-bit weights
• 32768x9x1-bit weights
• 4x processing mode
• 4x1024x9x8-bit weights
• 4x2048x9x4-bit weights
• 4x4096x9x2-bit weights
• 4x8192x9x1-bit weights
• The first processor in each x16 includes additional weight storage for input layer processing:
• 1x processing mode
• 1024x9x8-bit weights
• 2048x9x4-bit weights
• 4096x9x2-bit weights
• 8196x9x1-bit weights
• 4x processing mode
• 4x256x9x8-bit weights
• 4x512x9x4-bit weights
• 4x1024x9x2-bit weights
• 4x2048x9x1-bit weights
• Programmable per x16 processor weight RAM start address, start pointer, and mask count
• Arm AMBA APB accessible
• Optional weight load hardware assist for packed weight storage
● 128 independently configurable layers (per x16 processor)
• Programmable start layer – any of the 128 layers
• Linked layer mode allows arbitrary nonsequential layer execution
• Configurable per layer parameters
• Processor and mask enables (16 channels)
• Input data format – byte-wide input data or 4x8-bit wide input data (x16 processors 0, 4, 8, or 12 only)
• Per layer data streaming
• Up to eight simultaneous streaming layers – available for the first eight layers
• Optional FIFO input data paths (first layer only)
• Selectable streaming termination layer – transition to nonstream processing mode
• Programmable per stream configuration
• Stream start – relative to prior stream
• Three stream processing delay counters – two column counters for noninteger ratios, 1-row delta counter
• Data SRAM circular buffer size
• Programmable input data size (separate row, column fields)
• Programmable row and column padding – 0 to 3 bytes
• Configurable number of input channels – 1 to 1024
• Configurable number of output channels – 1 to 1024 (determined by the kernel count value)
• Selectable kernel bit width size (1, 2, 4, or 8)
• Selectable kernel SRAM pointer start address and count
• Optional in-flight input image pooling
• Pool mode – none, maximum, or average
• Pool size – 2x2 to 16x16 with independent row and column counts
• Pool dilation – 0 to 15
• Programmable stride – 1 to 4 common row/column stride value
• Data SRAM read pointer base address
• Configurable read pointer increment value for flexible input channel access

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
• Data SRAM write pointer configuration
• Base address
• Independent offsets for output channel storage in SRAM
• Programmable stride increment offset
• Bias – 8192 8-bit integers with an option for 1024 10-bit integers using multiple x16 processors
• Optionally configurable as 4x2048x8-bit bias for 4x mode (with an option for 10-bit bias using multiple x16
processors)
• Pre-activation output scaling – direction (up/down) and 0 to 15-bit shift magnitude
• Output activation – none, ReLU, absolute value
• Pass-through mode allows input data to be passed directly through to the output with programmable data
relocation.
• Element-wise operations (add, subtract, XOR, OR) with optional convolution – up to 16 elements
• Deconvolution
• Flattening - for MLP processing
• Depthwise convolution
• Simple logic modes support single mask bit +1/-1, 0/-1 modes
• No mask mode supports convolutions with a fixed mask value of 1
● Processing
• 64 parallel physical channel processors
• Organized as 4 x 16 processors
• 8-bit integer data path with an option for 32-bit integers on the output layer
• Per channel processor enable/disable
• Expandable to 1024 parallel logical channel processors
• Configurable 3x3 or 1x1 2D kernel size
• Configurable 1D kernel size to 1x9
• Full-resolution sum-of-products arithmetic for 1024 8-bit integer (data and weight) channels
• Two maximum operating frequency modes – up to 50MHz in nonpipelined mode or up to 200MHz in pipeline mode
• Up to 16 output channels per clock processing rate
• Conditional execution allows early layer termination and branching based on the programmable address and/or
data and/or count match
● Input layer maximum input size
• 20KB, 64 channels, non-streaming, APB I/F
• 80KB, 16 channels, non-streaming, APB I/F
• 80KB, 4 channels, non-streaming, FIFO I/F
• 2048x2048 bytes, 4 channels, streaming, FIFO I/F
● Hidden layers maximum input size
• Up to 20KB per channel, x64 channels, nonstreaming
• 20KB can be split equally across 1 to 16 logical channels, nonstreaming
• 4MB per channel, x64 channels, streaming
• 4MB can be split equally across eight layers, streaming
● Optional interrupt on CNN completion and FIFO full and empty statuses
● User accessible BIST on all internal memories
● User accessible zeroization of all internal memories
● Single-step operation with full data SRAM access for CNN operation debug
● Power management
• Independent x16 processor supply enables
• Independent x16 processor mask retention enables
• Independent x16 data path clock enables
• Functional APB clock gating with per x16 processor override – registers clocked only during APB write access.
• CNN clock frequency scaling (divide by 2, 4, 8, or 16)
• Chip-level voltage control for power-performance optimization
● Input data row buffer memory (TRAM)

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
• Organized as 12Kx16 or optionally as 4x3Kx16 in read-ahead mode
• Programmable per layer TRAM read/write pointer start and rollover values
• Automatically allocates memory based on the programmed number of input channels
● Read ahead input processing mode allows the next input data byte to be preprocessed while the current input byte
output channel generation is active.

Memory
Internal Flash Memory
2.5MB of internal flash memory provides nonvolatile storage of program and data memory.

Internal SRAM
The internal 384KB SRAM provides low-power retention of application information in all power modes except POWER
DOWN. The SRAM is divided into eight banks. SRAM0 and SRAM1 are both 32KB; SRAM2, SRAM3, SRAM4, and
SRAM5 are all 64KB each. SRAM6 is 48KB, and SRAM7 is 16KB. SRAM4, SRAM5, SRAM6, and SRAM7 are accessible
by the RV32 in LOW POWER mode. For enhanced system reliability, SRAM0 (32KB) can be configured with error
correction coded (ECC) single error correction-double error detection (SEC-DED). This data retention feature is optional
and configurable. This granularity allows the application to minimize its power consumption by only retaining the most
essential data.

Dynamic Voltage Scaling (DVS) Controller

The DVS controller works using the fixed high-speed oscillator and the VCOREA supply voltage to optimally operate the
Arm core at the lowest practical voltage. The ability to adaptively adjust the voltage provides a significant reduction in
dynamic power consumption.
The DVS controller provides the following features:
● Controls DVS monitoring and adjustment functions
● Continuous monitoring with programmable monitor sample period
● Controlled transition to a programmable operating point
● Independent high and low operating limits for safe, bounded operation
● Independent high, center, and low operating range delay line delay monitors
● Programmable adjustment rate – when an adjustment is required
● Single clock operation
● Arm peripheral bus interface provides control and status access
● Interrupt capability during error

Clocking Scheme
Multiple clock sources can be selected as the system clock:
● Internal phase-locked loop (IPLL) provides 100MHz and 200MHz clock sources
● Internal primary oscillator (IPO) at a nominal frequency of 120MHz
● Internal secondary oscillator (ISO) at a nominal frequency of 60MHz
● Configurable internal nanoring oscillator (INRO) at 8kHz, 16kHz, or 30kHz
● External RTC oscillator at 32.768kHz (ERTCO) (external crystal required)
● Internal baud rate oscillator at 7.3728MHz (IBRO)
● External square-wave clock up to 80MHz
There are multiple external clock inputs:
● LPTMR0 and LPTMR1 can be clocked from unique external sources.
● I2S can be be clocked from its own external source.
● USB can be clocked from its own external source.

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
RTC/CALIBRATION
OUTPUT
SQWOUT
(P3.1)

XTAL DRIVER OR 32KIN BYPASS

32KIN RTC_OSCCTRL.bypass
EXTERNAL CLOCK
32.768kHz 32.768kHz 32.768kHz
32.768kHz
CRYSTAL 1Hz 512Hz 4096Hz 32768Hz
OSC
POWER-DOWN MODE
REAL-TIME CLOCK
32KOUT CONTROLLER
MICROPOWER DOMAIN PERIPHERALS
POWER
LPUART0 MANAGEMENT UNIT
LPTMR0 LPTMR1 LPWDT0
2-WIRE
NANORING (INRO)
8kHz, 16kHz, 30kHz
LPTMR0_CLK (P2.6)
÷8

LPTMR1_CLK (P2.7)
LEGEND
AUTO-CAL
GCR_CLKCN.clksel X = UNCONNECTED CLOCK INPUT

= DEVICE PIN
120MHz
Arm Cortex
120MHz 4-CH
M4 SPI0
(CM4) DMA
INTERNAL PRIMARY 32.768kHz
OSCILLATOR (IPO)

7.3728MHz SYS_CLK ÷2
GCR_CLKCN.psc APB CLK
7.3728MHz

INTERNAL BAUD RATE

SYS_OSC
OSCILLATOR (IBRO) PRESCALER

60MHz

INTERNAL SECONDARY
OSCILLATOR (ISO)

PWRSEQ_LPCN. GCR_PCKDIV.cnnclksel
100MHz
RISC-V lpmclksel
(RV32)
CNN 12-BIT SAR ADC
GCR_PCKDIV.cnnfrq
INTERNAL PHASE 200MHz PRESCALER
LOCKED LOOP (IPLL) ADC
XTAL DRIVER OR AES/
EXTERNAL CLOCK CRC/ SAR_CLKCTRL.clkdiv
TRNG CNN CLOCK
25MHz QUADRANTS SCALER
25MHz
CRYSTAL OSC CNN
MEMORY SAR_CLKCTRL.clksel

(P1.10) ADC_EXT_CLK
EXT_CLK (P0.3)

(P0.3) USB_EXTCLK
I2S_CLKEXT (P0.14)
GCR_PCKDIV
.sdhcfrq ÷2, 4
÷4, 8

SD/ CTRL PHY

TMR0,TMR1 UART0 UART1 UART2 4 x PULSE 3x MIPI
I 2S SPI1 WDT0 1-Wire PCIF SDIO/
TMR2,TMR3 4-WIRE 2-WIRE 2-WIRE TRAINS I 2C CSI-2 HI-SPEED USB 2.0
MMC

Figure 9. Clocking Scheme

General-Purpose I/O (GPIO) and Special Function Pins

Most GPIO pins share both a firmware-controlled I/O function and one or more alternate functions associated with
peripheral modules. Pins can be individually enabled for GPIO or peripheral special function use. Configuring a pin as a
special function usually supersedes its use as a firmware-controlled I/O. Although this multiplexing between peripheral
and GPIO functions is usually static, it can also be done dynamically. The electrical characteristics of a GPIO pin are
identical whether the pin is configured as an I/O or special function, except where explicitly noted in the Electrical
Characteristics tables.
In GPIO mode, pins are logically divided into ports of 32 pins. Each pin of a port has an interrupt function that can be

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
independently enabled, and configured as a level- or edge-sensitive interrupt. All GPIOs of a given port share the same
interrupt vector.
When configured as GPIO, the following features are provided. The features can be independently enabled or disabled
on a per-pin basis.
● Configurable as input, output, bidirectional, or high impedance
● Optional internal pull-up resistor or internal pull-down resistor when configured as input
● Exit from low-power modes on rising or falling edge
● Selectable standard- or high-drive modes
The MAX78002 provides up to 60 GPIO pins. Caution is needed since Port 3 (P3.0 and P3.1 device pins) are configured
in a different manner from the above description. Refer to the MAX78002 User Guide for details.

MIPI Camera Serial Interface 2 (MIPI CSI-2) Controller

The MIPI CSI-2 is a low voltage interface suited for CMOS image sensors with the following features:
● D-PHY 2.1
● MIPI Alliance Standard for Camera Serial Interface 2 Version 2.1 compliant
● Implements all three CSI-2 MIPI Layers (Pixel to Byte packing, Low-Level Protocol, Lane Management)
● Receiver only
● Two data lanes, one clock lane
● Supports high speed (4.5+ Gbps) D-PHY operation
● Support for all CSI-2 data types
● Error correction support

Parallel Camera Interface (PCIF)

The PCIF is a low-voltage interface suited for CMOS image sensors. It provides up to 12-bits of parallel access capability
with single capture and continuous mode operation.

Analog-to-Digital Converter (ADC)

The 12-bit successive approximation register (SAR) ADC provides an external reference input and a single-ended input
multiplexer. The multiplexer selects an input channel from one of the eight external analog input signals (AIN0–AIN7) or
the internal power supply inputs.
The reference for the ADC can be:
● External VREF input
● Internal 1.25V or 2.048V selectable
An optional feature allows samples captured by the ADC to be automatically compared against user-programmable high
and low limits. Up to four channel limit pairs can be configured in this way. The comparison allows the ADC to trigger an
interrupt (and potentially wake the CPU from a power mode) when a captured sample goes outside the preprogrammed
limit range. Since this comparison is performed directly by the sample limit monitors, it can be performed even while the
CPU is in SLEEP, LOW POWER, or MICRO POWER mode. The eight AIN[7:0] inputs can be configured as four pairs
and deployed as four independent comparators.
The ADC measures the following voltages:
● AIN[7:0] up to 3.3V
● VBAT
● VSS
● VCOREA
● VCOREB
● 2.5V internal LDO
● 0.9V internal LDO
● VDDB
● VDDA
● Internal die temperature sensor output

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MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
Comparators
The eight AIN[7:0] inputs can be configured as four pairs and deployed as four independent comparators with the
following features:
● Comparison events can trigger interrupts
● Events can wake the CM4 from SLEEP, LOW POWER, MICRO POWER, STANDBY, or BACKUP operating modes
● Can be active in all power modes

Single-Inductor Multiple-Output Switch-Mode Power Supply (SIMO SMPS)

The SIMO SMPS built into the device provides a monolithic power supply architecture for operation from a single lithium
cell. The SIMO provides three buck regulator outputs that are voltage programmable. This architecture optimizes power
consumption efficiency of the device and minimizes the bill of materials for the circuit design since only a single inductor/
capacitor pair is required.

Power Management
Power Management Unit
The power management unit (PMU) provides high-performance operation while minimizing power consumption. It
exercises intelligent, precise control of power distribution to the CPUs and peripheral circuitry.
The PMU provides the following features:
● User-configurable system clock
● Automatic enabling and disabling of crystal oscillators based on power mode
● Multiple power domains
● Fast wake-up of powered-down peripherals when activity detected
● Optional control of external switches to provide the CNN with dedicated power from an external source

ACTIVE Mode
In this mode, the CM4 and the RV32 can execute application code and all digital and analog peripherals are available
on demand. Dynamic clocking disables peripherals not in use, providing the optimal mix of high performance and low
power consumption. The CM4 has access to all system SRAM. The RV32 has access to SRAM4, SRAM5, SRAM6, and
SRAM7. Both the CM4 and the RV32 can execute from internal flash simultaneously. SRAM7 can be configured as an
instruction cache for the RV32.

SLEEP Mode
This mode consumes less power, but wakes faster because the clocks can optionally be enabled.
The device status is as follows:
● CM4 is asleep.
● RV32 is asleep.
● CNN quadrants and memory are configurable.
● Peripherals are on.
● Standard DMA is available for optional use.

LOW POWER Mode (LPM)

This mode is suitable for running the RV32 processor to collect and move data from enabled peripherals.
The device status is as follows:
● The CM4, SRAM0, SRAM1, SRAM2, and SRAM3 are in state retention.
● CNN quadrants and memory are configurable and active.
● The RV32 can access the SPI, all UARTS, all timers, I2C, 1-Wire, pulse train engines, I2S, CRC, AES, TRNG, PCIF,
and comparators, as well as SRAM4, SRAM5, SRAM6, and SRAM7. SRAM7 can be configured to operate as RV32
instruction cache.
● The transition from LOW POWER mode to ACTIVE mode is faster than the transition from BACKUP mode because
system initialization is not required.

MICRO POWER Mode (μPM)

This mode is used for extremely low power consumption while using a minimal set of peripherals to provide wakeup
capability.
The device status is as follows:
● Both CM4 and RV32 are state retained. System state and all SRAM is retained.
● CNN quadrants are powered off.
● CNN memory provides selectable retention.
● The GPIO pins retain their state.
● All non-MICRO POWER peripherals are state retained.
● The following oscillators are powered down:
• IPO
• IPLL
• ISO
● The following oscillators are enabled:
• IBRO
• ERTCO
• INRO
● The following MICRO POWER mode peripherals are available to wake up the device:
• LPUART0
• WWDT1
• All four low-power analog comparators

STANDBY Mode
This mode is used to maintain the system operation while keeping time with the RTC.
The device status is as follows:
● Both CM4 and RV32 are state retained. System state and all SRAM are retained.
● CNN quadrants are powered off.
● CNN memory provides selectable retention.
● GPIO pins retain their state.
● All peripherals are state retained.
● The following oscillators are powered down:
• IPO
• IPLL
• ISO
• IBRO
● The following oscillators are enabled:
• ERTCO
• INRO

BACKUP Mode
This mode is used to maintain the system RAM. The device status is as follows:
● CM4 and RV32 are powered off.

[Link] Analog Devices | 46

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
● SRAM0 thru SRAM7 can be configured to be state retained as per Table 1.
● CNN memory provides selectable retention.
● All peripherals are powered off.
The following oscillators are powered down:
● IPO
● IPLL
● ISO
● IBRO
The following oscillators are enabled:
● ERTCO
● INRO
Table 1. BACKUP Mode SRAM Retention Block Sizes
RAM BLOCK RAM SIZE
SRAM0 32KB + ECC
SRAM1 32KB
SRAM2 64KB
SRAM3 64KB
SRAM4 64KB
SRAM5 64KB
SRAM6 48KB
SRAM7 16KB

POWER DOWN Mode (PDM)

This mode is used during product level distribution and storage. The device status is as follows:
● CM4 and RV32 are powered off.
● All peripherals and SRAM are powered down.
● All oscillators are powered down.
● There is no data retention in this mode, but values in flash memory are preserved.
● Voltage monitors are operational.

Wakeup Sources
The sources of wakeup from the SLEEP, LOW POWER, MICRO POWER, STANDBY, BACKUP, and POWER DOWN
operating modes are summarized in Table 2.
Table 2. Wakeup Sources
OPERATING MODE WAKEUP SOURCE
SLEEP Any enabled peripheral with interrupt capability; RSTN
SPI0, I2S, I2C, UARTs, timers, watchdog timers, wakeup timer, all comparators, RTC, GPIOs, RSTN, and
LOW POWER (LPM)
RV32
MICRO POWER
All comparators, LPUART, LPTMR1, LPTIMER2, LPWDT0, RTC, wakeup timer, GPIOs, and RSTN
(μPM)
STANDBY RTC, wakeup timer, GPIOs, CMP0, and RSTN
BACKUP RTC, wakeup timer, GPIOs, CMP0, and RSTN
POWER DOWN
P3.0, P3.1, and RSTN
(PDM)

Real-Time Clock
An RTC keeps the time of day in absolute seconds. The 32-bit seconds register can count up to approximately 136 years

[Link] Analog Devices | 47

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
and be translated to calendar format by application software.
The RTC provides a time-of-day alarm that can be programmed to any future value between 1 second and 12 days.
When configured for long intervals, the time-of-day alarm can be used as a power-saving timer, allowing the device to
remain in an extremely low-power mode, but still awaken periodically to perform assigned tasks. A second independent
32-bit 1/4096 subsecond alarm can be programmed with a tick resolution of 244μs. Both can be configured as recurring
alarms. When enabled, either alarm can cause an interrupt or wake the device from most low-power modes.
The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing
requirements in the Electrical Characteristics table.
The RTC calibration feature provides the ability for user software to compensate for minor variations in the RTC oscillator,
crystal, temperature, and board layout. Enabling the SQWOUT alternate function outputs a timing signal derived from the
RTC. External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with 1ppm
resolution. Under most circumstances, the oscillator does not require any calibration.

Programmable Timers
32-Bit Timer/Counter/PWM (TMR, LPTMR)
General-purpose, 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (PWM) signals
with minimal software interaction.
The timer provides the following features:
● 32-bit up/down autoreload
● Programmable prescaler
● PWM output generation
● Capture, compare, and capture/compare capability
● External pin multiplexed with GPIO for timer input, clock gating, or capture
● Timer output pin
● TMR0–TMR3 can be configured as 2 × 16-bit general-purpose timers
● Timer interrupt
The MAX78002 provides six 32-bit timers (TMR0, TMR1, TMR2, TMR3, LPTMR0, and LPTMR1). LPTMR0 and LPTMR1
are capable of operation in the SLEEP, LOW POWER, and MICRO POWER modes.
I/O functionality is supported for all of the timers. Note that the function of a port can be multiplexed with other functions
on the GPIO pins, so it might not be possible to use all of the ports depending on the device configuration. See Table 3
for individual timer features.
Table 3. Timer Configuration Options
REGISTER DUAL CLOCK SOURCE
SINGLE SINGLE POWER
INSTANCE ACCESS 16
32 BIT 16 BIT MODE PCLK ISO IBRO INRO ERTCO LPTMR0_CLK LPTMR1_CLK
NAME BIT
ACTIVE,
SLEEP,
TMR0 TMR0 Yes Yes No Yes Yes Yes No Yes No No
LOW
POWER
ACTIVE,
SLEEP,
TMR1 TMR1 Yes Yes No Yes Yes Yes No Yes No No
LOW
POWER
ACTIVE,
SLEEP,
TMR2 TMR2 Yes Yes No Yes Yes Yes No Yes No No
LOW
POWER

[Link] Analog Devices | 48

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
Table 3. Timer Configuration Options (continued)
ACTIVE,
SLEEP,
TMR3 TMR3 Yes Yes No Yes Yes Yes No Yes No No
LOW
POWER
ACTIVE,
SLEEP,
LOW
LPTMR0 TMR4 No No Yes No No Yes Yes Yes Yes No
POWER,
MICRO
POWER
ACTIVE,
SLEEP,
LOW
LPTMR1 TMR5 No No Yes No No Yes Yes Yes No Yes
POWER,
MICRO
POWER

Watchdog Timer (WDT)

Microcontrollers are often used in harsh environments where electrical noise and electromagnetic interference (EMI) are
abundant. Without proper safeguards, these hazards can disturb device operation and corrupt program execution. One
of the most effective countermeasures is the windowed watchdog timer (WDT), which detects runaway code or system
unresponsiveness.
The WDT is a 32-bit, free-running counter with a configurable prescaler. When enabled, the WDT must be periodically
reset by the application software. Failure to reset the WDT within the user-configurable timeout period indicates that the
application software is not operating correctly and results in a WDT timeout. A WDT timeout can trigger an interrupt,
system reset, or both. Either response forces the instruction pointer to a known good location before resuming instruction
execution. The windowed timeout period feature provides more detailed monitoring of system operation, requiring the
WDT to be reset within a specific window of time. See Table 4 for individual timer features.
The MAX78002 provides two instances of the watchdog timer—WDT0 and LPWDT0.
Table 4. Watchdog Timer Configuration Options
CLOCK SOURCE
INSTANCE NAME REGISTER ACCESS NAME POWER MODE
PCLK IBRO INRO ERTCO
ACTIVE,
WDT0 WDT0 SLEEP, Yes Yes No No
LOW POWER
ACTIVE,
SLEEP,
LPWDT0 WDT1 No Yes Yes Yes
LOW POWER,
MICRO POWER

Pulse Train Engine (PT)

Multiple, independent pulse train generators can provide either a square-wave or a repeating pattern from 2 to 32 bits
in length. Any single pulse train generator or any desired group of pulse train generators can be synchronized at the bit
level, allowing for multibit patterns. Each pulse train generator is independently configurable.
The pulse train generators provide the following features:
● Independently enabled
● Safe enable and disable for pulse trains without bit banding
● Multiple pin configurations allow for flexible layout
● Pulse trains can be started/synchronized independently or as a group
● Frequency of each enabled pulse train generator is also set separately, based on a divide down (such as divide by 2,
divide by 4, and divide by 8) of the input pulse train module clock

[Link] Analog Devices | 49

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
● Input pulse train module clock can be optionally configured to be independent from the system AHB clock
● Multiple repetition options
• Single shot (nonrepeating pattern of 2 to 32 bits)
• Pattern repeats user-configurable number of times or indefinitely
• Termination of one pulse train loop count can restart one or more other pulse trains
The pulse train engine feature is an alternate function associated with a GPIO pin. In most cases, enabling the pulse train
engine function supersedes the GPIO function.
The MAX78002 provide up to four instances of the pulse train engine peripheral (PT[3:0]).

Serial Peripherals
High-Speed USB Peripheral
The integrated USB peripheral is compliant with the High-Speed (480Mb/s) USB 2.0 specification. The integrated USB
physical interface (PHY) reduces board space and system cost. An integrated voltage regulator enables smart switching
between the main supply and VDDB when connected to a USB host controller. The USB peripheral supports DMA for
the endpoint buffers. A total of 11 endpoint buffers are supported with configurable selection of IN or OUT in addition to
endpoint 0.

I2C Interface (I2C)

The I2C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can
operate as a one-to-one, one-to-many or many-to-many communications medium. These engines support Standard-
mode, Fast-mode, Fast-mode Plus, and High-speed mode I2C speeds. It provides the following features:
● Controller or target mode operation
• Supports up to four different target addresses in target mode
● Supports standard 7-bit addressing or 10-bit addressing
● RESTART condition
● Interactive receive mode
● Tx FIFO preloading
● Support for clock stretching to allow slower target devices to operate on higher speed busses
● Multiple transfer rates
• Standard-mode: 100kbps
• Fast-mode: 400kbps
• Fast-mode Plus: 1000kbps
• High-speed mode: 3.4Mbps
● Internal filter to reject noise spikes
● Receiver FIFO depth of 8 bytes
● Transmitter FIFO depth of 8 bytes
The MAX78002 provides three instances of the I2C peripheral—I2C0, I2C1, and I2C2.

I2S Interface (I2S)

The I2S interface is a bidirectional, four-wire serial bus that provides serial communications for codecs and audio
amplifiers compliant with the I2S Bus Specification, June 5, 1996. It provides the following features:
● Controller and target mode operation
● 8, 16, 24, and 32 bit frames
● Receive and transmit DMA support
● Wakeup on FIFO status (full/empty/threshold)
● Pulse density modulation support for receive channel
● Word select polarity control
● First bit position selection
● Interrupts generated for FIFO status
● Receiver FIFO depth of 32 bytes

[Link] Analog Devices | 50

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
● Transmitter FIFO depth of 32 bytes
The MAX78002 provides one instance of the I2S peripheral (I2S).

Serial Peripheral Interface (SPI)

SPI is a highly configurable, flexible, and efficient synchronous interface among multiple SPI devices on a single bus. The
bus uses a single clock signal and multiple data signals, and one or more target select lines to address only the intended
target device. The SPI operates independently and requires minimal processor overhead.
The provided SPI peripherals can operate in either target or controller mode and provide the following features:
● SPI modes 0, 1, 2, or 3 for single-bit communication
● 3- or 4-wire mode for single-bit target device communication
● Full-duplex operation in single-bit, 4-wire mode
● Dual and quad data modes supported
● Multiple target selects on some instances
● Multicontroller mode fault detection
● Programmable interface timing
● Programmable SCK frequency and duty cycle
● 32-byte transmit and receive FIFOs
● Target select assertion and deassertion timing with respect to leading/trailing SCK edge
The MAX78002 provides two instances of the SPI peripheral—SPI0 and SPI1. See Table 5 for configuration options.

Table 5. SPI Configuration Options

TARGET MAXIMUM FREQUENCY MAXIMUM FREQUENCY
INSTANCE DATA
SELECT LINES CONTROLLER MODE (MHz) TARGET MODE (MHz)
3-wire, 4-wire, dual, or
SPI0 3 60 60
quad data support
3-wire, 4-wire, dual, or
SPI1 1 30 60
quad data support

UART (UART, LPUART)

The universal asynchronous receiver-transmitter (UART, LPUART) interface supports full-duplex asynchronous
communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a
given port, the system uses two extra pins to implement the industry-standard request to send (RTS) and clear to send
(CTS) flow control signaling. Each instance is individually programmable.
● 2-wire interface or 4-wire interface with flow control
● 8-byte send/receive FIFO
● Full-duplex operation for asynchronous data transfers
● Interrupts available for frame error, parity error, CTS, Rx FIFO overrun, and FIFO full/partially full conditions
● Automatic parity and frame error detection
● Independent baud-rate generator
● Programmable 9th-bit parity support
● Multidrop support
● Start/stop bit support
● Hardware flow control using RTS/CTS
● 12.5Mbps for UART maximum bit rate
● 1.85Mbps for LPUART maximum bit rate
● Two DMA channels can be connected (read and write FIFOs)
● Programmable word size (5 bits to 8 bits)
The MAX78002 provides four instances of the UART peripheral—UART0, UART1, UART2, and LPUART0. LPUART0 is
capable of operation in the SLEEP, LOW POWER, and MICRO POWER modes. See Table 6 for configuration options.

1-Wire Controller (OWM)

Analog Device's 1-Wire bus consists of one signal that carries data and also supplies power to the target devices and
a ground return. The bus controller communicates serially with one or more target devices through the bidirectional,
multidrop 1-Wire bus. The single-contact serial interface is ideal for communication networks requiring minimal
interconnection.
The provided 1-Wire controller supports the following features:
● Single contact for control and operation
● Unique factory identifier for any 1-Wire device
● Multiple device capability on a single line
The OWM supports both standard (15.6kbps) and overdrive (110kbps) speeds.

Standard DMA Controller

The standard DMA controller allows automatic one-way data transfer between two entities. These entities can be
either memories or peripherals. The transfers are done without using CPU resources. The following transfer modes are
supported:
● 4-channel
● Peripheral to data memory
● Data memory to peripheral
● Data memory to data memory
● Event support
All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from
the FIFO.
The MAX78002 provides one instance of the standard DMA controller.

Security
AES
The dedicated hardware-based AES engine supports the following algorithms:
● AES-128
● AES-192
● AES-256
The AES keys are automatically generated by the engine and stored in dedicated flash to protect against tampering. Key
generation and storage is transparent to the user.

[Link] Analog Devices | 52

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator
True Random Number Generator (TRNG) Non-Deterministic Random Bit Generator (NDRBG)
The device provides a non-deterministic entropy source that can be used to generate cryptographic seeds or strong
encryption keys as part of an overall framework for a secure customer application.
Software can use random numbers to trigger asynchronous events that add complexity to program execution to thwart
replay attacks or key search methodologies.
The TRNG can support the system-level validation of many security standards. Analog Devices will work directly with
the customer’s validation laboratory to provide the laboratory with any required information. Contact Analog Devices for
details of compliance with specific standards.

CRC Module
A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application
software. It supports a user-defined programmable polynomial up to 32-bits. Direct memory access copies data into
the CRC module so that CRC calculations on large blocks of memory are performed with minimal CPU intervention.
Examples of common polynomials are depicted in Table 7.
Table 7. Common CRC Polynomials
ALGORITHM POLYNOMIAL EXPRESSION
CRC-32-ETHERNET x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + x0
CRC-CCITT x16 + x12 + x5 + x0
CRC-16 x16 + x15 + x2 + x0
USB DATA x16 + x15 + x2 + x0
PARITY x1 + x0

Bootloader
The bootloader allows loading and verification of program memory through a serial interface. It provides the following
features:
● Bootloader interface through UART
● Program loading of Motorola® SREC format files
● Permanent lock state prevents altering or erasing program memory
● Access to the USN for device or customer application identification
● Disabling of the SWD interface to block debug access port functionality
The bootloader interface pins listed in Table 8 must be accessible to the host to use the bootloader.

Secure Boot
The secure boot feature available on some devices ensures software integrity by automatically comparing program
memory against a stored HMAC SHA-256 hash value after every reset. Programs that fail the integrity check indicate
corrupted or modified program memory and are prevented from executing any instructions. Devices with the secure boot
feature provide additional security through an optional challenge/response feature that authenticates before executing
bootloader commands.

Debug and Development Interface (SWD, JTAG)

The serial wire debug interface is used for code loading and ICE debug activities for the CM4. A JTAG interface is
provided for the RV32. All devices in mass production have the debugging/development interface enabled.
Motorola is a registered trademark of Motorola Trademark Holdings, LLC.

[Link] Analog Devices | 53

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Applications Information
Bypass Capacitors
The proper use of bypass capacitors reduces noise generated by the IC into the ground plane. The Pin Descriptions table
indicates which pins should be connected to bypass capacitors, and the appropriate ground plane.
It is recommended that one instance of a bypass capacitor should be connected to each power pin/ball of the IC package.
For example, if the Pin Descriptions table shows four device pins associated with voltage supply A, a separate capacitor
should be connected to each pin for a total of four capacitors.
Capacitors should be placed as close as possible to their corresponding device pins. When more than one value of
capacitor per pin is recommended, the capacitors should be placed in parallel starting with the lowest value capacitor
closest to the pin.

Bootloader Activation
The bootloader interface options are shown in Table 8. The bootloader is activated if the activation pins are in their active
state before exiting any reset and remain in that state until the bootloader sends the first command prompt through the
interface. If the pins are not in their active state, the device will perform a secure boot and, if successful, begin execution
of the application code. The design must ensure the activation pins and the RSTN pin are available to the host so it can
activate the bootloader.
Note: It is recommended that at least one of the bootloader activation pins are connected to a 10kΩ pull-up resistor to
ensure that the pins are in their inactive state during reset.
Table 8. Bootloader Interface
ACTIVATION PINS INTERFACE
P0.0 UART0A_RX (Active Low) P0.0 UART0A_RX
P0.29 SWDCLK (Active Low) P0.1 UART0A_TX

Ordering Information
FLASH SYSTEM SECURE
PART BOOTLOADER PIN-PACKAGE
(MB) RAM (KB) BOOT
384 + ECC 144 CSBGA, 12mm x 12mm x 1.3mm, 0.8mm
MAX78002GXE+ 2.5 Yes No
8 pitch

[Link] Analog Devices | 54

MAX78002 Artificial Intelligence Microcontroller with
Low-Power Convolutional Neural Network
Accelerator

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 6/22 Initial release —

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of
their respective owners.
w w w . a n a l o g . c o m Analog Devices | 55

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