usw [a]slif | T] 1 [| 4} @=z=| RECE26 _) Siddaganga Institute of Technology, Tumakuru — 572 103 o Astnomous Intend VIU, Daag Apo by AICTE, New Dal) Fifth Semester B.E. Electronics & Communicstion Engg. Examinations Feb. - Mar. 2022 Advanced Computer Architecture Time: 3 Hours Max. Marks: 100 Note Answer any five questions choosing one full question from each unit. Unit-1 1 a) Along with a diagram, justify the role of different elements of modern computer architecture in the context of parallel processing. 6 foe 3 Peo Te Tre: or] b) A500 MHz processor was used to execute a program with the following detai Tasiraction Type Insizuetion count_[_ Clock Cyete count Data Transer "50000 2 Contol Transfer 250000 2 Integer Arithmetic 00000 1 Floating point aries 320000 z Determine the effective CPI, MIPS rate, CPU throughput and execution time for this program. 6 2 eo: fro |e ©) Analyse the Flynn’s classification of computer architecture with relevant diagrams. [mea Per Pro. wo) OR 2 a) Analyse the architectural evolution from sequential scalar computer to vector processors and parallel computers. m: [3 feo Ta 7 b) Compare implicit parallelism and explicit parallelism from programmer and architectural perspectives. gram, analyse the architecture of a vector super computer emphasizing ¢) With a suitable block on register-to-register architecture. See Te Pea Unit-E 3 a) Forthe given 2x2 matrices multiplication algorithm, develop i) Fine grain program graph ii) Grain packing of 15 small nodes in to 5 bigger nodes. Assume IPC=212, multiplication and addition require 101 and 8 cycles respectively. Cn= Anx But Aix Br Ci2= Aix Biot Arex Bar Ca1= Aux B+ Azox Bat Cx2= Aux Bi2+ An+ Bao Sum = Ci + Cr+ Cat Coz 3 co: b) Compare control flow, data flow and demand driven computers. Please Turn Over2+ RECE26 For the given program below develop i) Hardware parallelism cyvae1@ © @Q @ ° with two-issue processor which can execute one memory access 64 Neg iS (load or write) and one arithmetic operation simultaneously >< ii) Dual-processor execution of the program. Also compute ¢yae3 CG) = hardware parallelism in both the cases and software parallelism i z for the given program, Fig. Xe) 5 m3 o> me 2 KOT OR a) Detect parallelism in the following program using Bernstein's conditions. Develop i) Data and resource dependence graph ii) Sequential execution iii) Parallel execution PI:C=DxE; P2:M=G+C; P3:A=B=C; P4:C=L+M: PS:F=GE 6 6 ©) For the given program i) Develop the fine grain program graph with 17 nodes before packing and ii) Coarse grain program graph with 5 nodes after packing. Assume grain sizes of memory load operation is 1. multiplication operation is 2 and all communication delays are 4 10. I. 12. 13. 14, 15. 16. pz 17. = 8 Unit - 2) Draw and analyse parallelism profile of a divide-and-conquer algorithm. Derive the expression for asymptotic speedup. 6 b) Derive expression for i) System efficiency i) Utilization and ifi) Quality of parallelism with respect to parallel processing. 6 3 co , | ©) Derive an expression for Amdahl's law, starting from weighted harmonic mean speedup. Also draw and analyse the speedup Vs n for different a (sequential bottle neck) values, 8 Bs Contd.Se RECE26 or ‘adding n-numbers on p-processors i, 6 a). Show that the efficiency of parallel system for : GEE YL) ee ee by Analyse the differem basic metrics affecting the scalability of @ parallel computing 5° 6 «) Compare speedup models fori) fixed workload (Amdahl's lat) and fxed time (Gustafson's 4) application models of parallel computers with relevant sketches. : 8 Unit —1V 7 a) With block diagram, compare hardware features built into CISC and RISC processors: 6 b) Along with block diagram, explain VAX 8600 CISC processor architecture: 6 ©) Along with the block diagram, illustrate the significance of each block of the POWER architecture of the IBM RISC system/6000 superscalar processor. 8 me eee ee eT oR 8 a) With diagram, analyse the data path architecture and control unit of a typical, simple scalar processor. - 6 b) Along with block diagram, explain the architecture of a typical VLIW processor 6 ©) Along with block diagram, explain Intel i860 RISC processor. - 8 9 a) Derive the expressions for i) Speedup factor if) PCR ii) Efficiency for a linear k-stage pipeline processor. : b) Compare linear pipelining and non-linear pipelining along with relevant sketches and reservation tables. : c)_ Implement the following dot product operation, using internal data forwarding between a multiply unit and an add unit and also show that data forwarding will reduce the execution time. s= DE xb; 8 10 OR : a) Consider the execution of a program of 15,00,000 instructions by a linear pipeline processor with a clock rate of 1000MHz. Assume pipeline has 5 stages. Calculate i) the speedup factor due to 6 the pipelining ii) efficiency and_ iii) throughput of this pipelined processor. Please Turn OverRECE26 b) Considering PCR (performance/cost ratio), show that that optimal number of pipelined stages ko is given by ke E Where ¢, t, d and h are standard notations. [a js feo fs ron | ©) Consider the following pipeline reservation table. TT2{[3]4[ ss St x sr |x x 3 x SH x 35 ¥ x i) Find the set of forbidden latencies and the collision vector ii) Draw the state transition diagram iii) Find all simple cycle and greedy cycles iv) Find MAL (Minimum average latency) v) Let the Pipeline clock period be t = 20ns. Find the throughput of the pipeline. bs oS | PO? so: 1