CLASS ASSIGNMENT 2
date : 01-06-2022
QUESTIONS
1. Difference between $display and $strobe and $monitor with code
2. Write a verilog code for generating 5 random between 1.0 and 2.0.
3. write RTL for 3:8 decoder using shift operator
4. Write an RTL for N bit shift register using for loop?
1) DIFFERENCE BETWEEN $DISPLAY AND $STROBE AND $MONITOR WITH CODE
$display
1. $display is used to display values of variables or strings or expressions.
2. It inserts a new line at the end of the string by default.
3. $display without any argument produces a new line.
EXAMPLE CODE
// RTL
module test_t(a,b,c,x,y);
input a,b,c;
output reg x,y;
always@(*)
begin
x <= a + b;
y <= a - b;
x <= c;
end
endmodule
// TESTBENCH
module test();
reg a,b,c;
wire x,y;
test_t DUT(a,b,c,x,y);
initial
begin
#10 a = 1'b1;
#10 b = 1'b0;
#10 c = 1'b0;
end
initial
$display("inputs = %b %b %b outputs = %b %b",a,b,c,x,y); // $display is used to display values of
a,b,c,x,y
initial
#50 $finish();
endmodule
$strobe
1. Strobing is done with system task called $strobe.
2. $strobe is much similar to $display except,if multiple statements and $display are executed at same
time unit the execution of $display is non-deterministic,where as $strobe is executed after all other
assignment statements complete the execution.
3. $strobe provides synchronization in simulation environment ,that is, data is displayed only after other
assignment statements which impact the values displayed by $strobe are executed.
EXAMPLE CODE
// RTL
module test_t(clk,b,d,a,c);
input clk,b,d;
output reg a,c;
always@(posedge clk)
begin
a = b;
c = d;
end
endmodule
// TESTBENCH
module test();
reg b,d,clk;
wire a,c;
test_t DUT(clk,b,d,a,c);
initial
begin
repeat(5)
clk = 1'b0;
#5 clk = ~clk;
end
initial
begin
#10 b = 1'b1;
#10 c = 1'b0;
#10 b = 1'b0; c = 1'b1;
end
always@(posedge clk)
$strobe("display a = %b,c = %b",a,c);
endmodule
$monitor
1. Mechanism to monitor a signal when it changes it value is provided by $monitor task.
2. Format used by $monitor is similar to that of $display .
3. It continuously monitors the parameter of signals mentioned and displays all parameters in the list
whenever the value of any one variable changes .
4. Unlike $display , $monitor gets invoked only once.
5. additional tasks called $monitoron and $monitoroff are used to start and terminate $monitor task
mid-way through the simulation.
EXAMPLE CODE
module test();
reg clk,rst;
initial
begin
repeat(5)
#5 clk = 1'b1;
#10 clk = 1'b0;
end
initial
begin
rst = 1'b0;
#20 rst = 1'b1;
#10 rst = 1'b0;
end
initial
$monitor($time,"value of clock signal = %b reset = %b",clk,rst);
endmodule
2) WRITE A VERILOG CODE FOR GENERATING 5 RANDOM BETWEEN 1.0 AND 2.0.
CODE
module test(y);
output reg y;
integer i;
always@(*)
begin
for(i=0;i<6;i=i+1)
y = {$random}%1.0 + 1.0;
end
endmodule
3) WRITE AN RTL CODE FOR 3:8 DECODER USING SHIFT OPERATOR
CODE
module decoder(d,y);
input [2:0] d;
output reg [7:0] y = 8'b00000001;
always@(*)
begin
case(d)
3'b000 : y <= y;
3'b001 : y <= d << 1;
3'b010 : y <= d << 2;
3'b011 : y <= d << 3;
3'b100 : y <= d << 4;
3'b101 : y <= d << 5;
3'b110 : y <= d << 6;
3'b111 : y <= d << 7;
default: y = 8'b00000001;
endcase
end
endmodule
4) WRITE AN RTL FOR N BIT SHIFT REGISTER USING FOR LOOP
CODE
module shift_reg(d,y);
input d;
output reg [9:0] y = 10'b0000111101;// initialized the output to 10 bit binary 0000111101
integer i;
always@(*)
begin
for(i=0;i<10;i=i+1)
y = {d,y[9-1:0]}; // assigning input to LSB everytime new value is entered to d
end
endmodule
