Course Instructor: Ms.

Saba Zia
Gate Level Modeling
CLO3, PLO3

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Introduction
 Structural Modeling ~ Gate level Modeling
 Equivalent to schematic diagram
 Structural model is created from built-in primitives or user-defined
primitives
 Built-in Verilog primitives are basic gates built into the Verilog language

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 Introduction to Verilog
Keywords Module Name Input and Output Ports (write outputs
first for better programming practice)

Port Declaration

(write outputs first)

Instance name

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Built-in Primitives (Gate Types)
Single output but  module logic_cct (a, b, out);
extendable inputs
Detect error in the
code with respect
input a, b; to execution of
statements and
output out; rectify it
and ins2and (out ,a, b);
nand ins2nand (out , a, b);
or ins2or (out ,a, b);
nor ins2nor (out , a, b);
xor ins2xor (out ,a, b);
xnor ins2xnor (out , a, b);
xnor ins3xnor (out , a, b, c);
endmodule
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Truth Tables

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Built-in Primitives (Gate Types)
 These primitives have
one scalar input but
extendable outputs.
 Buf
 (pass-through
primitive)

 Not
 (inverter primitive)

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Conditional Buf/Not

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Gate Delays
 Physical circuits exhibit propagation delay
 Therefore, sometimes necessary to specify delays only in simulation

and #(30) G1(w1,A,B);

not #(10) G2 (E,C);
or #(20) G3 (D,w1,E);

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Examples- Gate Level Modeling
 module logic_cct (out,a, b, c, d);
input a,b,c,d;
a
output out; w3
b w1
w4
wire w1,w2,w3,w4;
out
and ins1(w1,a,b);
c
and ins2(w2,c,d); d w2 logic_cct.v
not ins3(w3,w1);
xor ins4(w4,w3,w2);
not ins5(out,w4);
endmodule

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Calling a Module into
another Module - out
Port Mapping w a
w3
x b w1
 Positional Mapping w4

module port_mapping(out, w, x, y, z); out

y c
input w,x,y,z; w2
z d logic_cct
output out;
logic_cct ins_logic (out, w, x, y, z); port_mapping.v
endmodule

 Named Mapping
module port_mapping(out, w, x, y, z);
input w,x,y,z;
output out;
logic_cct ins_logic (.out(out),.a(w), .b(x), .c(y), .d(z));
endmodule 3/26/2021 12
Multiplexer Implementation (Gate level)- 2X1 MUX
A X A X1 X0 X
0 X0 0 0 0 0 X = A’ . X0 + A . X1
1 X1 0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
not ins1 (w1,A);
w1
w2 not ins2 (w2,w1);
w3
and ins3 (w3,w2,X1);
and ins4 (w4,w1,X0);
w4 or ins5 (X,w3,w4);
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Task
 Design 4X1 MUX using 2X1 MUX and write its Verilog HDL code using gate
level modeling.

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