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Asynchronous Counter Lab Experiment

This document describes designing and verifying a 4-bit ripple counter. It discusses asynchronous (ripple) counters and how they work by clocking each successive flip-flop from the output of the previous one. A 4-bit ripple counter circuit is shown using JK flip-flops. The lab procedure involves connecting the components as shown and observing the output at each stage as clock pulses are applied sequentially. Several pre-lab and post-lab questions are provided about ripple counters, decade counters, and timing.

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Shristi Sinha
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847 views2 pages

Asynchronous Counter Lab Experiment

This document describes designing and verifying a 4-bit ripple counter. It discusses asynchronous (ripple) counters and how they work by clocking each successive flip-flop from the output of the previous one. A 4-bit ripple counter circuit is shown using JK flip-flops. The lab procedure involves connecting the components as shown and observing the output at each stage as clock pulses are applied sequentially. Several pre-lab and post-lab questions are provided about ripple counters, decade counters, and timing.

Uploaded by

Shristi Sinha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Lab 11: Design of 4 bit Ripple Counter

11.1 Aim
To design and verify the timing diagram of 4 bit Ripple Counter.

11.2 Hardware Requirement


a. Equipment - Digital IC Trainer Kit
b. Discrete Components - IC7473 Dual JK Flip-flop

11.3 Introduction

Circuits for counting events are frequently used in computers and other digital systems. Since a
counter circuit must remember its past states, it has to possess memory. The number of flip flops
used and how they are connected determine the number of states and the sequence of the states that
the counter goes through in each complete cycle. Counters can be classified into two broad
categories according to the way they are clocked:

a. Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse,
and then each successive flip -flop is clocked by the Q or Q' output of the previous flip -
flop.
b. Synchronous Counters - all memory elements are simultaneously triggered by the same
clock.

Asynchronous Counter:

If the flip-flops do not receive the same clock signal, then that counter is called as Asynchronous
counter. The output of system clock is applied as clock signal only to first flip-flop. The remaining
flip-flops receive the clock signal from output of its previous stage flip-flop. Hence, the outputs of
all flip-flops do not change affect at the same time.

4 BIT RIPPLE COUNTERS

Figure 11.1: 4-bit Asynchronous Counter


Figure 11.2: Timing Diagram

11.4 Pre lab questions


1. Mention why Asynchronous counter is referred as Ripple Counter?
2. What is the purpose of Preset input?
3. Sketch the timing diagrams for mod 6 counter.
4. What is a decade counter?
5. What is the race-around condition?

11.5 Lab Procedure


1. Connections are made as per circuit diagram.
2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA, QB
& QC, QD.

11.6 Post lab questions


1. Design a 4-bit frequency divider.
2. Define state table & how many states are required to design 6-bit ripple counter?
3. A 4-bit binary ripple counter uses Flip-flops with propagation delay time of 25ns
each. The maximum possible time required for change state will be ------------------- --.
4. How many Flip-flops a decade counter will require?
5. What is the maximum number that can be obtained by a ripple counter by using
five Flip-flop?

11.7 Open Ended Question

Design MOD-10 counter and verify it in logisim software.

11.8 Result:

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