CommunicationConcepts

Characteristicsof CommunicationSystems Communication Systems

must be a Sender and Receiver A protocol is a set of rules which governs the transfer of data between computers. Protocols allow communication between computers and networks. Handshaking is used to establish which protocols to use. g p Handshaking controls the flow of data between computers protocols will determine the speed of transmission, error checking method size of bytes and whether synchronous method, bytes, or asynchronous

5BasicComponents
Every communication system has 5 basic requirements Data Source (where the data originates) Transmitter (device used to transmit data) Transmission Medium (cables or non cable) Receiver (device used to receive data) Destination (where the data will be placed)

5BasicComponents 5 Basic Components

TransmissionMediaSpeed
Bandwidth The amount of data which ca be a d dt e a ou t o c can
:

transmitted on a medium over a fixed amount of time (second). It is measured on Bits per Second or Baud

Bits per Second (bps): A measure of

transmission speed. The number of bits (0 0r 1) which can be transmitted in a second

Baud Rate Is a measure of how fast a change of

:

state occurs (i.e. a change from 0 to 1)

SynchronousVs AsynchronousTransmissions
Synchronous T S h Transmission i i
all data sent at once and no packet switching

Asynchronous Transmission y
Uses stop/ start bits yp most common type of serial data transfer Allows sharing of bandwidth (i.e. talk on phone p g ) while another person is using internet)

TransmissionDirection
simplex: One direction only

HalfDuplexTransmission Half Duplex Transmission

Halfduplex:Both directionsbut onlyone directionata time

FullDuplexTransmission Full Duplex Transmission

Fullduplex:send andreceive bothdirections atonce Eg: Telephone Eg:Telephone, MobilePhone

Transmission Direction

TransmissionMedia
twisted pair telephone cable twistedpair telephonecable coaxialcableThickblackcableusedforhigher bandwidthcommunicationsthantwistedpair bandwidth communications than twisted pair fibreoptic datatransferredthroughpulsesof light.Extremelyfast. li ht E t l f t Noncablemethodssuchassatelite, microwave,wirelessandbluetooth

Errordetectionandcorrection
Oftenpartofbusprotocol Errordetection:abilityofreceivertodetecterrorsduringtransmission Errorcorrection:abilityofreceiverandtransmittertocooperatetocorrect problem
Typicallydonebyacknowledgement/retransmissionprotocol

Biterror:singlebitisinverted Burstofbiterror:consecutivebitsreceivedincorrectly Parity:extrabitsentwithwordusedforerrordetection

Oddparity:datawordplusparitybitcontainsoddnumberof1s Evenparity:datawordplusparitybitcontainsevennumberof1s Al Alwaysdetectssinglebiterrors,butnotallburstbiterrors d t t i l bit b t t ll b t bit

Checksum:extrawordsentwithdatapacketofmultiplewords
e.g.,extrawordcontainsXORsumofalldatawordsinpacket

Basicsofserialcommunication
Parallel: expensive - short distance fast no modulation Serial :cheaper long (two different cities by modem)-slow

SerialTransmission Serial Transmission

Dataistransmitted,onasinglechannel,onebitatatime Data is transmitted, on a single channel, one bit at a time oneafteranother Muchfasterthanparallelbecauseofwaybitsprocessed (e.g.USBandSATAdrives)
1 0 0 1 1 0 0 1

Sender transmitted

Receiver received

SerialCommunications Transmissionmodes Transmission modes

Two basic transmission modes: Twobasictransmissionmodes: asynchronous:transmitterandreceiverclocksare independent p synchronous:transmitterandreceiverare synchronized y

SerialCommunications Comparisonoftransmissionmodes Comparison of transmission modes

Asynchronous: y
suitablefordatatransmittedatrandomintervals(e.g.keyboardtocomputer) largeoverhead(20%ormore) ratherlowdatarates(upto115.2kbps,practically38.4kbps) rather low data rates (up to 115.2 kbps, practically 38.4 kbps) simplicityandavailability:UARTandRS232arepresentinanyPC usedinthegreatmajorityofdialupconnections

Synchronous:
lowoverhead(longframes) highrates l lesspronetoerrors t

Serialcommunication Serial communication

Singledatawire,possiblyalsocontrolandpowerwires Wordstransmittedonebitatatime Higherdatathroughputwithlongdistances
Lessaveragecapacitance,somorebitsperunitoftime

Cheaper,lessbulky More complex interfacing logic and communication protocol Morecomplexinterfacinglogicandcommunicationprotocol

Senderneedstodecomposewordintobits Receiverneedstorecomposebitsintoword Controlsignalsoftensentonsamewireasdataincreasingprotocol complexity

ParallelTransmission
-each bit has its own piece of wire along which it travels - often used to send data to a printer

0 0 1 1 0 0 1

All bits are sent simultaneously

Rece eiver re eceived d

Sen nder tra ansmitted

Contents
Introduction Introduction Bus Protocol AMBA BUS I2C BUS CAN BUS CAN

Whatisabus?
ABusIs: sharedcommunicationlink shared communication link singlesetofwiresusedtoconnectmultiplesubsystems
Processor Input Control Memory Datapath Output

ABusisalsoafundamentaltoolforcomposinglarge, complexsystems complex systems systematicmeansofabstraction

Busses

AdvantagesofBuses

Processer

I/O Device

I/O Device

I/O Device

Memory

Versatility:
Newdevicescanbeaddedeasily P i h l Peripheralscanbemovedbetweencomputer b db systemsthatusethesamebusstandard

LowCost:
Asinglesetofwiresissharedinmultipleways

DisadvantageofBuses

Processor

I/O Device

I/O Device

I/O Device

Memory

Itcreatesacommunicationbottleneck
ThebandwidthofthatbuscanlimitthemaximumI/Othroughput

Themaximumbusspeedislargelylimitedby:
Thelength ofthebus h l h f h b Thenumber ofdevicesonthebus Theneedtosupportarangeofdeviceswith: Widelyvaryinglatencies Widelyvaryingdatatransferrates

Parallelcommunication Parallel communication

Multiple data, control, and possibly power wires Multipledata,control,andpossiblypowerwires
Onebitperwire

Highdatathroughputwithshortdistances g g p TypicallyusedwhenconnectingdevicesonsameIC orsamecircuitboard

Busmustbekeptshort
longparallelwiresresultinhighcapacitancevalueswhichrequires moretimetocharge/discharge more time to charge/discharge Datamisalignmentbetweenwiresincreasesaslengthincreases

Highercost,bulky g , y
24

Serialcommunication Serial communication

Singledatawire,possiblyalsocontrolandpowerwires Wordstransmittedonebitatatime d i d bi i Higherdatathroughputwithlongdistances
Lessaveragecapacitance,somorebitsperunitoftime

Cheaper,lessbulky Morecomplexinterfacinglogicandcommunication protocol

Sender needs to decompose ord into bits Senderneedstodecomposewordintobits Receiverneedstorecomposebitsintoword Control signals often sent on same wire as data increasing Controlsignalsoftensentonsamewireasdataincreasing protocolcomplexity

25

GeneralOrganizationofaBus
Control Lines Data Lines

Controllines:
Signalrequestsandacknowledgments I di t h t t Indicatewhattypeofinformationisonthedatalines fi f ti i th d t li

Datalinescarryinformationbetweenthe sourceandthedestination: d th d ti ti
DataandAddresses Complexcommands p

MasterversusSlave
Master issues command Bus Master Data can go either way Bus Slave

Abustransactionincludestwoparts: b l d
Issuingthecommand(andaddress) request Transferring the data Transferringthedata action

Master istheonewhostartsthebustransactionby:
issuingthecommand (andaddress)

Slave istheonewhorespondstotheaddressby:
Sendingdatatothemasterifthemasteraskfordata Receivingdatafromthemasterifthemasterwantstosenddata

SynchronousandAsynchronousBus
SynchronousBus:
Includesaclock inthecontrollines Afixedprotocolforcommunicationthatisrelativetotheclock Advantage: involvesverylittlelogicandcanrunveryfast g y g y Disadvantages: Everydeviceonthebusmustrunatthesameclockrate To avoid clock skew they cannot be long if they are fast Toavoidclockskew,theycannotbelongiftheyarefast

AsynchronousBus:
It is not clocked Itisnotclocked Itcanaccommodateawiderangeofdevices Itcanbelengthenedwithoutworryingaboutclockskew Itrequiresahandshakingprotocol

Bussessofar
Master Slave

Control Lines Address Lines Data Lines

BusMaster:hasabilitytocontrolthebus,initiates Bus Master: has ability to control the bus, initiates transaction BusSlave:moduleactivatedbythetransaction BusCommunicationProtocol:specificationofsequenceof eventsandtimingrequirementsintransferring information.

BusTransaction
A bit ti Arbitration: Request: Action: Whogetsthebus Wh t th b Whatdowewanttodo Whathappensinresponse

Arbitration: ObtainingAccesstotheBus Obtaining Access to the Bus

Control: M t i iti t C t l Master initiates requests t Bus Master Data can go either way Bus Slave

Oneofthemostimportantissuesinbusdesign:
How is the bus reserved by a device that wishes to use it? Howisthebusreservedbyadevicethatwishestouseit?

Chaosisavoidedbyamasterslavearrangement:
Only the bus master can control access to the bus: Onlythebusmastercancontrolaccesstothebus: Itinitiatesandcontrolsallbusrequests Aslaverespondstoreadandwriterequests p q

BusArbitration
Whenmore thanonedevicewantstobethebus master,weneedsomebusarbitration mechanismtopreventchaos. Acentralized arbitrationschemerequiresa dedicatedbusarbiter,whodetermineswhich deviceisthebusmasternext;hence,every deviceconnectstothebusarbiterwithone(or more)busrequestandone(ormore)busgrant lines.

Arbitration: ObtainingAccesstotheBus Obtaining Access to the Bus

Thesimplestsystem: Processor istheonlybusmaster Allbusrequestsmustbecontrolled bytheprocessor Majordrawback:theprocessorisinvolvedinevery transaction

MultiplePotentialBusMasters: theNeedforArbitration the Need for Arbitration

Busarbitrationscheme:
Abusmasterwantingtousethebusassertsthebusrequest Abusmastercannotusethebusuntilitsrequestisgranted Ab Abusmastermustsignaltothearbitertheendofthebus t t i l t th bit th d f th b utilization

Busarbitrationschemesusuallytrytobalancetwofactors:
Bus priority: the highest priority device should be serviced first Buspriority:thehighestprioritydeviceshouldbeservicedfirst Fairness:Eventhelowestprioritydeviceshouldnever becompletelylockedoutfromthebus

MultiplePotentialBusMasters: theNeedforArbitration the Need for Arbitration

Bus arbitration schemes can be divided into four broad Busarbitrationschemescanbedividedintofourbroad classes:
Daisychainarbitration y Centralized,parallelarbitration Distributedarbitrationbyselfselection:eachdevicewantingthe busplacesacodeindicatingitsidentityonthebus. Distributedarbitrationbycollisiondetection: Eachdevicejust goesforit Problems found after the fact Each device just goes for it.Problemsfoundafterthefact.

TheDaisyChainBus ArbitrationsScheme Arbitrations Scheme

Device 1 Highest Hi h t Priority Grant Bus Arbiter Grant Device D i 2 Device N Lowest L t Priority Grant Release Request

Advantage:simple Disadvantages:
Cannotassurefairness: Alowprioritydevicemaybelockedoutindefinitely Theuseofthedaisychaingrantsignalalsolimitsthebusspeed f

CentralizedParallelArbitration
Device 1 Device D i 2 Device N

Grant Bus Arbiter

Req

Usedinessentiallyallprocessormemorybusses y p y andinhighspeedI/Obusses

IncreasingtheBusBandwidth
Separateversusmultiplexedaddressanddatalines:
Addressanddatacanbetransmittedinonebuscycle ifseparateaddressanddatalinesareavailable Cost: (a) more bus lines (b) increased complexity Cost:(a)morebuslines,(b)increasedcomplexity

Data bus width: Databuswidth:

Byincreasingthewidthofthedatabus,transfersofmultiple wordsrequirefewerbuscycles Example:SPARCstation20smemorybusis128bitwide Cost:morebuslines

Multilevelbusarchitectures Multilevel bus architectures

Dont want one bus for all communication
Peripherals would need high-speed, processor-specific bus interface high-speed excess gates, power consumption, and cost; less portable Too many peripherals slows down bus
Microprocessor Cache Memory controller

DMA controller

Processorlocalbus High speed wide most Highspeed,wide,most frequentcommunication Connectsmicroprocessor, cache,memorycontrollers,etc.

Processor-local bus Peripheral Peripheral Peripheral Bridge

Peripheral bus

39

Multilevelbusarchitectures Multilevel bus architectures

Peripheralbus Lowerspeed,narrower,less frequentcommunication Typically industry standard bus Typicallyindustrystandardbus (ISA,PCI)forportability ISA:IndustryStandard Architecture A hit t

Microprocessor

Cache

Memory controller

DMA controller

Processor-local bus Peripheral Peripheral Peripheral Bridge

Peripheral bus

Bridge Single purpose processor converts communication between Single-purpose busses

40

Bridge
A Bridge is a slave on the fast bus and master ABridgeisaslave onthefastbusandmaster oftheslowbus Takes command from the fast bus on which it Takescommandfromthefastbusonwhichit isslave I Issuescommandsontheslowbus d h l b Returnsresultsfromslowbustofastbus Alsofunctionsasprotocoltranslator

August 26, 2011

41

AMBA
AdvancedMicrocontroller BusArchitecture

AMBAIntroduction AMBA Introduction

AdvancedMicrocontrollerBusArchitecture(AMBA),created byARM asaninterface fortheirmicroprocessors. Easy to obtain documentation (free download) and can be Easytoobtaindocumentation(freedownload)andcanbe usedwithoutroyalties. VerycommonincommercialSoCs (e.g.QualcommMultimediaCellphoneSoC) AMBA2.0releasedin1999,includesAPB andAHB

TheSystemonaChip
System Bus
DMA CPU DSP

Mem Ctrl. Ctrl

Bridge

MPEG

Custom Interfaces Control Wires Peripheral Bus

Systemonachip (SOC)requiresbusing (SOC) requires busing systemstoconnect variouscomponents, includingoneormore microprocessors, memories,peripherals ,p p andspeciallogic.

The Board-on-a-Chip Approach A h

AMBASpecification
AMBA: Advanced Microcontroller Bus Architecture A hit t Created by ARM to enable standardized interfaces to their embedded processors Actually three standards: APB, AHB, and AXI Very commonly used for commercial IP cores

45

AMBASpecification p
AMBA: Advanced Microcontroller Bus Architecture A hit t Created by ARM to enable standardized interfaces to their embedded processors
Simple Bus

Actually three standards: APB, AHB, and ASB Very commonly used for commercial IP cores

46

AMBASpecification
AMBA: Advanced Microcontroller Bus Architecture A hit t Created by ARM to enable standardized interfaces to their embedded processors
Simple Bus Complex Bus

Actually three standards: APB, AHB, Very commonly used for commercial IP cores

47

AMBASpecification
AMBA: Advanced Microcontroller Bus Architecture A hit t Created by ARM to enable standardized interfaces to their embedded processors
Simple Bus Complex Bus

Actually three standards: APB, AHB, AHB: Advanced high Speed Bus APB: Advanced Peripheral Bus Very commonly used for commercial IP cores
48

AMBAAHB

AHB addresses many of the limitations of APB:

multi-master multiple outstanding transactions (sort of...) back-to-back transactions

Unfortunately, this adds significant complexity

49

Bushierarchies Bus hierarchies

Advanced Microcontroller Bus Architecture AdvancedMicrocontrollerBusArchitecture (AMBA)
Advanced High performance Bus (AHB) AdvancedHighperformanceBus(AHB) AdvancedSystemBus(ASB) Advanced Peripheral Bus (APB) AdvancedPeripheralBus(APB).

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50

AMBA2.0SystemLevelView

Source: AMBA Specification, Rev. 2.0

AdvancedHighperformanceBus (AHB)
TheAMBAAHBisforhighperformance,highclock frequencysystemmodules. TheAHBactsasthehighperformancesystem backbone bus. AHBsupportstheefficientconnectionofprocessors, onchipmemories andoffchipexternalmemory hi i d ff hi l Interfaceswithlowpowerperipheralmacrocell functions. f ti AHBisalsospecifiedtoensureeaseofuseinan efficientdesignflowusingsynthesisandautomated efficient design flow using synthesis and automated test techniques.
RB - 2003/2005
52

AdvancedSystemBus (ASB)
The AMBA ASB is for highperformance system TheAMBAASBisforhigh performancesystem modules. AMBAASBisanalternativesystembussuitablefor y usewherethehighperformance featuresofAHBare notrequired. ASBalsosupportstheefficientconnectionof processors,onchipmemoriesandoffchipexternal memoryinterfaceswithlowpower peripheral f hl h l macrocellfunctions.

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53

AdvancedPeripheralBus (APB)
The AMBA APB is for lowpower peripherals TheAMBAAPB isforlow powerperipherals. AMBAAPBisoptimizedforminimalpower consumption and reduced interface andreducedinterface complexity tosupportperipheralfunctions. APBcanbeusedinconjunctionwitheither APB can be used in conjunction with either versionofthesystembus.

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54

ObjectivesoftheAMBAspecification j p
The AMBA specification has been derived to satisfy TheAMBAspecificationhasbeenderivedtosatisfy fourkeyrequirements:
tofacilitatetherightfirsttime developmentofembedded microcontroller productswithoneormoreCPUsorsignal processors to be technology independent and ensure that highly tobetechnologyindependentandensurethathighly reusable peripheraland systemmacrocellscanbe migratedacrossadiverserangeofICprocessesandbe appropriateforfullcustom,standardcellandgatearray technologies

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55

ObjectivesoftheAMBAspecification
To encourage modular system design to improve Toencouragemodular systemdesigntoimprove processorindependence, providinga developmentroadmapforadvancedcachedCPU coresandthe developmentofperipherallibraries Tominimizethesiliconinfrastructurerequiredto supportefficientonchipand offchip communicationforbothoperationand manufacturingtest. manufacturing test

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Serialprotocols:I2C Serial protocols: I2C

I2C(InterIC) ( )
TwowireserialbusprotocoldevelopedbyPhilips Semiconductorsnearly20yearsago EnablesperipheralICstocommunicateusingsimple communicationhardware Data transfer rates up to 100 kbits/s and 7bit addressing Datatransferratesupto100kbits/sand7 bitaddressing possibleinnormalmode 3.4Mbits/sand10bitaddressinginfastmode CommondevicescapableofinterfacingtoI2Cbus:
EPROMS,Flash,andsomeRAMmemory,realtimeclocks,watchdog timers,andmicrocontrollers timers, and microcontrollers
57

WhatisI What is I2C?

Shorthand for an Inter integrated circuit ShorthandforanInterintegratedcircuit bus DevelopedbyPhilipsSemiconductorforTV setsinthe1980s I2CdevicesincludeEEPROMs,thermal sensors,andreal timeclocks sensors, and realtime clocks Usedasacontrolinterfacetosignal processingdevicesthathaveseparatedata interfaces,e.g.RFtuners,videodecoders interfaces e g RF tuners video decoders andencoders,andaudioprocessors.

WhatisI What is I2C?

I2C bus has three speeds Cbushasthreespeeds: Slow(under100Kbps) Fast (400 Kbps) Fast(400Kbps) Highspeed(3.4Mbps) I2Cv.2.0 Limitedtoabout10feetformoderate speeds

I2CBusConfiguration g

2wireserialbus Serialdata(SDA)andSerial clock(SCL) Half duplex,synchronous,multi masterbus Halfduplex, synchronous, multimaster bus Nochipselectorarbitrationlogicrequired

I2CProtocol

clocksignal q 2.Mastersendsaunique7bitslavedeviceaddress 3.Mastersendsread/writebit(R/W) 0 slave receive,1 slavetransmit 4.Receiversendsacknowledgebit(ACK) 4 Receiver sends acknowledge bit (ACK) 5.Transmitter(slaveormaster)transmits1byteof data

1.Mastersendsstartcondition(S)andcontrols M t d t t diti (S) d t l

the th

I2CProtocol(cont.) ( )

6.ReceiverissuesanACKbitforthebytereceived 6 R i i ACK bit f th b t i d

7.Repeat5and6ifmorebytesneedtobetransmitted. 8.a)Forwritetransaction(mastertransmitting),masterissues 8 a) For write transaction (master transmitting) master issues stopcondition(P)afterlastbyteofdata. 8.b)Forreadtransaction(masterreceiving),masterdoesnot acknowledgefinalbyte,justissuesstopcondition(P)totell theslavethetransmissionisdone

I2CSignals

Start high-to-low transition of the SDA line while SCL line is high Stop low-to-high transition of the SDA line while SCL line is high Ack receiver pulls SDA low while transmitter allows it to float high Data transition takes place while SCL is slow, valid while SCL is high

I2Cbusstructure I2C bus structure

SCL SDA Microcontroller (master) EEPROM (servant) Addr=0x01 Temp. Sensor (servant) Addr=0x02 LCDcontroller (servant) Addr=0x03

SDA SCL Start condition

SDA SCL Sending 0

SDA SCL Sending 1 From Servant

SDA SCL Stop condition From receiver

D C
S T A R T A 6 A 5 A 0 R / w A C K D 8 D 7 D 0 A C K S T O P

Typical read/write cycle

64

Serialprotocols:CAN Serial protocols: CAN

CAN(Controllerareanetwork) Protocol for real time applications Protocolforrealtimeapplications DevelopedbyRobertBoschGmbH Originallyforcommunicationamongcomponentsofcars Originally for communication among components of cars ApplicationsnowusingCANinclude: elevatorcontrollers,copiers,telescopes,productionline controlsystems,andmedicalinstruments Datatransferratesupto1Mbit/s and11bitaddressing C CommondevicesinterfacingwithCAN: d i i t f i ith CAN 8051compatible8592processorandstandaloneCAN controllers
65

Serialprotocols:CAN Serial protocols: CAN

ActualphysicaldesignofCANbusnotspecifiedinprotocol Requires devices to transmit/detect dominant and Requiresdevicestotransmit/detectdominantand recessivesignalsto/frombus e.g.,1=dominant,0=recessiveifsingledatawireused Busguaranteesdominantsignalprevailsoverrecessive signalifassertedsimultaneously

66

USB

UniversalSerialBus Universal Serial Bus

Being introduced as a highspeed Beingintroducedasahigh speed replacementforthetraditionalRS232 port USBhashigherbandwidth
1 5 Mb 12 Mb 1.5Mbps,12Mbpsand480Mbps d 480 Mb FasterthantheRS232portthatoperatesin theregionof115+Kbps the region of 115+ K bps

Devicescanbedaisychained

DaisyChainingofUSBDevices
USB Connection Device 3

Computer

USB Port

In

Device 2

Device 1
Out

ConnectingUSBDevicesUsinga Hub
USB Connection Device 3

Computer

USB Port

Device 2
In

Hub
Out

SampleUSBDevices
Keyboards Monitors DigitalCameras i i lC DigitalVideRecorders etc.

USBStandards
USB 1 1 USB1.1 USB2.0 USBOnTheGo(OTG) S O h G (O G)
Anewerstandardbeingdesignedforportableand smalldevices ll d

OperatingSystemSupportforUSB
The operating systems such as Windows XP or the TheoperatingsystemssuchasWindowsXPorthe laterversionsofsomeoftheolderoperatingsystems supportUSB
Windows98 Windows95OSR2

InaccordancewithUSBstandards,theseoperating systemssupporthotplugandplayforUSBdevices

HotPlugandPlay
Theabilitytoconnectadevicetothe computerwhileacomputerisinoperation Asthedeviceisconnected,theOSwould:
Recognizethedevice g Configurethedevice

There is no manual intervention in the Thereisnomanualinterventioninthe aboveprocess

AdvantagesofUSBOvertheRS 232Port 232 Port

Higher speed Higherspeed Abilitytodaisychaindifferentdevices S Supportforhotplugandplay f h l d l

Serialprotocols:USB Serial protocols: USB

USB(UniversalSerialBus)
EasierconnectionbetweenPCandmonitors,printers,digitalspeakers, modems,scanners,digitalcameras,joysticks,multimediagameequipment 2datarates:
12Mbpsforincreasedbandwidthdevices 1.5Mbpsforlowerspeeddevices(joysticks,gamepads)

Tieredstartopologycanbeused
O USB d i (h b) OneUSBdevice(hub)connectedtoPC d PC
hubcanbeembeddedindeviceslikemonitor,printer,orkeyboardorcanbestandalone

MultipleUSBdevicescanbeconnectedtohub Upto127devicescanbeconnectedlikethis p

USBhostcontroller
Managesandcontrolsbandwidthanddriversoftwarerequiredbyeachperipheral Dynamicallyallocatespowerdownstreamaccordingtodevices connected/disconnected

FIREWIRE

Serialprotocols:FireWire
HighperformanceserialbusdevelopedbyAppleComputer Inc. Designedforinterfacingindependentelectroniccomponents e.g.,Desktop,scanner e g Desktop scanner Datatransferratesfrom12.5to400Mbits/s,64bitaddressing Plugandplaycapabilities g p y p Packetbasedlayereddesignstructure ApplicationsusingFireWireinclude: diskdrives,printers,scanners,cameras

IEEE1394Standard(FireWire)
I Insomeways,itcompeteswithUSB it t ith USB Bandwidthis400Mbpsor50MBps I h Intheorytherefore,itcanreplaceolderSCSIand h f i l ld SCSI d IDEusedforconnectingharddisks Fi Wi i FireWiresimpactismostlikelytobefeltin ti t lik l t b f lt i multimedia applicationsinvolvingaudio and video Somebasicnetworkingcanbedonethroughthe Firewireportsaswell Firewire ports as well

DataTransmission
100 Mbps 200 Mbps and 400 Mbps 100Mbps,200Mbpsand400Mbps Newerportsarebeingdevelopedtosupport 800Mbpsand1600Mbps 800 Mbps and 1600 Mbps Dataistransmittedinpacketsanditis availabletoallthedevicesonthebus il bl ll h d i h b

TypeofTransmission
Asynchronous(bulk)transfer guarantees correcttransmission;suitableforcontrol dataandwhereerrorfreetransmission takesprecedenceoverspeed. Isochronoustransfer guarantees bandwidth(idealfortransmittingtime criticaldata,e.g.video,audio) ld d d ) Courtesy:www.thesycon.de

AMBA
AdvancedMicrocontroller BusArchitecture

Parallelprotocols:ARMBus
ARMBus
DesignedandusedinternallybyARMCorporation InterfaceswithARMlineofprocessors ManyICdesigncompanieshaveownbusprotocol Datatransferrateisafunctionofclockspeed
IfclockspeedofbusisX,transferrate=16xXbits/s

32bitaddressing

AMBAIntroduction AMBA Introduction

AdvancedMicrocontrollerBusArchitecture(AMBA),created byARM asaninterface fortheirmicroprocessors. Easy to obtain documentation (free download) and can be Easytoobtaindocumentation(freedownload)andcanbe usedwithoutroyalties. VerycommonincommercialSoCs (e.g.QualcommMultimediaCellphoneSoC) AMBA2.0releasedin1999,includesAPB andAHB

TheSystemonaChip
System Bus
DMA CPU DSP

Mem Ctrl. Ctrl

Bridge

MPEG

Custom Interfaces Control Wires Peripheral Bus

Systemonachip (SOC)requiresbusing (SOC) requires busing systemstoconnect variouscomponents, includingoneormore microprocessors, memories,peripherals ,p p andspeciallogic.

The Board-on-a-Chip Approach A h

AMBASpecification
AMBA: Advanced Microcontroller Bus Architecture A hit t Created by ARM to enable standardized interfaces to their embedded processors Actually three standards: APB, AHB, and AXI Very commonly used for commercial IP cores

86

AMBASpecification p
AMBA: Advanced Microcontroller Bus Architecture A hit t Created by ARM to enable standardized interfaces to their embedded processors
Simple Bus

Actually three standards: APB, AHB, and ASB Very commonly used for commercial IP cores

87

AMBASpecification
AMBA: Advanced Microcontroller Bus Architecture A hit t Created by ARM to enable standardized interfaces to their embedded processors
Simple Bus Complex Bus

Actually three standards: APB, AHB, Very commonly used for commercial IP cores

88

AMBASpecification
AMBA: Advanced Microcontroller Bus Architecture A hit t Created by ARM to enable standardized interfaces to their embedded processors
Simple Bus Complex Bus

Actually three standards: APB, AHB, AHB: Advanced high Speed Bus APB: Advanced Peripheral Bus Very commonly used for commercial IP cores
89

AMBAAHB

AHB addresses many of the limitations of APB:

multi-master multiple outstanding transactions (sort of...) back-to-back transactions

Unfortunately, this adds significant complexity

90

Bushierarchies Bus hierarchies

Advanced Microcontroller Bus Architecture AdvancedMicrocontrollerBusArchitecture (AMBA)
Advanced High performance Bus (AHB) AdvancedHighperformanceBus(AHB) AdvancedPeripheralBus(APB).

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91

AMBA2.0SystemLevelView

Source: AMBA Specification, Rev. 2.0

AdvancedHighperformanceBus (AHB)
TheAMBAAHBisforhighperformance,highclock frequencysystemmodules. TheAHBactsasthehighperformancesystem backbone bus. AHBsupportstheefficientconnectionofprocessors, onchipmemories andoffchipexternalmemory hi i d ff hi l Interfaceswithlowpowerperipheralmacrocell functions. f ti AHBisalsospecifiedtoensureeaseofuseinan efficientdesignflowusingsynthesisandautomated efficient design flow using synthesis and automated test techniques.
93

AdvancedSystemBus (ASB)
The AMBA ASB is for highperformance system TheAMBAASBisforhigh performancesystem modules. AMBAASBisanalternativesystembussuitablefor y usewherethehighperformance featuresofAHBare notrequired. ASBalsosupportstheefficientconnectionof processors,onchipmemoriesandoffchipexternal memoryinterfaceswithlowpower peripheral f hl h l macrocellfunctions.

94

AdvancedPeripheralBus (APB)
The AMBA APB is for lowpower peripherals TheAMBAAPB isforlow powerperipherals. AMBAAPBisoptimizedforminimalpower consumption and reduced interface andreducedinterface complexity tosupportperipheralfunctions. APBcanbeusedinconjunctionwitheither APB can be used in conjunction with either versionofthesystembus.

95

Serialprotocols:I2C
I2C(InterIntegratedCircuit)
TwowireserialbusprotocoldevelopedbyPhilipsSemiconductorsnearly 20yearsago EnablesperipheralICstocommunicateusingsimplecommunication p p g p hardware Datatransferratesupto100kbits/sand7bitaddressingpossiblein normalmode 3.4Mbits/sand10bitaddressinginfastmode CommondevicescapableofinterfacingtoI2Cbus:
EPROMS Flash and some RAM memory realtime clocks watchdog timers EPROMS,Flash,andsomeRAMmemory,realtimeclocks,watchdogtimers, andmicrocontrollers

I2Cbusstructure
SCL SDA Micro-controller (master) EEPROM (servant) Temp. Sensor (servant) LCD-controller (servant) < 400 pF Addr=0x01 Addr=0x02 Addr=0x03

SDA

SDA

SDA

SDA

SCL Start condition

SCL Sending 0

SCL Sending 1 From Servant

SCL Stop condition From receiver

D C

S T

A R T

A 6

A 5

A 0
Typical read/write cycle

R / w

A C K

D 8

D 7

D 0

A C K

S T

O P

Serialprotocols:CAN
CAN(Controllerareanetwork) Protocolforrealtimeapplications DevelopedbyRobertBoschGmbH O i i ll f Originallyforcommunicationamongcomponentsofcars i i f ApplicationsnowusingCANinclude: elevator controllers copiers telescopes production line elevatorcontrollers,copiers,telescopes,productionline controlsystems,andmedicalinstruments Datatransferratesupto1Mbit/sand11bitaddressing CommondevicesinterfacingwithCAN: 8051compatible8592processorandstandaloneCAN controllers t ll

Parallelprotocols:PCIBus
PCIBus(PeripheralComponentInterconnect)
HighperformancebusoriginatedatIntelintheearly1990s StandardadoptedbyindustryandadministeredbyPCISIG(PCISpecialInterest Group) Interconnectschips,expansionboards,processormemorysubsystems Datatransferratesof127.2to508.6Mbits/sand32bitaddressing
Laterextendedto64bitwhilemaintainingcompatibilitywith32bitschemes

Synchronousbusarchitecture Multiplexeddata/addresslines

Wirelessprotocols:Bluetooth
Bluetooth
New,globalstandardforwirelessconnectivity Basedonlowcost,shortrangeradiolink Connectionestablishedwhenwithin10metersofeachother Nolineofsightrequired
e.g.,Connecttoprinterinanotherroom

Wirelesscommunication
Infrared(IR) ( )
Electronicwavefrequenciesjustbelowvisiblelightspectrum Diodeemitsinfraredlighttogeneratesignal Infrared transistor detects signal conducts when exposed to infrared Infraredtransistordetectssignal,conductswhenexposedtoinfrared light Cheaptobuild Need lineofsight,limitedrange

Radiofrequency(RF)
El t Electromagneticwavefrequenciesinradiospectrum ti f i i di t Analogcircuitryandantennaneededonbothsidesoftransmission Lineofsightnotneeded,transmitterpowerdeterminesrange

Wirelessprotocols:IrDA
IrDA
Protocolsuitethatsupportsshortrangepointtopointinfrareddata transmission Created and promoted by the Infrared Data Association (IrDA) CreatedandpromotedbytheInfraredDataAssociation(IrDA) Datatransferrateof9.6kbpsand4Mbps IrDAhardwaredeployedinnotebookcomputers,printers,PDAs,digital cameras,publicphones,cellphones cameras public phones cell phones Lackofsuitabledrivershasslowedusebyapplications Windows2000/98nowincludesupport BecomingavailableonpopularembeddedOSs

WirelessProtocols:IEEE802.11
IEEE802.11
ProposedstandardforwirelessLANs SpecifiesparametersforPHYandMAClayersofnetwork
PHY layer PHYlayer
physicallayer handlestransmissionofdatabetweennodes p provisionsfordatatransferratesof1or2Mbps p operatesin2.4to2.4835GHzfrequencyband(RF) or300to428,000GHz(IR)

MAClayer
mediumaccesscontrollayer protocolresponsibleformaintainingorderinsharedmedium collisionavoidance/detection

ChapterSummary
Basicprotocolconcepts
Actors,direction,timemultiplexing,controlmethods

Generalpurposeprocessors
PortbasedorbusbasedI/O I/Oaddressing:MemorymappedI/OorStandardI/O / / / Interrupthandling:fixedorvectored Directmemoryaccess

Arbitration
Priorityarbiter(fixed/rotating)ordaisychain

Bushierarchy Advancedcommunication Advanced communication

Parallelvs.serial,wiresvs.wireless,errordetection/correction,layering Serialprotocols:I2C,CAN,FireWire,andUSB;Parallel:PCIandARM. Serial wireless protocols: IrDA Bluetooth and IEEE 802 11 Serialwirelessprotocols:IrDA,Bluetooth,andIEEE802.11.