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DRV632
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DRV632 DirectPath™, 2-VRMS Audio Line Driver With Adjustable Gain

1 Features 3 Description
1• Stereo DirectPath™ Audio Line Driver The DRV632 is a 2-VRMS pop-free stereo line driver
designed to allow the removal of the output dc-
– 2 Vrms Into 10 kΩ With 3.3-V Supply blocking capacitors for reduced component count and
• Low THD+N < 0.01% at 2 Vrms Into 10 kΩ cost. The device is ideal for single-supply electronics
• High SNR, >90 dB where size and cost are critical design parameters.
• 600-Ω Output Load Compliant Designed using TI’s patented DirectPath™
• Differential Input and Single-Ended Output technology, The DRV632 is capable of driving 2 VRMS
into a 10-kΩ load with 3.3-V supply voltage. The
• Adjustable Gain by External Gain-Setting
device has differential inputs and uses external gain-
Resistors setting resistors to support a gain range of ±1 V/V to
• Low DC Offset, <1 mV ±10 V/V, and gain can be configured individually for
• Ground-Referenced Outputs Eliminate DC- each channel. Line outputs have ±8-kV IEC ESD
Blocking Capacitors protection, requiring just a simple resistor-capacitor
ESD protection circuit. The DRV632 has built-in
– Reduce Board Area active-mute control for pop-free audio on/off control.
– Reduce Component Cost The DRV632 has an external undervoltage detector
– Improve THD+N Performance that mutes the output when the power supply is
removed, ensuring a pop-free shutdown.
– No Degradation of Low-Frequency Response
Due to Output Capacitors Using the DRV632 in audio products can reduce
• Short-Circuit Protection component count considerably compared to
traditional methods of generating a 2-VRMS output.
• Click- and Pop-Reduction Circuitry The DRV632 does not require a power supply greater
• External Undervoltage Mute than 3.3 V to generate its 5.6-Vpp output, nor does it
• Active Mute Control for Pop-Free Audio On/Off require a split-rail power supply. The DRV632
Control integrates its own charge pump to generate a
negative supply rail that provides a clean, pop-free
• Space-Saving TSSOP Package ground-biased 2-VRMS output.
2 Applications The DRV632 is available in a 14-pin TSSOP.
• Set-Top Boxes Device Information(1)
• Blu-ray Disc™, DVD Players PART NUMBER PACKAGE BODY SIZE (NOM)
• LCD and PDP TV DRV632 TSSOP (14) 5.00 mm × 4.40 mm
• Mini/Micro Combo Systems (1) For all available packages, see the orderable addendum at
• Sound Cards the end of the datasheet.

• Laptops
Simplified Diagram

± RIGHT
DAC
+

DRV632

+ LEFT
DAC
±

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagram ......................................... 8
2 Applications ........................................................... 1 9.3 Feature Description................................................... 9
3 Description ............................................................. 1 9.4 Device Functional Modes........................................ 11
4 Revision History..................................................... 2 10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
5 Device Comparison Table..................................... 3
10.2 Typical Application ............................................... 12
6 Pin Configuration and Functions ......................... 4
11 Power Supply Recommendations ..................... 14
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4 12 Layout................................................................... 15
12.1 Layout Guidelines ................................................. 15
7.2 ESD Ratings.............................................................. 5
12.2 Layout Example .................................................... 15
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information .................................................. 5 13 Device and Documentation Support ................. 16
7.5 Electrical Characteristics........................................... 5 13.1 Device Support...................................................... 16
7.6 Operating Characteristics.......................................... 6 13.2 Community Resources.......................................... 16
7.7 Typical Characteristics .............................................. 7 13.3 Trademarks ........................................................... 16
13.4 Electrostatic Discharge Caution ............................ 16
8 Parameter Measurement Information .................. 7
13.5 Glossary ................................................................ 16
9 Detailed Description .............................................. 8
9.1 Overview ................................................................... 8 14 Mechanical, Packaging, and Orderable
Information ........................................................... 16

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (August 2015) to Revision C Page

• Added link to DRV632EVM User's Guide............................................................................................................................. 15

Changes from Revision A (June 2013) to Revision B Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Added Device Comparison table. .......................................................................................................................................... 3

Changes from Original (January 2011) to Revision A Page

• Changed description of UVP in PIN FUNCTIONS table ........................................................................................................ 4

• Deleted min value for SNR and DNR in OPERATING CHARACTERISTICS table ............................................................... 6

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5 Device Comparison Table

MINIMUM LOAD
DEVICE INPUT OFFSET (±µV) OUTPUT VOLTAGE (TYP) (VRMS)
IMPEDANCE (Ω)
DRV632 1000 2.4 600
DRV612 1000 2.2 600
1000 (line output) / 8
DRV604 500 2.1
(headphone output)
DRV603 1000 2.05 (VSS = 3.3 V) / 3.01 (VDD = 5 V) 600
DRV602 5000 2.05 (VSS = 3.3 V) / 3.01 (VDD = 5 V) 600
DRV601 8000 2.1 (VSS = 3.3 V) / 2.7 (VDD = 4.5 V) 100
DRV600 8000 2.1 (VSS = 3.3 V) / 2.7 (VDD = 4.5 V) 100

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6 Pin Configuration and Functions

PW Package
14-Pin TSSOP
(Top View)

+INR 1 14 +INL

–INR 2 13 –INL

OUTR 3 12 OUTL
External
GND 4 Under-
Voltage
11 UVP
Detector

Mute 5 10 GND

VSS 6 9 VDD
Charge Pump
CN 7 8 CP

Pin Functions
PIN
TYPE (1) DESCRIPTION
NAME NO.
CN 7 I/O Charge-pump flying capacitor negative connection
CP 8 I/O Charge-pump flying capacitor positive connection
GND 4, 10 P Ground
–INL 13 I Left-channel OPAMP negative input
+INL 14 I Left-channel OPAMP positive input
–INR 2 I Right-channel OPAMP negative input
+INR 1 I Right-channel OPAMP positive input
Mute 5 I Mute, active-low
OUTL 12 O Left-channel OPAMP output
OUTR 3 O Right-channel OPAMP output
UVP 11 I Undervoltage protection, internal pullup; unconnected if UVP function is unused.
VDD 9 P Positive supply
VSS 6 P Supply voltage

(1) I = input, O = output, P = power

7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range
MIN MAX UNIT
Supply voltage, VDD to GND –0.3 4 V
VI Input voltage VSS – 0.3 VDD + 0.3 V
RL Minimum load impedance – line outputs – OUTL, OUTR 600 Ω
Mute to GND, UVP to GND –0.3 VDD + 0.3 V
TJ Maximum operating junction temperature –40 150 °C
Tstg Storage temperature –40 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1500
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±4000 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply voltage DC supply voltage 3 3.3 3.6 V
RL Load impedance 0.6 10 kΩ
VIL Low-level input voltage Mute 40 % of VDD
VIH High-level input voltage Mute 60 % of VDD
TA Operating free-air temperature –40 25 85 °C

7.4 Thermal Information

DRV632
(1)
THERMAL METRIC PW (TSSOP) UNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 130 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49 °C/W
RθJB Junction-to-board thermal resistance 63 °C/W
ψJT Junction-to-top characterization parameter 3.6 °C/W
ψJB Junction-to-board characterization parameter 62 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

7.5 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage VDD = 3.3 V 0.5 1 mV
PSRR Power-supply rejection ratio 80 dB
VOH High-level output voltage VDD = 3.3 V 3.1 V
VOL Low-level output voltage VDD = 3.3 V –3.0 V
5
VUVP_EX External UVP detect voltage 1.25 V
VUVP_EX_HYSTERESIS External UVP detect hysteresis current 5 µA
fCP Charge pump switching frequency 200 300 400 kHz
|IIH| High-level input current, Mute VDD = 3.3 V, VIH = VDD 1 µA
|IIL| Low-level input current, Mute VDD = 3.3 V, VIL = 0 V 1 µA
VDD = 3.3 V, no load, Mute = VDD 5 14 25
IDD Supply current VDD = 3.3 V, no load, Mute = GND, 14 mA
disabled

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7.6 Operating Characteristics

VDD = 3.3 V, RDL = 10 kΩ, RFB = 30 kΩ, RIN = 15 kΩ, TA = 25°C, Charge pump: CP = 1 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Output voltage, outputs in phase THD+N = 1%, VDD = 3.3 V, f = 1 kHz, RL = 10 kΩ 2 2.4 Vrms
THD+N Total harmonic distortion plus noise VO = 2 VRMS, f = 1 kHz 0.002%
SNR Signal-to-noise ratio (1) A-weighted 105 dB
DNR Dynamic range A-weighted 105 dB
VN Noise voltage A-weighted 11 μV
ZO Output Impedance when muted Mute = GND 110 mΩ
Input-to-output attenuation when Mute = GND dB
80
muted
Crosstalk—L to R, R to L VO = 1 Vrms –110 dB
ILIMIT Current limit 25 mA

(1) SNR is calculated relative to 2-Vrms output.

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7.7 Typical Characteristics

VDD = 3.3 V , TA = 25°C, C(PUMP) = C(VSS) = 1 µF , CIN = 2.2 µF, RIN = 15 kΩ, Rfb = 30 kΩ, ROUT = 32 Ω, COUT = 1 nF (unless
otherwise noted)

10 10
Active Filter Active Filter
Gain = 2V/V Gain = 2V/V
RL = 10 kΩ RL = 600Ω
1 1

0.1 0.1
THD+N (%)

THD+N (%)
0.01 0.01

0.001 0.001
100 Hz 100 Hz
1 kHz 1 kHz
10 kHz 10 kHz
0.0001 0.0001
0.1 1 3 0.1 1 3
Output Voltage (V) Output Voltage (V)

Figure 1. Total Harmonic Distortion and Noise vs Output Figure 2. Total Harmonic Distortion and Noise vs Output
Voltage Voltage
10 10
Active Filter Ch1 1 Vrms Active Filter Ch1 1 Vrms
Gain = 2V/V Ch1 2 Vrms Gain = 2V/V Ch1 2 Vrms
RL = 10 kΩ RL = 600 Ω
1 1

0.1 0.1
THD+N (%)

THD+N (%)

0.01 0.01

0.001 0.001

0.0001 0.0001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Figure 3. Total Harmonic Distortion and Noise vs Frequency Figure 4. Total Harmonic Distortion and Noise vs Frequency
0
RL = 10 kΩ Left to Right
VO = 1 Vrms Right to Left
−20 VREF = 1 V

−40
Crosstalk (dBrA)

−60

−80

−100

−120

−140
20 100 1k 10k 20k
Frequency (Hz)

Figure 5. Crosstalk vs Frequency

8 Parameter Measurement Information

All parameters are measured according to the conditions described in Specifications.

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9 Detailed Description

9.1 Overview
Combining the TI's patented DirectPath technology with the built-in click and pop reduction circuit, the DRV632 is
a 2-VRMS pop-free stereo line driver designed to avoid the use of the output DC-blocking capacitors, resulting in
reduced component count and cost. The DRV632 is capable of driving 2-VRMS into a line load of 600 Ω to 10
kΩ with a 3.3-V supply voltage. The use of charge-pump flying, PVSS, and decoupling capacitors ensure the
performance of the amplifier. The device has two channels with differential inputs that require DC input-blocking
capacitors to block the DC portion of the audio source. These allow the DRV632 inputs to be properly biased to
provide maximum performance. The DRV632 allows external gain-setting resistors to support a gain range of ±1
V/V to ±10 V/V. The gain can be configured individually for each channel. Additionally, both channels can be
used as a second-order filter when the removal of out-of-band noise is required. The DRV632 has a built-in
active-mute control for pop-free audio on/off, and avoids the click and pop generation by using external
undervoltage detection. The device does not generate a pop or click when the power supply is removed or
placed.

9.2 Functional Block Diagram

+INL +INR

Line Line
–INL Driver Driver –INR

OUTL OUTR

GND UVP
Click and Pop Short-Circuit
Suppression Protection

Mute GND

VSS Bias VDD

Circuitry

CN CP

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9.3 Feature Description

9.3.1 Line Driver Amplifiers
Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 6 illustrates
the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often
large in value. The line load (typical resistive values of 600 Ω to 10 kΩ) combines with the dc blocking capacitors
to form a high-pass filter. Equation 1 shows the relationship between the load impedance (RL), the capacitor
(CO), and the cutoff frequency (fC).
1
fc =
2p R L CO (1)
CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known.
1
CO =
2p R L f c (2)
If fC is low, the capacitor must then have a large value because the load resistance is small. Large capacitance
values require large package sizes. Large package sizes consume PCB area, stand high above the PCB,
increase cost of assembly, and can reduce the fidelity of the audio output signal.
9 V–12 V Conventional Solution

+ VDD
Mute Circuit
+ Co
+ Output VDD/2
OPAMP
–
GND

Enable

3.3 V DirectPath
DRV632 Solution
VDD
Mute Circuit
+
Output GND
DRV632
–
VSS

Enable

Figure 6. Conventional and DirectPath Line Drivers

The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to
provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the
IC, the device operates in what is effectively a split-supply mode. The output voltages are now centered at zero
volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click and pop
reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors. The bottom block diagram
and waveform of Figure 6 illustrate the ground-referenced line-driver architecture. This is the architecture of the
DRV632.

9.3.2 Charge-Pump Flying Capacitor and PVSS Capacitor

The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The PVSS capacitor must be at least equal to the charge-pump capacitor in order to allow maximum charge
transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical. Capacitor values that are
smaller than 1 μF can be used, but the maximum output voltage may be reduced and the device may not operate
to specifications. If the DRV632 is used in highly noise-sensitive circuits, TI recommends adding a small LC filter
on the VDD connection.

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Feature Description (continued)

9.3.3 Decoupling Capacitors
The DRV632 is a DirectPath line-driver amplifier that requires adequate power supply decoupling to ensure that
the noise and total harmonic distortion (THD) are low. A good, low equivalent-series-resistance (ESR) ceramic
capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this decoupling
capacitor close to the DRV632 is important for the performance of the amplifier. For filtering lower-frequency
noise signals, a 10-μF or greater capacitor placed near the audio power amplifier would also help, but it is not
required in most applications because of the high PSRR of this device.

9.3.4 Gain-Setting Resistor Ranges

The gain-setting resistors, RIN and Rfb, must be chosen so that noise, stability, and input capacitor size of the
DRV632 are kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too
high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different inverting-
input gain settings.

Table 1. Recommended Resistor Values

GAIN INPUT RESISTOR VALUE, RIN FEEDBACK RESISTOR VALUE, Rfb
–1 V/V 10 kΩ 10 kΩ
–1.5 V/V 8.2 kΩ 12 kΩ
–2 V/V 15 kΩ 30 kΩ
–10 V/V 4.7 kΩ 47 kΩ

9.3.5 Input-Blocking Capacitors

DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV632. These capacitors block the dc portion of the audio source and allow the DRV632 inputs to be properly
biased to provide maximum performance.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 3. For this calculation, the capacitance used is the input-blocking capacitor, and the resistance is the
input resistor chosen from Table 1; then the frequency and/or capacitance can be determined when one of the
two values is given.

It is recommended to use electrolytic capacitors or high-voltage-rated capacitors as input blocking capacitors to

ensure minimal variation in capacitance with input voltages. Such variation in capacitance with input voltages is
commonly seen in ceramic capacitors and can increase low-frequency audio distortion.
1 1
fcIN = or CIN =
2p R INCIN 2p fcIN R IN (3)

9.3.6 DRV632 UVP Operation

The shutdown threshold at the UVP pin is 1.25 V. The customer must use a resistor divider to obtain the
shutdown threshold and hysteresis desired for a particular application. The customer-selected thresholds can be
determined as follows:

9.3.7 External Undervoltage Detection

External undervoltage detection can be used to mute/shut down the DRV632 before an input device can
generate a pop.
The shutdown threshold at the UVP pin is 1.25 V. The user selects a resistor divider to obtain the shutdown
threshold and hysteresis for the specific application. The thresholds can be determined as follows:
VUVP = (1.25 – 6 μA × R3) × (R1 + R2) / R2
Hysteresis = 5 μA × R3 × (R1 + R2) / R2
For example, to obtain VUVP = 3.8 V and 1-V hysteresis, use R1 = 3 kΩ, R2 = 1 kΩ, and R3 = 50 kΩ.

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VSUP_MO

R1

R3
UVP

R2

Figure 7. UVP Resistor Divider

9.4 Device Functional Modes

9.4.1 Using the DRV632 as a Second-Order Filter
Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible
with the DRV632, as it can be used like a standard operational amplifier. Several filter topologies can be
implemented, both single-ended and differential. In Figure 8, multi-feedback (MFB) with differential input and
single-ended input are shown.
An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from
the source and lowers the dc gain to 1, helping to reduce the output dc offset to a minimum.
To calculate the component values, use the TI WEBENCH® Filter Designer (www.ti.com/filterdesigner).
Differential Input Inverting Input
R2 R2

C3 R1 R3 C1 C3 R1 R3 C1

–IN –IN

– –
C2 DRV632 C2 DRV632
+ +

+IN

C3 R1 R3 C1

R2

Figure 8. Second-Order Active Low-Pass Filter

The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small-size ac-coupling capacitor. With the proposed values of R1 = 15 kΩ, R2 = 30 kΩ, and R3 = 43 kΩ, a
dynamic range (DYR) of 106 dB can be achieved with a 1-μF input ac-coupling capacitor.

9.4.2 Mute Mode

The DRV632 can be muted using the low-active Mute pin (pin 5). The click-and-pop suppression capacity
ensures that when the mute mode is used, it does not generate an additional click or pop.

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

This typical connection diagram highlights the required external components and system-level connections for
proper operation of the device. This configuration can be realized using the Evaluation Module (EVM) of the
device. This flexible module allows full evaluation of the device in all available modes of operation. Also see the
DRV632 product page for information on ordering the EVM.

10.2 Typical Application

RIGHT LEFT
– INPUT – INPUT
+

+
C3 C3 C3 C3

R1 R1 R1 R1

C2 R2 R2 C2

R3 R3 R3 R3

+
C1 C1
R2 DRV632 R2

+INR +INL

Line Line
–INR Driver Driver –INL

C1 C1

RIGHT OUTPUT OUTR OUTL LEFT OUTPUT

GND UVP
Click and Pop Short-Circuit
Suppression Protection

EN GND
R11

3.3-V Supply R12

VSS Bias VDD
Circuitry
1mF 1mF

CN CP

Linear
Low-Dropout
1mF Regulator
System Supply

10 mF

R1 = 15 kΩ, R2 = 30 kΩ, R3 = 43 kΩ, C1 = 47 pF, C2 = 180 pF

Differential-input, single-ended output, second-order filter

Figure 9. Typical Application Schematic

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Typical Application (continued)

10.2.1 Design Requirements
In this design example, use the parameters listed in Table 2.

Table 2. Design Parameters

KEY PARAMETERS VALUE
Supply Voltage 3.3 V
Supply Current 0.10 A
Load Impedance 600 Ω (minimum)

10.2.2 Detailed Design Procedure

10.2.2.1 Charge-Pump Flying, PVSS and Decoupling Capacitors

To transfer charge during the generation of the negative supply voltage, an 1-µF low equivalent-series-resistance
(ESR) charge-pump flying capacitor is used for this design. Similar 1-µF capacitors are placed in VSS, and as
close as possible to VDD. See Charge-Pump Flying Capacitor and PVSS Capacitor and Decoupling Capacitors
for details.

10.2.2.2 Second-Order Active Low-Pass Filters

With the help of the TI WEBENCH Filter Designer (www.ti.com/filterdesigner), the values of R1 = 15 kΩ, R2 = 30
kΩ, R3 = 43 kΩ, C1 = 47 pF, and C2 = 180 pF are proposed to design a second-order low-pass filter with a
differential-input and a single-ended output. See Using the DRV632 as a Second-Order Filter for details.

10.2.2.3 UVP Resistor Divider

R11 and R12 are placed to design a resistor divider. The shutdown threshold at the UVP pin is 1.25 V. See
External Undervoltage Detection for details.

10.2.3 Application Curves

10 10
Active Filter Active Filter
Gain = 2V/V Gain = 2V/V
RL = 10 kΩ RL = 600Ω
1 1

0.1 0.1
THD+N (%)

THD+N (%)

0.01 0.01

0.001 0.001
100 Hz 100 Hz
1 kHz 1 kHz
10 kHz 10 kHz
0.0001 0.0001
0.1 1 3 0.1 1 3
Output Voltage (V) Output Voltage (V)

Figure 10. Total Harmonic Distortion and Noise vs Output Figure 11. Total Harmonic Distortion and Noise vs Output
Voltage Voltage

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10 10
Active Filter Ch1 1 Vrms Active Filter Ch1 1 Vrms
Gain = 2V/V Ch1 2 Vrms Gain = 2V/V Ch1 2 Vrms
RL = 10 kΩ RL = 600 Ω
1 1

0.1 0.1
THD+N (%)

THD+N (%)
0.01 0.01

0.001 0.001

0.0001 0.0001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

Figure 12. Total Harmonic Distortion and Noise vs Figure 13. Total Harmonic Distortion and Noise vs
Frequency Frequency

0
RL = 10 kΩ Left to Right
VO = 1 Vrms Right to Left
−20 VREF = 1 V

−40
Crosstalk (dBrA)

−60

−80

−100

−120

−140
20 100 1k 10k 20k
Frequency (Hz)

Figure 14. Crosstalk vs Frequency

11 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 3 V and 3.6 V. This input supply
must be well-regulated. If the input supply is located more than a few inches from the DRV632 device, additional
bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a
value of 47 µF is a typical choice.
Placing a decoupling capacitor close to the DRV632 improves the performance of the line-driver amplifier. An low
equivalent-series-resistance (ESR) ceramic capacitor with a value of 1 µF is a typical choice.
If the DRV632 is used in highly noise-sensitive circuits, TI recommends adding a small LC filter on the VDD
connection.

14 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated

Product Folder Links: DRV632

 DRV632
www.ti.com SLOS681C – JANUARY 2011 – REVISED AUGUST 2019

12 Layout

12.1 Layout Guidelines

12.1.1 Gain-Setting Resistors
The gain-setting resistors, RIN and Rfb, must be placed close to pins 13 and 17, respectively, to minimize
capacitive loading on these input pins and to ensure maximum stability of the DRV632. For the recommended
PCB layout, see the DRV632EVM User's Guide.

12.2 Layout Example

LIN(-) LOUT

Decoupling
UVP capacitor as close
Circuit as possible to the
device

LIN(+)
Power Ground
RIN(+)

PVSS capacitor
as close as
possible to the
MUTE device

RIN(-) ROUT

Pad to Ground Plane Top Layer Signal Traces

Connection to VDD Top Layer Ground Plane
Via to Ground Layer

Figure 15. DRV632 Layout Example

Copyright © 2011–2019, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: DRV632
DRV632
SLOS681C – JANUARY 2011 – REVISED AUGUST 2019 www.ti.com

13 Device and Documentation Support

13.1 Device Support

13.1.1 Development Support

For the DRV632EVM and Gerber files, go to www.ti.com/tool/DRV632EVM.

13.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.3 Trademarks
DirectPath, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

16 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated

Product Folder Links: DRV632

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DRV632PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV632

DRV632PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV632

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV632PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV632PWR TSSOP PW 14 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
DRV632PW PW TSSOP 14 90 530 10.2 3600 3.5

Pack Materials-Page 3
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