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Verilog scalar and vector
1. Scalar and Vector
2. Bit-selects
3. Part-selects
4. Common Errors
Verilog needs to represent individual bits as well as groups of
bits. For example, a single bit sequential element is a flip-flop.
However a 16-bit sequential element is a register that can hold
16 bits. For this purpose, Verilog has scalar and vector nets and
variables.
Scalar and Vector
A net or reg declaration without a range specification is
considered 1-bit wide and is a scalar. If a range is specified,
then the net or reg becomes a multibit entity known as a
vector.
1 wire o_nor; // single bit scalar
2 wire [7:0] o_flop; // 8-bit vector net
3 reg parity; // single bit scalar
4 reg [31:0] addr; // 32 bit vector var
The range gives the ability to address individual bits in a vector.
The most significant bit of the vector should be specified as the
left hand value in the range while the least significant bit of the
vector should be specified on the right.
1 wire [msb:lsb] name;
2 integer my_msb;
3
4 wire [15:0] priority; // msb = 15, ls
5 wire [my_msb: 2] prior; // illegal
A 16 bit wide net called priority will be created in the example
above. Note that the msb and lsb should be a constant
expression and cannot be substituted by a variable. But they can
be any integer value - positive, negative or zero; and the lsb
value can be greater than, equal to or less than msb value.
Bit-selects
Any bit in a vectored variable can be individually selected and
assigned a new value as shown below. This is called as a bit-
select. If the bit-select is out of bounds or the bit-select is x or
z, then the value returned will be x.
1 reg [7:0] addr; // 8-bit reg variabl
2
3 addr [0] = 1; // assign 1 to bit 0
4 addr [3] = 0; // assign 0 to bit 3
5 addr [8] = 1; // illegal : bit8 d
Part-selects
A range of contiguous bits can be selected and is known as a
part-select. There are two types of part-selects, one with a
constant part-select and another with an indexed part-select.
1 reg [31:0] addr;
2
3 addr [23:16] = 8'h23; // bits 23 to 16 wi
Having a variable part-select allows it to be used effectively in
loops to select parts of the vector. Although the starting bit can
be varied, the width has to be constant.
[<start_bit> +: <width>] // part-select increme
[<start_bit> -: <width>] // part-select decreme
1 module des;
2 reg [31:0] data;
3 int i;
4
5 initial begin
6 data = 32'hFACE_CAFE;
7 for (i = 0; i < 4; i++) begin
8 $display ("data[8*%0d +: 8] = 0x%0h", i, da
9 end
10
11 $display ("data[7:0] = 0x%0h", data[7:0]);
12 $display ("data[15:8] = 0x%0h", data[15:8]);
13 $display ("data[23:16] = 0x%0h", data[23:16])
14 $display ("data[31:24] = 0x%0h", data[31:24])
15 end
16
17 endmodule
Simulation Log
ncsim> run
data[8*0 +: 8] = 0xfe // ~ data
data[8*1 +: 8] = 0xca // ~ data
data[8*2 +: 8] = 0xce // ~ data
data[8*3 +: 8] = 0xfa // ~ data
data[7:0] = 0xfe
data[15:8] = 0xca
data[23:16] = 0xce
data[31:24] = 0xfa
ncsim: *W,RNQUIE: Simulation is complete.
Common Errors
1 module tb;
2 reg [15:0] data;
3
4 initial begin
5 $display ("data[0:9] = 0x%0h", data[0:9]);
6 end
7 endmodule
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