Counters in Digital Logic

A Counter is a device which stores (and sometimes displays)

the number of times a particular event or process has occurred,
often in relationship to a clock signal. Counters are used in
digital electronics for counting purpose, they can count speci c
event happening in the circuit. For example, in UP counter a
counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on
our design like any random sequence 0,1,3,2… .They can also
be designed with the help of ip ops. They are used as
frequency dividers where the frequency of given pulse
waveform is divided. Counters are sequential circuit that count
the number of pulses can be either in binary code or BCD form.
The main properties of a counter are timing , sequencing , and
counting. Counter works in two modes
Up counter

Down counter
Counter Classi cation

Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter
1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only rst
ip op is driven by main clock and the clock input of rest of the
following ip op is driven by output of previous ip ops. We
can understand it by following diagram-
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 It is evident from timing diagram that Q0 is changing as soon as
the rising edge of clock pulse is encountered, Q1 is changing
when rising edge of Q0 is encountered(because Q0 is like clock
pulse for second ip op) and so on. In this way ripples are
generated through Q0,Q1,Q2,Q3 hence it is also called
RIPPLE counter and serial counter. A ripple counter is a
cascaded arrangement of ip ops where the output of one ip
op drives the clock input of the following ip op
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2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one
global clock which drives each ip op so output changes in
parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency
than asynchronous counter as it does not have cumulative
delay because of same clock is given to each ip op. It is also
called as parallel counter.

Synchronous counter circuit

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 Timing diagram synchronous counter
From circuit diagram we see that Q0 bit gives response to each
falling edge of clock while Q1 is dependent on Q0, Q2 is
dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.

Decade Counter
A decade counter counts ten different states and then reset to
its initial states. A simple decade counter will count from 0 to 9
but we can also make the decade counters which can go
through any ten states between 0 to 15(for 4 bit counter).

Clock pulse Q3 Q2 Q1 Q0
 0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

Truth table for simple decade counter

 Decade counter circuit diagram
We see from circuit diagram that we have used nand gate for
Q3 and Q1 and feeding this to clear input line because binary
representation of 10 is—
1010
And we see Q3 and Q1 are 1 here, if we give NAND of these
two bits to clear input then counter will be clear at 10 and again
start from beginning.
Important point: Number of ip ops used in counter are
always greater than equal to (log2 n) where n=number of
states in counter.

Some previous years gate questions on Counters

Q1. Consider the partial implementation of a 2-bit counter

using T ip- ops following the sequence 0-2-3-1-0, as
shown below
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To complete the circuit, the input X should be
(A) Q2?
(B) Q2 + Q1
(C) (Q1 ? Q2)’
(D) Q1 ? Q2
(GATE-
CS-2004)
Solution:
From circuit we see
T1=XQ1’+X’Q1—-(1)
AND
T2=(Q2 ? Q1)’—-(2)

AND DESIRED OUTPUT IS 00->10->11->01->00

SO X SHOULD BE Q1Q2’+Q1’Q2 SATISFYING 1 AND 2.
SO ANS IS (D) PART.
Q2. The control signal functions of a 4-bit binary counter
are given below (where X is “don’t care”)
The counter is connected as follows:

Assume that the counter and gate delays are negligible. If

the counter starts at 0, then it cycles through the following
sequence:
(A) 0,3,4
(B) 0,3,4,5
(C) 0,1,2,3,4
 (D)
0,1,2,3,4,5
(GATE-CS-2007)
Solution:
Initially A1 A2 A3 A4 =0000
Clr=A1 and A3
So when A1 and A3 both are 1 it again goes to 0000
Hence 0000(init.) -> 0001(A1 and A3=0)->0010 (A1 and A3=0)
-> 0011(A1 and A3=0) -> 0100 (A1 and A3=1)[ clear condition
satis ed] ->0000(init.) so it goes through 0->1->2->3->4
Ans is (C) part.

Ripple Counter in Digital Logic

Counters play a crucial role in digital logic circuits, enabling
tasks such as clock frequency division and sequencing. This
article explores the concept of ripple counters, a type of
asynchronous counter, their operation, advantages, and
disadvantages in digital logic design.

What is a Counter?
Counter is basically used to count the number of clock pulses
applied to a ip- op. It can also be used for Frequency divider,
time measurement, frequency measurement, distance
measurement, and also for generating square waveforms. In
this, the ip- ops are asynchronous counters and are supplied
with different clock signals, there may be a delay in producing
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 output. Also, a few numbers of logic gates are needed to design
asynchronous counters. So they are elementary in design and
also are less expensive.

What is a Ripple counter?

Ripple counter is a cascaded arrangement of ip- ops where
the output of one ip- op drives the clock input of the following
ip- op. The number of ip ops in the cascaded arrangement
depends upon the number of different logic states that it goes
through before it repeats the sequence a parameter known as
the modulus of the counter. A n-bit ripple counter can count up
to 2n states. It is also known as MOD n counter. It is known as
ripple counter because of the way the clock pulse ripples its
way through the ip- ops. Some of the features of ripple
counter are:
•
It is an asynchronous counter.
•
Different ip- ops are used with a different clock pulse.
•
All the ip- ops are used in toggle mode.
•
Only one ip- op is applied with an external clock pulse
and another ip- op clock is obtained from the output of
the previous ip- op.
• The ip- op applied with an external clock pulse act as
LSB (Least Signi cant Bit) in the counting sequence.
A counter may be an up counter that counts upwards or can be
a down counter that counts downwards or can do both i.e.count
up as well as count downwards depending on the input control.
The sequence of counting usually gets repeated after a limit.
When counting up, for the n-bit counter the count sequence
goes from 000, 001, 010, … 110, 111, 000, 001, … etc. When
counting down the count sequence goes in the opposite
manner: 111, 110, … 010, 001, 000, 111, 110, … etc.

A 3-bit Ripple counter using a JK ip- op is as follows:

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 In the circuit shown in the above gure, Q0(LSB) will toggle for
every clock pulse because JK ip- op works in toggle mode
when both J and K are applied 1, 1, or high input. The following
counter will toggle when the previous one changes from 1 to 0.

Truth Table is as follows:

The 3-bit ripple counter used in the circuit above has eight
different states, each one of which represents a count value.
Similarly, a counter having n ip- ops can have a maximum of 2
to the power n states. The number of states that a counter owns
is known as its mod (modulo) number. Hence a 3-bit counter is
a mod-8 counter. A mod-n counter may also be described as a
divide-by-n counter. This is because the most signi cant ip- op
(the furthest ip- op from the original clock pulse) produces one
pulse for every n pulses at the clock input of the least signi cant
ip- op (the one triggers by the clock pulse). Thus, the above
counter is an example of a divide-by-4 counter.
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 Timing diagram

Let us assume that the clock is negative edge triggered so the

above the counter will act as an up counter because the clock is
negative edge triggered and output is taken from Q.

Counters are used very frequently to divide clock frequencies

and their uses mainly involve digital clocks and in multiplexing.
The widely known example of the counter is parallel to serial
data conversion logic.

Advantages of Ripple Counter in Digital

Logic
• Can be easily designed by T ip- op or D ip- op.
• Can be used in low speed circuits & divide by n-counters.
• Used as Truncated counters to design any mode number
counters (i.e. Mod 4, Mod 3)
Disadvantages of Ripple Counter in
Digital Logic
• Extra ip- op are needed to do resynchronization.
• To count the sequence of truncated counters, additional
feedback logic is needed.
• Propagation delay of asynchronous counters is very large,
while counting the large number of bits.
• Counting errors may occur due to propagation delay for
high clock frequencies.
Conclusion
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 In conclusion, ripple counters are valuable in digital logic
design, allowing for straightforward frequency division and
sequence generation. They are easily constructed using T or D
ip- ops and have applications in various scenarios, despite
their limitations such as propagation delay and the need for
additional logic for truncated counting. Understanding the
principles of ripple counters is essential for digital circuit
designers.

Frequently Asked Questions

Q.1: How do you overcome the limitations of
propagation delay in ripple counters?

Answer:
To overcome propagation delay issues in ripple counters, one
can opt for synchronous counters or other counter designs that
minimize delay. Synchronous counters use a common clock
signal to trigger all ip- ops simultaneously, reducing delay
concerns.
Q.2: What are some common alternatives to ripple
counters in digital logic design?

Answer:
Common alternatives to ripple counters include synchronous
counters, Johnson counters, and decade counters. These
counters offer improved performance and reduced propagation
delay in various applications.

Ring Counter in Digital Logic

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A ring counter is a typical application of the Shift register. The
ring counter is almost the same as the shift counter. The only
change is that the output of the last ip- op is connected to the
input of the rst ip- op in the case of the ring counter but in the
case of the shift register it is taken as output. Except for this, all
the other things are the same.
No. of states in Ring counter = No. of flip-flop
used
So, for designing a 4-bit Ring counter we need 4 ip- ops.

In this diagram, we can see that the clock pulse (CLK) is

applied to all the ip- ops simultaneously. Therefore, it is a
Synchronous Counter. Also, here we use Overriding input (ORI)
for each ip- op. Preset (PR) and Clear (CLR) are used as ORI.
When PR is 0, then the output is 1. And when CLR is 0, then
the output is 0. Both PR and CLR are active low signal that
always works in value 0.

PR = 0, Q = 1
CLR = 0, Q = 0
These two values are always xed. They are independent of the
value of input D and the Clock pulse (CLK). Working – Here,
ORI is connected to Preset (PR) in FF-0 and it is connected to
Clear (CLR) in FF-1, FF-2, and FF-3. Thus, output Q = 1 is
generated at FF-0, and the rest of the ip- op generates output
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Q = 0. This output Q = 1 at FF-0 is known as Pre-set 1 which is
used to form the ring in the Ring Counter.

This Preseted 1 is generated by making ORI low and that time

Clock (CLK) becomes don’t care. After that ORI is made to high
and apply low clock pulse signal as the Clock (CLK) is negative
edge triggered. After that, at each clock pulse, the preseted 1 is
shifted to the next ip- op and thus forms a Ring. From the
above table, we can say that there are 4 states in a 4-bit Ring
Counter.

4 states are:
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
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 In this way can design a 4-bit Ring Counter using four D ip-
ops.
Types of Ring Counter: There are two types of Ring Counter:
1. Straight Ring Counter: It is also known as One hot
Counter. In this counter, the output of the last ip- op is
connected to the input of the rst ip- op. The main point
of this Counter is that it circulates a single one (or zero) bit
around the ring.

2. Here, we use Preset (PR) in the rst ip- op and Clock

(CLK) for the last three ip- ops.
3. Twisted Ring Counter – It is also known as a switch-tail
ring counter, walking ring counter, or Johnson counter. It
connects the complement of the output of the last shift
register to the input of the rst register and circulates a
stream of ones followed by zeros around the ring.
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 4. Here, we use Clock (CLK) for all the ip- ops. In the
Twisted Ring Counter, the number of states = 2 X the
number of ip- ops.

General Purpose Registers

A register serves as a quick memory for accepting, storing, and
sending data and instructions that the CPU will need right away.
A register is a collection of ip- ops, Single bit digital data is
stored using ip- ops. By combining many ip- ops, the storage
capacity can be extended to accommodate a huge number of
bits. We must utilize an n-bit register with n ip ops if we wish
to store an n-bit word.
The gates govern the ow of information, i.e., when and how
the information is sent into a register, whereas the ip- ops
store the binary information.

Working of Registers:
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When we provide the system with input, that input is stored in
registers, and when the system returns results after processing,
those results are also drawn from the registers. so that the CPU
can use them to process the data that the user provides.
Registers are performed based on three operations:

• Fetch: The Fetch Operation is used to retrieve user-

provided instructions that have been stored in the main
memory. Registers are used to fetch these instructions.
• Decode: The Decode Operation is used to interpret the
Instructions, which means that the CPU will determine
which Operation has to be carried out on the Instructions
after the Instructions have been decoded.
• Execute: The CPU manages the Execute Operation. The
results that the CPU generates are then stored in the
memory before being presented on the user screen.
Types of Registers:
• Status and control registers.
• General-purpose data registers.
• Special purpose register.
Status and Control Register:
Status and Control registers report and allow modi cation of the
state of the processor and of the program being executed.
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General-Purpose Data Registers:
General purpose registers are extra registers that are present in
the CPU and are utilized anytime data or a memory location is
required. These registers are used for storing operands and
pointers. These are mainly used for holding the following:
• Operands for logical and arithmetic operations
• Operands for address calculation
• Memory pointers
There are 3 types of General-purpose data registers they are:
Data registers: Data registers consists of four 32-bit data
registers, which are used for arithmetic, logical and other
operations. Data registers are again classi ed into 4 types they
are:
• AX: This is known as the accumulator register. Its 16 bits
are split into two 8-bit registers, AH and AL, allowing it to
execute 8-bit instructions as well. In 8086 microprocessors,
it is used in the arithmetic, logic, and data transfer
instructions. One of the numbers involved in manipulation
and division must be in AX or AL.
• BX: This is called a Base register. It has 16 bits and is split
into two registers with 8 bits each, BH and BL. An address
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pointer for indirect addressing that is based, based
indexed, or register-based.
• CX: This is known as the Count register. Its 16 bits are split
into two 8-bit registers, CH and CL, allowing it to execute
8-bit instructions as well. This acts as a counter for loops. It
facilitates the development of program loops. Shift/rotate
instructions and string manipulation both allow the use of
the count register as a counter.
• DX: This is known as the Data register. Its 16 bits are split
into two 8-bit registers, DH and DL so that it can execute 8-
bit instructions as well. In I/O operations, the data register
can be used as a port number. It is also applied to division
and multiplication.
Pointer registers: The pointer registers consist of 16-bit left
sections (SP, and BP) and 32-bit ESP and EBP registers.
• SP: This is known as a Stack pointer used to point the
program stack. For accessing the stack segment, it works
with SS. It has a 16-bit size. It designates the item at the
top of the stack. The stack pointer will be (FFFE)H if the
stack is empty. The stack segment is relative to its offset
address.
• BP: This is known as the Base pointer used to point data
in the stack segments. We can utilize BP to access data in
the other segments, unlike SP. It has a 16-bit size. It mostly
serves as a way to access parameters given via the stack.
The stack segment is relative to its offset address.
Index registers: The 16-bit rightmost bits of the 32-bit ESI and
EDI index registers. SI and DI are sometimes employed in
addition and sometimes in subtraction as well as for indexed
addressing.
• SI: This source index register is used to identify memory
addresses in the data segment that DS is addressing.
Therefore, it is simple to access successive memory
 locations when we increment the contents of SI. It has a
16-bit size. Relative to the data segment, it has an offset.
• DI: The function of this destination index register is
identical to that of SI. String operations are a subclass of
instructions that employ DI to access the memory
addresses speci ed by ES. It is generally used as a
Destination index for string operations.
Special Purpose Registers:
To store machine state data and change state con guration,
special purpose registers are employed. In other words, it is
also de ned as the CPU has a number of registers that are
used to carry out instruction execution these registers are called
special purpose registers. Special purpose registers are of 8
types they are cs, ds, ss, es, fs, and gs registers come under
segment registers. These registers hold up to six segment
selectors.
• CS (Code Segment register): A 16-bit register called a
code segment (CS) holds the address of a 64 KB section
together with CPU instructions. All accesses to instructions
referred to by an instruction pointer (IP) register are made
by the CPU using the CS segment. Direct changes to CS
registration are not possible. When using the far jump, far
call, and far return instructions, the CS register is
automatically updated.
• DS (Data Segment register): A 64KB segment of
program data is addressed using a 16-bit register called
the data segment. The processor by default believes that
the data segment contains all information referred to by the
general registers (AX, BX, CX, and DX) and index registers
(SI, DI). POP and LDS commands can be used to directly
alter the DS register.
• SS (Stack Segment register): A 16-bit register called a
stack segment holds the address of a 64KB segment with
a software stack. The CPU by default believes that the
stack segment contains all information referred to by the
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 stack pointer (SP) and base pointer (BP) registers. POP
instruction allows for direct modi cation of the SS register.
• ES (Extra Segment register): A 16-bit register called
extra segment holds the address of a 64KB segment,
typically holding program data. In string manipulation
instructions, the CPU defaults to assuming that the DI
register refers to the ES segment. POP and LES
commands can be used to directly update the ES register.
• FS (File Segment register): FS registers don’t have a
purpose that is predetermined by the CPU; instead, the OS
that runs them gives them a purpose. On Windows
processes, FS is used to point to the thread information
block (TIB).
• GS (Graphics Segment register): The GS register is
used in Windows 64-bit to point to operating system-
de ned structures. OS kernels frequently use GS to
access thread-speci c memory. The GS register is
employed by Windows to control thread-speci c memory.
In order to access CPU-speci c memory, the Linux kernel
employs GS. A pointer to a thread local storage, or TLS, is
frequently used as GS.
• IP (Instruction Pointer register): The registers CS and
IP are used by the 8086 to access instructions. The
segment number of the following instruction is stored in the
CS register, while the offset is stored in the IP register.
Every time an instruction is executed, IP is modi ed to
point to the upcoming instruction. The IP cannot be directly
modi ed by an instruction, unlike other registers; an
instruction may not have the IP as its operand.
• Flag register: The status register for an x86 CPU houses
its current state, and it is called the FLAGS register. The
ag bits’ size and signi cance vary depending on the
architecture. It often includes information about current
CPU operation limitations as well as the outcome of
mathematical operations. Some of these limitations might
forbid the execution of a particular class of “privileged”
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 instructions and stop some interrupts from triggering. Other
status ags may override memory mapping and specify the
response the CPU should have in the event of an
arithmetic overrun.

Shift Registers in Digital Logic

Pre-Requisite: Flip-Flops
Flip ops can be used to store a single bit of binary data (1 or
0). However, in order to store multiple bits of data, we need
multiple ip- ops. N ip ops are to be connected in order to
store n bits of data. A Register is a device that is used to store
such information. It is a group of ip- ops connected in series
used to store multiple bits of data. The information stored within
these registers can be transferred with the help of shift
registers.

Shift Register is a group of ip ops used to store multiple bits

of data. The bits stored in such registers can be made to move
within the registers and in/out of the registers by applying clock
pulses. An n-bit shift register can be formed by connecting n
ip- ops where each ip- op stores a single bit of data. The
registers which will shift the bits to the left are called “Shift left
registers”. The registers which will shift the bits to the right are
called “Shift right registers”. Shift registers are basically of
following types.

Types of Shift Registers

• Serial In Serial Out shift register
• Serial In parallel Out shift register
• Parallel In Serial Out shift register
• Parallel In parallel Out shift register
• Bidirectional Shift Register
• Universal Shift Register
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 • Shift Register Counter
Serial-In Serial-Out Shift Register (SISO)

The shift register, which allows serial input (one bit after the
other through a single data line) and produces a serial output is
known as a Serial-In Serial-Out shift register. Since there is only
one output, the data leaves the shift register one bit at a time in
a serial pattern, thus the name Serial-In Serial-Out Shift
Register. The logic circuit given below shows a serial-in serial-
out shift register. The circuit consists of four D ip- ops which
are connected in a serial manner. All these ip- ops are
synchronous with each other since the same clock signal is
applied to each ip- op.

Serial-In Serial-Out Shift Register (SISO)

The above circuit is an example of a shift right register, taking

the serial data input from the left side of the ip op. The main
use of a SISO is to act as a delay element.
Serial-In Parallel-Out Shift Register (SIPO)

The shift register, which allows serial input (one bit after the
other through a single data line) and produces a parallel output
is known as the Serial-In Parallel-Out shift register. The logic
circuit given below shows a serial-in-parallel-out shift register.
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 The circuit consists of four D ip- ops which are connected. The
clear (CLR) signal is connected in addition to the clock signal to
all 4 ip ops in order to RESET them. The output of the rst
ip- op is connected to the input of the next ip op and so on.
All these ip- ops are synchronous with each other since the
same clock signal is applied to each ip- op.

Serial-In Parallel-Out shift Register (SIPO)

The above circuit is an example of a shift right register, taking

the serial data input from the left side of the ip- op and
producing a parallel output. They are used in communication
lines where demultiplexing of a data line into several parallel
lines is required because the main use of the SIPO register is to
convert serial data into parallel data.

Parallel-In Serial-Out Shift Register (PISO)

The shift register, which allows parallel input (data is given

separately to each ip op and in a simultaneous manner) and
produces a serial output is known as a Parallel-In Serial-Out
shift register. The logic circuit given below shows a parallel-in-
serial-out shift register. The circuit consists of four D ip- ops
which are connected. The clock input is directly connected to all
the ip- ops but the input data is connected individually to each
ip- op through a multiplexer at the input of every ip- op. The
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 output of the previous ip- op and parallel data input are
connected to the input of the MUX and the output of MUX is
connected to the next ip- op. All these ip- ops are
synchronous with each other since the same clock signal is
applied to each ip- op.

Parallel-In Serial-Out Shift Register (PISO)

A Parallel in Serial Out (PISO) shift register is used to convert

parallel data to serial data.
Parallel-In Parallel-Out Shift Register (PIPO)

The shift register, which allows parallel input (data is given

separately to each ip op and in a simultaneous manner) and
also produces a parallel output is known as Parallel-In parallel-
Out shift register. The logic circuit given below shows a parallel-
in-parallel-out shift register. The circuit consists of four D ip-
ops which are connected. The clear (CLR) signal and clock
signals are connected to all 4 ip- ops. In this type of register,
there are no interconnections between the individual ip- ops
since no serial shifting of the data is required. Data is given as
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input separately for each ip op and in the same way, output is
also collected individually from each ip op.

Parallel-In Parallel-Out Shift Register (PIPO)

A Parallel in Parallel out (PIPO) shift register is used as a

temporary storage device and like SISO Shift register it acts as
a delay element.
Bidirectional Shift Register

If we shift a binary number to the left by one position, it is

equivalent to multiplying the number by 2 and if we shift a
binary number to the right by one position, it is equivalent to
dividing the number by 2. To perform these operations we need
a register which can shift the data in either direction.
Bidirectional shift registers are the registers that are capable of
shifting the data either right or left depending on the mode
selected. If the mode selected is 1(high), the data will be shifted
toward the right direction and if the mode selected is 0(low), the
data will be shifted towards the left direction. The logic circuit
given below shows a Bidirectional shift register. The circuit
consists of four D ip- ops which are connected. The input data
is connected at two ends of the circuit and depending on the
mode selected only one gate is in the active state.
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 Bidirectional Shift Register

Universal Shift Register

Universal Shift Register is a type of register that contains the

both right shift and the left shift. It has also parallel load
capabilities. Generally, these types of registers are taken as
memory elements in computers. But, the problem with this type
of register is that it shifts only in one direction. In simple words,
you mean that the universal shift register is a combination of the
bidirectional shift register and the unidirectional shift
register.
 Universal Shift Register

N-bit universal shift register consists of ip- ops and

multiplexers. Both are N in size. In this, all the n multiplexers
share the same select lines and this select input selects the
suitable input for ip- ops.
Shift Register Counter

Shift Register Counters are the shift registers in which the

outputs are connected back to the inputs in order to produce
particular sequences. There are basically two types:
• Ring Counter
• Johnson Counter
Ring Counter
A ring counter is basically a shift register counter in which the
output of the rst ip- op is connected to the next ip- op and
so on and the output of the last ip- op is again fed back to the
input of the rst ip- op, thus the name ring counter. The data
pattern within the shift register will circulate as long as clock
fi
fi
fl
fl
fl
fl
fl
fl
fl
fl
fl
fl
fl
fl
pulses are applied. The logic circuit given below shows a Ring
Counter.

Ring Counter Truth Table

The circuit consists of four D ip- ops which are connected.

Since the circuit consists of four ip- ops the data pattern will
repeat after every four clock pulses as shown in the truth table.
A Ring counter is generally used because it is self-decoding. No
extra decoding circuit is needed to determine what state the
counter is in.

Ring Counter

Johnson Counter
fl
fl
fl
fl
A Johnson counter is basically a shift register counter in which
the output of the rst ip op is connected to the next ip op
and so on and the inverted output of the last ip op is again
fed back to the input of the rst ip op. They are also known as
twisted ring counters. The logic circuit given below shows a
Johnson Counter. The circuit consists of four D ip- ops which
are connected.

Johnson Counter Truth Table

An n-stage Johnson counter yields a count sequence of 2n

different states, thus also known as a mod-2n counter. Since
the circuit consists of four ip- ops the data pattern will repeat
every eight clock pulses as shown in the truth table. The main
advantage of the Johnson counter is that it only needs n
number of ip- ops compared to the ring counter to circulate a
given data to generate a sequence of 2n states.
fl
fl
fi
fl
fl
fl
fi
fl
fl
fl
fl
fl
fl
fl
fl
fl
 Johnson Counter

Applications of Shift Registers

• The shift registers are used for temporary data storage.
• The shift registers are also used for data transfer and data
manipulation.
• The serial-in serial-out and parallel-in parallel-out shift
registers are used to produce time delay to digital circuits.
• The serial-in parallel-out shift register is used to convert
serial data into parallel data thus they are used in
communication lines where demultiplexing of a data line
into several parallel lines is required.
• A Parallel in Serial out shift register is used to convert
parallel data to serial data.