Programming Microprocessor –

Instruction Set Architecture II

CS2053 Computer Architecture
Computer Science & Engineering
University of Moratuwa

Sulochana Sooriyaarachchi
Chathuranga Hettiarachchi

Slides adopted from Dr.Dilum Bandara

Encoding Instructions
Various instruction types
Limited word size for registers, addresses, and
instructions
■ Consider 32bit words in RV32I
■ All the instructions are 32bits
■ Example : If we need to load an immediate value to
32-bit register, how to fit all opcode and operands
within 32-bit instruction?
Work with small numbers
Make compromises

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Instruction Formats(Types)

Fields
■ Opcode : 7bits
■ funct 3 : 3 bit function
■ funct 7 : 7 bit function
■ rs1, rs2 : two source registers (5 bits each)
■ rd : destination register (5 bits)

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Instruction Formats (6 Types)
R-Format: instructions using 3 register inputs
– add, xor, mul —arithmetic/logical ops
I-Format: instructions with immediates, loads
– addi, lw, jalr, slli

S-Format: store instructions: sw, sb

■ SB-Format: branch instructions: beq, bge
U-Format: instructions with upper immediates
– lui, auipc —upper immediate is 20-bits
■ UJ-Format: jump instructions: jal

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 Instruction Format-Register Type

(Register Type)

For the complete standard specifications:

https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf 5
Instruction Format-Immediate Type

(Immediate Type)

Discuss
later
today
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Upper Immediate Instructions

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Instruction Format-Upper Immediate

Load Upper Immediate (lui)

lui t1,0x70070
Fill up the upper 20 bits of destination register with immediate value
Add Upper Immediate value and Program Counter (auipc)
auipc a0,0x2
Fill the upper 20 bits of destination register with immediate value
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U Type Instruction Example
RISCV Instruction: lui x5,0x10

Imm [31:12] rd opcode

0 1 1 0 1 1 1
0 1 0 0 0 0 0 0 1 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 1 0 1 1 1
0 0 0 1 0 2 B 7
Machine Instruction: 0x000102B7

Result ?? Rd = imm << 12

We can work with 20bit
Register x5 (t0) = 0x0010 <<12 immediate values!
= 0x00010000

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RISC-V U-type instructions usage
Some instructions are difficult to get done with a single instruction.
Example:
Load immediate value 0x700707FF (or any 32 bits long number) to
x6 register

Since we must encode the instruction opcode in 32 bits as well, it is

impossible to do in a single instruction.
Split the 32bit value to two parts. [31:12][11:0]

Need two instruction to do this:

lui x6, 0x70070 (U type instruction) Upper Part Lower Part
addi x6, 0x7FF (20 bits) (12 bits)

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Example 1:Load 0x000707FF to t0
Split to two numbers 0x00070000 + 0x000007FF
■ 0x0070 to t0 upper bits
lui t0,0x70
0x10 = 0b01110000 << 12
t0 = 0b 0000 0000 0000 0111 0000 0000 0000 0000
0x7FF = 0b 0000 0000 0000 0000 0000 0111 1111 1111
addi t0,t0, 0x7FF
= 0b 0000 0000 0000 0111 0000 0111 1111 1111
= 0x000707FF
So , we loaded 0x000707FF to t0 32bit register

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Example 2:Load 0x0000FFFF to t0
0x7FF is the max value for addi instruction
Split to two numbers 0x00010000 + (-1)
■ 0x0010 to t0 upper bits
lui t0,0x10
0x10 = 0b00010000 << 12
t0 = 0b 0000 0000 0000 0001 0000 0000 0000 0000
-1 = 0b 1111 1111 1111 1111 1111 1111 1111 1111
addi t0,t0, -1
= 0b 0000 0000 0000 0000 1111 1111 1111 1111
= 0x0000FFFF
So , we loaded 0x0000FFFF to t0 32bit register

How about loading 0x0000F800 ???

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Meh..
Why so complicated? Difficult to write programs
Who designed these??
Can’t we make it easier???

Early days, the instruction sets used to be

relatively easy to understand and write.
■ Microchip PIC instruction set.
■ Z80 instructions.

We need to understand real world demands

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How to identify a good ISA?
Meet functional requirements

Are the real-world computations cheaper, faster

and energy efficient?
Have less “code density”, so the memory for
storing and transferring programs will be less
The base instruction set is selected based on the
real-world performance measures.
■ Run a collection of real-world programs with and
without a specific instruction
“Benchmark” Example: SPEC benchmark
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Good time to start reading the book.
■ Chapter 1

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Assembly Programmers View
Writing code ?
■ Usually, we write codes in C or Python etc.
■ Compilers and Assemblers can take care of
converting high-level codes to machine codes.
Let us define some ‘high-level assembly’
instructions as well to make it easier to write
assembly codes

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Assembly Programmers View
Example:
■ Loading 32bit values to registers using base
instructions is complicated.
■ Let our assembler handle the complexity
■ We shall write intuitive instructions
Pseudo Instructions
li t1, 0x7FFFFFFF
Load immediate value to t1 register (assembler will convert
this to following two “base instructions”)
80000337 lui t1,0x80000
fff30313 addi t1,t1,-1 # 7fffffff
List of pseudo instructions can be found in riscv-card. 17
Some RISC V Pseudo Instructions

Some more are available…

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Memory Related Instructions

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Registers vs Memory (Norms)
General Purpose Memory
Registers
■ Named (norm) ■ Addressed
■ Limited ■ Larger/Extended
■ Located very close to the ■ Away from ALU
ALU
■ Expensive ■ Cheaper compared to
registers
■ Fast ■ Slow compared to
registers
■ Locations are not related ■ Memory “map”: relative
locations (Viewed as an
array or a contiguous
space)
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Registers vs Memory
0xfff30313 Instruction
Processor Core Memory

pc 0x000000d8

IR 0xfff30313

a0 0x000020d8
Data
t0 Memory
t1

Device Control/Status
Registers 21
Instructions for memory access
Load values from memory to registers
Store values to memory from registers 32bits
0
Address? 1

■ How many addresses?

RV32I => Address bus is 32bits
Maximum Memory Space: 232 x 4bytes
4294967296
2^32 /1024/1024/1024 = 4GB x 4bytes
RV64I => Address bus is 64bits
Values? 232-1

■ 32 bits 22
Load and Store Instructions

Load: copy a value from memory to register rd : Immediate type

Source is a memory address
Store: copy the value in register rs2 to memory : Store type

Need the proper 32bit address

(Immediate type and Store type)

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Load Word Instruction (I type)
lw t0, 4(a0)
RISCV Instruction: lw x5, 4(x10) Assume we have a ‘base address’
already available in a0 register

No. of bytes offset

000000000100 01010 010 00101 0000011

31 20 19 15 14 12 11 7 6 0

Imm[11:0] rs1 funct3 rd opcode

Byte offset (immediate) Base address funct3 Destination I type load

register lw register
0 1 0 0 0 0 0 0 1 1
0 0 1 0 0 0 1 0 1 0 0 0 1 0 1
0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 1
0 0 4 5 2 2 8 3

Machine Instruction: 0x00452283 24

Load Half Instruction (I type)
lh t0, 2(a0)
RISCV Instruction: lh x5, 2(x10) Assume we have a ‘base address’
already available in a0 register
Only half of the word will be loaded
No. of bytes offset

000000000010 01010 010 00101 0000011

31 20 19 15 14 12 11 7 6 0

Imm[11:0] rs1 funct3 rd opcode

Byte offset (immediate) Base address funct3 Destination I type load

register lh register
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 1 0 1 0 0 0 1 0 1
0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1
0 0 2 5 1 2 8 3

Machine Instruction: 0x00251283 25

Store Instructions (S type)
To store a value in memory, you need three
things
■ Memory location to save to
rs1: base memory address
Immediate memory location offset
■ Value to save
rs2: contains data to be stored
■ Choice: Move rs2 to different place or split immediate
offset
Example sw x14, 8(x2)
rs1 base addr
rs2 register with value Immediate offset 26
Store Type Example 1

RISCV Instruction: sw x14, 8(x2)

0 0 0 0 0 0 0 0 1 0 0 0

imm[11:5] rs2 rs1 funct3 imm[4:0] opcode

0 1 0 0 1 0 0 0 1 1
0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0
0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 1
0 0 E 1 2 4 2 3

Machine Instruction: 0x00E12423

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Store Instructions (S type)
sw t0, 4(a0)
RISCV Instruction: sw x5, 4(x10) Assume we have a ‘base address’
available in a0 register

No use unless
offset is large 00101 01010 010 00100 0100011
31 20 19 15 14 12 11 7 6 0

Imm[11:5] rs2 rs1 funct3 Imm[4:0] opcode

Immediate offset Source Base address funct3 Immediate S type store

[4:0] register register sw offset [4:0]
0 1 0 0 1 0 0 0 1 1
0 0 1 0 1 0 1 0 1 0 0 0 1 0 0
0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1
0 0 5 5 2 2 2 3

Machine Instruction: 0x00552223 28

Programmers Perspective
We don’t know memory addresses.
Let us write memory position independent code
■ Ask the assembler to declare a data section along
with the instruction sequence

■ auipc instruction allows to address relative to

program counter.

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.data
A: .word 0x1F2F3F4F
.text
.globl main

main:
la a0, A
# Pseudo instruction la (How it works? will discuss in next slide)
# Load the address of symbol to the register

li t1, 0x1E2E3E4E

lw t0, 0(a0)
# Get the value in a0 address, byte offset 0 and load it to t0 register

sw t1, 0(a0)
# Store value in t1 to A, at byte offset of 0

ret
.end

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auipc instruction and la pseudo
instruction

.data
A: .word 0x1F2F3F4F 000000d8 <main>:
.text d8: 00002517 auipc a0,0x2
dc: 0b050513 addi a0,a0,176 # 2188 <A>
.globl main e0: 00002517 auipc a0,0x2
main: e4: 0a850513 addi a0,a0,168 # 2188 <A>
la a0, A e8: 00002517 auipc a0,0x2
la a0, A ec: 0a050513 addi a0,a0,160 # 2188 <A>
la a0, A f0: 00008067 ret
ret
.end 31
auipc instruction
000000d8 <main>:
d8: 00002517 auipc a0,0x2
dc: 0b050513 addi a0,a0,176 # 2188 <A>
pc 0x000000d8
e0: 00002517 auipc a0,0x2
e4: 0a850513 addi a0,a0,168 # 2188 <A>
e8: 00002517 auipc a0,0x2
ec: 0a050513 addi a0,a0,160 # 2188 <A>
f0: 00008067 ret

a0 0x000020d8

t0

t1 0x00002000
0x000000d8
A: 0x00002188: 0x000020d8
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auipc instruction
000000d8 <main>:
d8: 00002517 auipc a0,0x2
dc: 0b050513 addi a0,a0,176 # 2188 <A>
pc 0x000000d8
0x000000dc
e0: 00002517 auipc a0,0x2
e4: 0a850513 addi a0,a0,168 # 2188 <A>
e8: 00002517 auipc a0,0x2
ec: 0a050513 addi a0,a0,160 # 2188 <A>
f0: 00008067 ret

a0 0x000020d8
0x00002188

t0
1762 = 0x000000b0
t1
0x000020dc
+ 0x000000b0
A: 0x00002188:
0x00002188
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la pseudo instruction
We wrote the same instruction, but it is converted
to different immediate values by assembler

.data
A: .word 0x1F2F3F4F 000000d8 <main>:
.text d8: 00002517 auipc a0,0x2
dc: 0b050513 addi a0,a0,176 # 2188 <A>
.globl main e0: 00002517 auipc a0,0x2
main: e4: 0a850513 addi a0,a0,168 # 2188 <A>
la a0, A e8: 00002517 auipc a0,0x2
la a0, A ec: 0a050513 addi a0,a0,160 # 2188 <A>
la a0, A f0: 00008067 ret
ret
.end 34
Branching Instructions

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Branching Instructions
(Branch type)

Change the Program Counter

⬄ Change the Program Flow

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Thank you!

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