Digital Systems II Chapter 2
Counters
INTRODUCTION
-As discussed in Chapter 7, the connection of flip-flops enables
the performance of counting operations.
-The number of flip flops employed and how they are coupled
define the number of states, known as the modulus, as well as the
precise sequence of states that the counter runs through
throughout each complete cycle.
-Counters are divided into two main categories based on how they
are clocked: asynchronous & synchronous.
-Asynchronous counters, also known as ripple counters, the first
flip-flop is clocked by an external clock pulse, and each
subsequent flip-flop is clocked by the output of the previous flip-
flop.
-Synchronous counters, the clock input is linked to all of the
flip-flops, causing them to be clocked at the same time.
Counters are characterized largely by the type of sequence, the
number of states, or the number of flip-flops in the counter within
1
each of these two categories. very high-speed integrated circuit
hardware description language (VHDL) codes for several counter
types are shown.
Asynchronous Counters
-The term asynchronous refers to events that do not have a fixed
time relationship with each other and, generally, do not occur at
the same time.
-An asynchronous counter is one in which the flip-flops (FF)
within the counter do not change states at exactly the same time
because they do not have a common clock pulse
A 2-Bit Asynchronous Binary Counter
Below is an asynchronous 2-bit counter. The clock (CLK) is
applied to the clock input (C) of just the first flip-flop, FF0, which
is always the least significant bit (LSB).
The second flip-flop, FF1, is triggered by the Q0 output of FF0.
FF0 changes state at the positive-going edge of each clock pulse,
but FF1 changes only when triggered by a positive-going
transition of the Q0 output of FF0
2
A 2-bit asynchronous binary counter. Open file F09-04 to verify operation. A Multisim tutorial is
available on the website.
-Applying four clock pulses to FF0 and observing the Q output of
each flip-flop will allow us to investigate the fundamental
operation of the asynchronous counter depicted in Figure below.
-Both flip-flops are connected for toggle operation (D = 𝑄) and
are initially presumed to be RESET (Q LOW).
As shown in the waveform below, the rising edge of CLK1 (clock
pulse 1) causes the Qo output of FF0 to go HIGH. Concurrently,
the 𝑄𝑜 output goes LOW, but this has no effect on FF1 because
a positive-going transition must occur to trigger the flip-flop.
3
Timing diagram for the counter of the figure above. As in previous chapters, output waveforms
are shown in green.
-Below is the truth table for the 2 bit asynchronous Counter.
Binary state sequence for 2 bit Asynchronous counter
A 3-Bit Asynchronous Binary Counter
The state sequence for a 3-bit binary counter is shown in the
following table, and a 3-bit asynchronous binary counter is
depicted in the following figure. The fundamental operation is
identical to that of the 2-bit.
4
asynchronous binary counter and its timing diagram for one cycle.
5
Propagation Delay
-Asynchronous counters are commonly referred to as ripple
counters for the following reason: The effect of the input clock
pulse is first “felt” by FF0. This effect cannot get to FF1
immediately because of the propagation delay through FF0.
-Then there's the propagation delay through FF1 before FF2 may
be activated. Thus, the effect of an input clock pulse "ripples"
through the counter, requiring some time to reach the last flip-flop
owing to propagation delays.
Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.
Observe how delays are cumulative, as each stage of a counter
is clocked later than the one before it.
6
Four-bit asynchronous binary counter and its timing diagram
A 4-bit asynchronous binary counter is shown in Figure (a)
below. Each D flip-flop is negative edge-triggered and has a
propagation delay for 10 nanoseconds (ns). Develop a timing
diagram showing the Q output of each flip-flop, and determine
the total propagation delay time from the triggering edge of a
7
clock pulse until a corresponding change can occur in the state of
Q3. Also, determine the maximum clock frequency at which the
counter can be operated.
𝑇𝑝 𝑡𝑜𝑡𝑎𝑙 = 4𝑥10𝑛𝑆, the max CLK frequency is
1 1
𝑓𝑚𝑎𝑥 = = = 25𝑀𝐻𝑧
𝑡𝑝 40
To avoid issues caused by the propagation delay, the counter must
operate below this frequency.
*Related problem
If all of the flip-flops in Figure (a) above are positive edge
triggered, display the timing diagram.
Asynchronous Decade Counters.
-After the 1001 state, this counter recycles the count sequence
back to zero using incomplete decoding. Because the flip-flops
are activated by the trailing edge, clocks are derived from the Q
outputs. Using a similar method, additional truncated sequences
can be obtained.
-The modulus of a counter is the number of phases through which
it will sequence.
8
-MOD10 is a typical modulus for counters with truncated
sequences. Decade counters are counters with 10 states in their
sequence.
➢ Max number of states = 2𝑛
➢ Where n is the number of flip-flops in the counter
➢ Counters can be built in such a way that the number of states
in their sequence is smaller than the maximum value of 2𝑛
Partial decoding
-In Figure (a) below, just 𝑄1 and 𝑄3 are linked to the NAND gate
inputs. Partial decoding is used in this configuration since none
of the other states (zero through nine) have both 𝑄1 and 𝑄3 HIGH
at the same time, which makes it sufficient to decode the count of
10.
-The time diagram is presented in waveform (b). Notice the Q1
waveform glitch. Q1 must hit HIGH before the count of ten can
be deciphered, which causes this issue.
➢ Count sequence from 0000 to 1001.
9
➢ One way to make the counter recycle after count 9(1001) is
to decode count 10(1010) with a NAND gate and count the
o/p of the NAND gate to the clear (CLR) inputs of the FF.
An asynchronously clocked decade counter with asynchronous recycling.
10
Show how an asynchronous counter with J-K flip-flops can be
implemented having a modulus of twelve with a straight binary
sequence from 0000 through 1011.
Asynchronously clocked modulus-12 counter with asynchronous recycling.
*Related problem
How can the counter in Figure (a) above be modified to make it a
modulus-13 counter?
11
Synchronous Counters
In a synchronous counter, all flip-flops are clocked together with
a common clock pulse. Synchronous counters overcome the
disadvantage of accumulated propagation delays, but generally
they require more circuitry to control state changes.
A 2-Bit Synchronous Binary Counter
2-bit synchronous binary counters.
Timing diagram for the above counter
Operation of a J – K flip flop synchronous counter
-First, assume that the counter is initially in the binary 0 state; that
is, both flip-flops are RESET.
12
-When the positive edge of the first clock pulse is applied, FF0
will toggle and Q0 will therefore go HIGH.
Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-
flops are assumed to be equal).
A 3-Bit Synchronous Binary Counter
A 3-bit synchronous binary counter and its timing diagram is
shown below.
13
-𝑄0 changes on each clock pulse as the counter moves from its
initial state to its final state and back.
-FF0 must be held in the toggle mode by constant HIGHs on its
𝐽0 and 𝑄0 inputs.
-Notice that 𝑄1 goes to the opposite state following each time 𝑄0
is a 1. This change occurs at CLK2, CLK4, CLK6, and CLK8.
The CLK8 pulse causes the counter to recycle.
-To produce this operation, 𝑄0 is connected to the 𝐽1 and 𝐾1
inputs of FF1. When 𝑄0 is a 1and a clock pulse occurs, FF1 is in
14
the toggle mode and therefore changes state. The other times,
when 𝑄0 is a 0, FF1 is in the no-change mode and remains in its
present state.
➢ FFO is held at the toggle mode by Jo=Ko=H
➢ Q1 goes to the opposite state each time Qo =1, which occurs
at CLK 2, CLK4, CLK 6, and CLK 8.
➢ CLK 8 causes the counter to recycle.
➢ Qo is connected to J1 and K1 of FF1
➢ When Qo = 1 and a CLK pulse occurs FF1 is in the toggle
mode.
➢ When Qo = 0 no change occurs
➢ FF2 changes when Qo = Q1 = Q2
➢ This causes FF2 to toggle at other times FF2 has no change.
Summary of the analysis of the counter
A 4-Bit Synchronous Binary Counter
15
-Figure and timing diagram below show a 4-bit synchronous
binary counter.
-This particular counter is implemented with negative edge-
triggered flip-flops. The reasoning behind the J and K input
control for the first three flip-flops is the same as previously
discussed for the 3-bit counter.
-FF3 changes only twice in the sequence i.e Q0 =Q1 = Q2= HIGH
This conclusion is decoded by AND gate G2, that when a clock
pulse occurs FF3 will change state.
-For all other timers J3 and K3 inputs of FF3 are low and FF3 is
called the no change counter.
A 4-bit synchronous binary counter
16
Timing diagram
A 4-Bit Synchronous Decade Counter
-As you know, the BCD decade counter goes from 0000 to 1001
in a truncated binary sequence. It recycles to 0000 instead of 1001
to 1010. A synchronous BCD decade counter and timing diagram
are presented below.
A synchronous BCD decade counter.
17
Timing and diagram
-FF0 toggles when J0= K0 = 1
-FF1 (Q1) changes on the next clock pulse each time Q0 = 1 and
Q3 = 0. Therefore, logic equation for J1 and K1 is J1=K1=Q0Q3
→ use AND
-FF2 (Q2) changes on the next clock pulse when Q0 =1 and Q1=
1. The input logic equation is J2 =K2 =Q0Q1. Use AND gate 2
-FF3 (Q3) changes to the opposite on the next clock pulse each
timer Q0=1, Q1= 1, Q2 =1 ( State 7) OR when Qo=1 and Q3= 1
( State 9). The logic equation for J3 and K3 inputs are J3=
K3=QoQ1Q2 + QoQ3. → Use AND/ OR logic shown.
18
4-Bit Synchronous Binary Counter Implementation
The 74HC163 4-bit synchronous binary counter
The 74HC163 is a 4-bit synchronous binary counter integrated
circuit.
19
Timing example for a 74HC163.
Up/Down Synchronous Counters
-An up/down counter can move in either way across a sequence.
-Up/down counters, often known as bidirectional counters, can
have any given state sequence.
-A 3-bit binary counter that advances upward (0, 1, 2, 3, 4, 5, 6,
7) and reverses direction (7, 6, 5, 4, 3, 2, 1, 0) illustrates
up/down sequential execution.
20
-FF0: For Q0, FF0 will toggle on each clock pulse i.e Jo=Ko=1
-For UP sequence a change on the next clock pulse when Qo=1
-For Down sequence, Q1 changes on the next clock pulse when
Qo = 0
-FF1: The J1 and K1 input for FF1 under the FF conditions is
J1= K1= Qo. Up + 𝑄0 . Down
-FF2: For Up count, Q2 change on the next clock pulse when Qo=
Q1= 1.
-For Down count, Q2 changes on the next clock pulse when Qo=
Q1 =0
-Thus J2, K2 impact for FF2=1 under the conditions expressed by
the following equation:
J2=K2=QoQ1. Up + 𝑄𝑜𝑄1. Down
-Each of the conditions for the J and K inputs of each flip flop
produces a toggle at the appropriate point in the counter sequence.
Up/Down sequence for a 3-bit binary counter.
21
𝐽0 = 𝐾0 = 1
𝐽2 = 𝐾2 = (𝑄0 . 𝑄1 . 𝑈𝑃) + (𝑄0 . 𝑄1 . 𝐷𝑂𝑊𝑁)
A basic 3-bit up/down synchronous counter
22
Show the timing diagram and determine the sequence of a 4-bit
synchronous binary up/down counter if the clock and UP/DOWN
control inputs have waveforms as shown in Figure (a) below. The
counter starts in the all-0s state and is positive edge-triggered.
Truth table
23
*Related Problem
Show the timing diagram if the UP/DOWN control waveform in
Figure (a) above is inverted.
Implementation: up/down decade counter
The figure below shows a logic diagram for the 74HC190, an
example of an integrated circuit up/down synchronous decade
counter. The direction of the count is determined by the level of
the up/down input (D/U). When this input is HIGH, the counter
counts down; when it is LOW, the counter counts up. Also, this
device can be preset to any desired BCD digit as determined by
the states of the data inputs when the LOAD input is LOW.
The 74HC190 up/down synchronous decade counter.
24
-In the timing diagram below, the 74HC190 counter is set to seven
(0111) and goes through a count-up and count-down process.
- The MAX/MIN output is HIGH when the counter is in either the
all-0s (MIN) or 1001 (MAX) state.
Timing example for a 74HC190
Design of Synchronous Counters
-We use sequential circuit design techniques and apply them to
counter design.
25
-Sequential circuits are classified into 2 types namely Moore
Circuit and Mealy Circuit.
-Moore circuit: The output/s depend only on the present internal
state.
-Mealy Circuit: output/s depend on both the present state and the
input/s.
-The section is recommended for those who want an introduction
to counter design or state machine design.
Step 1: State Diagram
A state diagram is the initial stage in designing a state machine
(counter). The state diagram displays the series of states the
counter goes through when clocked. A basic 3-bit Gray code
counter state diagram is shown below.
This circuit has only the clock as input and its outputs are the flip-
flop outputs from the counter. Please study the coverage of the
Gray code in Chapter 2 at this time.
26
State diagram for a 3-bit Gray code counter.
Step 2: Next-State Table
After defining the sequential circuit with a state diagram, create a
next-state table listing the current state of the counter and its
matching next state. The counter moves to the next state once a
clock pulse is applied. The next-state table for the 3-bit Gray code
counter is illustrated in Table below, generated from the state
diagram. Q0 is the least important bit.
27
Step 3: Flip-Flop Transition Table
The J-K flip-flop transition table is shown above. To list all
potential output transitions, the Q output of the flip-flop is shown
from current to next states.
Qn represents the current flip-flop state before a clock pulse, and
Qn + 1 represents the following state after 1 clock pulse. For each
output transition, the J and K inputs causing it are stated. An X
means “don’t care” (input might be 1 or 0).
Step 4: Karnaugh Maps
28
Examples of the mapping procedure for the counter sequence
Karnaugh maps determine the logic needed for the J and K inputs
of each flip-flop in the counter. There are Karnaugh maps for both
the J and K inputs of each flip-flop. To design, each cell in a
Karnaugh map reflects a current stage in the counter sequence
specified in Table above.
Completed Karnaugh maps for all three flip-flops in the counter
are displayed in the figure below. The cells are grouped and
Boolean expressions are created for each group.
29
Karnaugh maps for present-state J and K inputs.
Step 5: Logic Expressions for Flip-Flop Inputs
From the Karnaugh maps of Figure below you obtain the
following expressions for the J and K inputs of each flip-flop:
Step 6: Counter Implementation
30
Finally, construct combinational logic from J and K input
expressions and link flip-flops to create the 3-bit Gray code
counter (see Figure below).
Design a counter with the irregular binary count sequence shown
in the state diagram of Figure below. Use D flip-flops.
31
The state diagram is as shown. Although there are only four states,
a 3-bit counter is required to implement this sequence because the
maximum binary count is seven.
Since the required sequence does not include all the possible
binary states, the invalid states (0, 3, 4, and 6) can be treated as
“don’t cares” in the design.
However, if the counter should erroneously get into an invalid
state, you must make sure that it goes back to a valid state.
The D inputs are plotted on the present-state Karnaugh maps in
Figure below. Also “don’t cares” can be placed in the cells
32
corresponding to the invalid states of 000, 011, 100, and 110, as
indicated by the red Xs.
To simplify, group the 1s and use as many “don’t care” states as
possible, as illustrated in Figure below. The expression for each
D input from the maps is:
*Related problem
33
Verify the analysis that proves the counter will always return
(eventually) to a valid state from an invalid state.
34
