Advancing Low-Power Innovation

The Next Generation Full-chip Dynamic Power Analysis and Optimization Solution

RedHawk-NX is a next generation full-

chip power integrity solution archi- Dynamic Voltage Drop
tected to meet the capacity and performance
requirements of the most advanced Advanced Low Power
designs. RedHawk-NX can be used for early-
stage
Columbusgrid prototyping and optimization,
Impact on Timing
pre-tape-out power sign-off, and post
silicon debug. It has been silicon-proven
with thousands of successful tape-outs Power & Signal EM
by leading semiconductor and fab-
less semiconductor companies. By Root Cause Identification
using RedHawk-NX, engineers can mitigate
risks, reduce cost, and improve time-to-
Chip Model Creation
market.

Key Capabilities

• Provides SPICE accurate transient simula- • Earlyprototyping and analysis for package • Chip-Package-Board co-design analysis for
tion results at the SoC level through power selection and re-design risk mitigation late faster system-level power integrity closure
noise aware modeling of standard cells, in the design cycle
memories and IPs • Unified analysis and debugging environ-
• Fasterturn around time using high perfor- ment, including integrated root cause
mance multi-CPU engine and MPR (Mesh identification technology, reduces debug
Pattern Recognition) technology cycle time

Overview High Capacity and Performance memory needs. The benefits are significant
for stages of analysis that are most impacted
RedHawk-NX performs transient simulation RedHawk-NX’s hierarchical dynamic tech-
by design size such as extraction and matrix
with pico-second resolution to accurately nology delivers 30-50% reduction in runtime,
solve, providing 2-3X reduction in memory
analyze the effects of simultaneous switching peak memory usage, and disk space
footprint. Additionally by using multiple
noise coming from core logic, memory, macro, consumption, compared to a full flat analysis,
and I/O. It considers the on-chip and off-chip while maintaining accuracy of results within
capacitance elements, as well as package 2-3%. The capacity improvements are greater
and board parasitics. It integrates transistor- when sub-blocks or macros/memory modules
level SPICE modeling, inductance extraction are instantiated multiple times in the design.
of the on-die power grid, and package and
RedHawk-NX’s Mesh Pattern Recognition
system level parasitics for analysis of high
(MPR) is the industry’s first hierarchical
performance SoCs. RedHawk-NX provides an
extraction technology utilizing the regularity
integrated environment for analyzing Power,
of patterns in the power grid network for data Hierarchical modeling of memories and IPs
Noise and Reliability issues in SoC designs.
re-use and effective reduction of physical

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RedHawk-NX™ The Next Generation Full-chip Dynamic Power Analysis and Optimization Solution

cores systems, RedHawk-NX can parallelize Advanced Vectorless and amount is allocated during the placement
computation tasks and reduce the run-times, VCD Analysis Options stage.
especially for MTCMOS rush current analysis.
RedHawk-NX provides Vectorless Dynamic RedHawk-NX with FAO can also be used to re-
SPICE Accurate Simulation engine for full-chip dynamic analysis. The design the power grid mesh either in local area
Vectorless engine generates a cycle-by-cycle (fixing) or over the whole chip (optimization).
RedHawk-NX’s Apache Power Library (APL) Without compromising the total voltage drop,
pre-characterizes every cell in the design using switching scenario honoring user specified
constraints and extends the analysis coverage it increases metal resources in the areas of
SPICE simulation. It models switching current dynamic “hot spots”, while reduces the metal
waveforms and RC parasitic information by considering various design weakness
scenarios. The “smart” Vectorless techniques widths of the areas with low voltage drop to
for different input slew, output load, supply avoid over-designing. Its non-uniform grid
voltage, and operating states. RedHawk uses model power transients caused by sudden
power steps such as system reset sequencing. optimization allows designers to specify
this model to simulate all power and ground constraints such as area, metal layers, and
domains simultaneously and the switching The “frequency-aware” Vectorless option
generates switching scenario that considers target drop. Since the optimization engine is
current drawn by each cell is updated at every
time step based on the effective voltage seen resonance frequency of the chip-package-
by the cell. system, allowing designers to study the
impact of package resonance on the system.
The “scan” Vectorless technique supports
ATPG-based power integrity analysis without
requiring any vectors.

RedHawk-NX transient simulation supports

both gate (toggle information for every gate)
and RTL (toggle information for every state
and primary I/O point) vectors in industry
standard formats.

Design Optimization with

APL current characterization as a function of voltage “What-if” and FAO
RedHawk-NX simulation includes cell’s From within the RedHawk-NX’s GUI, the
intrinsic capacitance, load capacitance, designer can perform extensive “what-
intentional decoupling capacitance, and if” analysis for power-grid exploration and
well capacitance along with their respective design tradeoffs assessments. Designers can
resistive components. A package and board explore different ways to reduce IR drop and
model in either S-parameter or RLCK format EM violations by editing power/ground pads,
is also considered during true-transient power straps, vias / via arrays, and adding or
simulation. Typically, RedHawk-NX’s transient deleting power gates in the design. The easy-
simulation voltage waveforms results are to-use, layout-driven, incremental “what-if”
within 2% of SPICE and measured silicon. capabilities, including incremental extraction,
enables the designer to quickly explore design
Memory and Macro Modeling fix scenarios.
For memories and custom macros, RedHawk- RedHawk-NX with optional FAO feature
NX uses detailed GDS views for modeling provides automated fixing and optimization
the power grid. It can intelligently identify capabilities to reduce peak IR drop in the
the regions of memory bit-cells and adjust design. It analyzes the full-chip intrinsic
the current distribution within the memory parasitic and computes the additional
for higher degrees of accuracy. RedHawk- intentional decoupling capacitance (decap)
NX can also take the transistor-level SPICE required, as well as provide information
characterized models from the Totem™ about ineffective decap cells that can be
platform through Custom Macro Models eliminate, thus reducing their impact on
(CMM™). Using this model, designer can leakage and yield. Decap optimization can Design fixing using RedHawk-FAO
perform transistor-level analysis for memories be accomplished early in the design stage
and macros within the SoC design. to ensure that the location and the correct
tightly integrated with RedHawk-NX’s proven provides a number of waveform views such Average and transient current assignment can
dynamic analysis engine, the designers as total current / charge profile and instance- be done at region level and its distribution can
can feel confident with the accuracy of the based VDD drop / VSS ground bounce, and a be controlled by the user.
optimized grid. full-chip movie playback with instance-based
RedHawk-NX provides pad/bump placement
voltages over time.
Power Electro-migration Analysis guidance and identifies current congestion
Its layout based GUI provides designers areas on the die. From the early prototype
RedHawk-NX’s current direction-aware ex- with the flexibility and robustness required analysis, designer can create early die model,
traction technology delivers accurate power for easy-to-use yet comprehensive debug- Chip Power Model (CPM™). The package
EM analysis, resulting in least number of ging capabilities. and board designers can use CPM to help
false EM violations. RedHawk-NX can handle determine required number of layers in a
advanced rules which consist of EM limit Early Prototyping and Analysis package, the needed pin count, and the
variation for different width, length, thickness routing and via placement challenges.
RedHawk-NX allows power grid prototyping
and temperature, as well as blech-aware EM.
based on design specifications and
RedHawk-NX also supports advanced signal
technology information. The designers can
EM analysis with its SEM option.
build an early design database by using an
Unified Analysis and extensive set of layout drawing commands, or
Debugging Environment read in partial design information. RedHawk
provides intuitive and interactive capabilities
RedHawk-NX provides a single unified for mesh creation and automatic via, pad,
environment for analysis and debugging switch, and decap placement. Initial floor plan
of power, noise, and timing. It provides data along with power consumption data for
designers with various views, including layout various blocks, macros, and regions, are used
view of the power density, instance power, to perform early power analysis for the design.
and dynamic voltage drop. RedHawk-NX also

RedHawk GUI

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RedHawk-NX™ The Next Generation Full-chip Dynamic Power Analysis and Optimization Solution

RedHawk Explorer Design Weakness Check

RedHawk Explorer performs qualitative
RedHawk Explorer (RHE™) is an extension
design weakness check of parameters that
to RedHawk-NX which helps the designer
can cause power integrity issues such as pad
in locating, isolating, understanding, and
placement quality, power/ground weakness,
resolving various power integrity issues in
and simultaneous switching and highlights
SoC designs. RHE is tightly integrated with
regions with design weaknesses. It provides
RedHawk and provides very powerful cross-
interactive cross probing with RedHawk
probing capabilities with the RedHawk GUI.
GUI and allows the designer to control the
RHE can perform data integrity analysis,
thresholds in various qualitative checks.
design weakness exploration, and root cause
identification for different hot-spots in the
Minimum Resistance Path Tracing
design. It also generates a concise summary
Minimum Resistance Path Tracing in RedHawk
for various analysis results.
Explorer highlights the electrically shortest
route from Power/Ground voltage sources to
any instance in the design. The generated
resistance report shows the minimum
resistance path highlighting the bottleneck
segments.

RedHawk Explorer Summary View

Connectivity Tracing using RedHawk Explorer
Data Integrity Analysis
RedHawk Explorer reviews the user input data
Root Cause Identification
and alerts the designer if there are any data
During root cause identification, RedHawk
integrity issues. It highlights the regions in the
Explorer analyzes various voltage drop / EM
design which are affected with various issues
hot spots in the design and identifies their root
including library/design input data coverage
cause. It back-traces the data integrity issues
and missing-vias and shorts in the layout.
and design weaknesses, and highlights the
It generates detailed reports and provides
problems in the “hot spot” region / instance.
easy navigation options for the designers to
browse through the reports. It also checks
analysis settings used by the designer and
offers recommendations if there are any
settings which are out of range.

Root Cause Identification using RedHawk Explorer

Data Integrity Analysis using RedHawk Explorer

Apache Design Solutions

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