Arithmetic and Logic Unit Part-1 : Part-2 : Part-3 : Part-4 : Part-5 CONTENTS Arithmetic and Logic Unit : Look Ahead Carries Adders .. 2-2B to 2-4B .. 2-4B to 2-11B Multiplication : Signed . Operand Multiplication, Booth’s Algorithm and Array Multiplier ...2-11B to 2-16B Division and Logic Operations ...... Floating Point Arithmetic... ... 2-16B to 2-21B Operations, Arithmetic & Logic Unit Design IEEE Standard for... 2-21B to 2-24B Floating Point Numbersie Unit (ALY) ithmetic and Logic Que 2.1. | Describe sequential Arithmetic using proper diagram, 4—__ jircuits with the hely By combining arithmetic and logic circuits with we can get the arithmetic and logic units. p of multiplexer, { >| Arithmetic > circuit Lof —| Logie seme] circuit >| When the mode so the output of Based on the mod: When logic ope: @ » 1 Fig. 2.1.1. Block diagram of ALU, a select line S, =0, this ALU acts as an arithmetic circuit, arithmetic cireuit is transferred the output ofthe logic circuit: le select S, and input carry as final output. is transferred as final output, C,,, We increase or decrease arithmetic and logic operations, ‘quired in the logie circuits, ration is selected (S, ‘he output sum in full Y,=4,©B,@ ¥,=4,@B, Que 22. | Write short note on look ah, A Carry Look Ahead 'y input must be zero. ead carry adders, adder (CLA) or fast adder isa type ofcomputer rgeniatone eitecure en icsr-sems) 2.8 B (CS/T-Sem-3) p Acary lok ahead 2dr improves speed by veda time required to termine cary bits, y reducing the amount of yk ahead adder cal 3, Thecarry loo ¥ calculates on, Mis which reduces the Waiting time teal aaene cat bts before the Salue bits of the adder. late the result of the langer- 4, Carry lok abead depends on two things; a. Calculating: for each digit position 7 propagate a carry if one comes in pee that position is going to b, Combining these calculated values to be oe ‘whether, for each group of digits able to deduce quickly : t ve to nearry that comes in from the me Sroup is going to propagate 5, Carry look ahead logic uses the concepts of generating and propagati i agating 6g. The addition of two binary numbersin parallel impli j ‘The carry propagation timeis an important attri it limits the speed with which two numbers ma aed. adder Pocus g, Asolutionis to inerease the complexity of the equipment that the carry delay time is reduced. equipment in such a way Half adder Pac Fig. 2.2.1, 9 der the circuit of the full adder shown in Fig. 2.2.1, If we define two new binary variables, P,=A,OB,,G,=AB, 10, The output sum and carry can respectively be expressed as S, =P, ®C,, Ci =G,+P,C; sarry generate, and it produces a carry of 1 when both A, -yC,.P sealed acarry propagate, ‘arry into stage i will propagate into C.=G, +P,C,= G, + PLGo+ PC +L PG,+ PPG, + PP PC‘prithmetic and Logic y) 2B (CSIT-Sem.3) + a we Ce P, al et at Gy - com c Po. I i Go. 4 Cy —4_____ Fig. 2.2.2. Logic diagram of carry look ahead generator. Lrarr-2 | Multiplication : Signed 0; )perand Multiplication, Booth’s Alzorithm, and Array Multipliers, aeeninsiienanialaiiaentttiitien ———___ Questions-Answers Tong Answer Type and Medium Answer Type Questions 's algorithm in depth with the help of flowchart. Give an example for multiplication using Booth’s algorithm, AKTU 2016-17, Marke 1 Discuss the Booth’s algorithm for 2 5 lustrate it with the some example, > °™Plement number, Also OR Explain Booth’s multiplication algorithm in dot il etail, z 18, Marks 07 An: The algorithm for 2's complement multi Plication is as ' followsComputer Organization & Architecture 2-5 B (CS/IT-Sem-3) din B, mul top 1: Load multiplicand in B, multiplier in. F i st a a be wed. ‘or negative numbers, 2's tep 2: Initialize the down counter CR by the m ad Step {Clean locations A (n-bits) and Q, ee step 4 : Check LS bit of Q, and Q, , ; jointly. If the patterni . Pao. If 10,thenA=A~B. 101, then A= A+ Mer s00or 11 then z ithmetic right-shift with A, y Step 5: Perform ari with, Q, and Q,,, ,. LSof A goes t Sie erg, and LS of Q goes to Q, .,. Old content nis discarded Step 6 Decrement CRby one. 1f CR isnot zero then go to Step 4 Step 7: Final result (or the product) is available in A (higher part) and Q, (ower part). , Load multiplicand in B multiplier in Q Initialize CR by no. of bits Clear A and Q,. IsLS bit of Q and Qa +1 re A=A+B Perform 1-bit arithmetic right shift A,Q,andQ,,, [a——I then decrement CR by 1 Final result in A and Q Fig. 2.3.1. 2's Complement multiplication. Example : Both negative (-5 x-4) ‘Multiplicand (B)<-1011(-5) Multiplier (Q<1100-4) A Q, Q,.1 | Operation | CR 0000 | 1100 0 | Initial 4 0000 | 0110 0 | Shiftright 3 0000 | 0011 0 Shift right 2 o101 | 0011 o | AcA-B 1 oo10 | 1001 1 | Shiftright 0001 | 0100 1 | Shiftright 0 [wenit 0001 0x00 _=+20___——!anitnmetle and Logle Uni 2-6 1 (CAUP- Soma) _— ~~ juh ies hardway, vith Queda, | explain Booth'# alqort implomontation, : Answer Vig. 241 shows the hardwal ni for Booth’s algorithm, umber multiplication, ie regivter A, B, Q and | 1 > 1 ~ cirenit for por 2 The eireuit is similar (o the eit bite ni fi 3. A eonsists of an mbit addor, cont Q Mutuiphiennel mE] | eof] 1bit register Hardware implementation of signed binary multiplication for Booth’s algorithm, 4. Multiplier and muitiplicand are loaded into register Q and register B tively and Q , and initially set to 0. 6. The n-bit adder performs add multiplicand and content of re ton, input of adders comes from ster A 7, Incase ofaddition, Add /Sub lines 0, therefore, @ is directly applied as a second input to the n-bil aad 0 and multiplicand a er 8. In case of subtraction, Add/Sub line is 1 : | multiplicand is complemented and then applied ere c,, = Land result, the 2’s complement of the multiplicand jee "bit adder. As® of register A. 1s added to the content 9. The control logie scans bit Q, and Q one at ay; control signals to perform the correspon, clin, time and generates the 10. If the two bits are same (1~1 or Q ~0), the, function, Q_, register are shifted to right 1 it without cut the bits of A, Q ad (Add/Subtract Enable = 0). addition or subtractiotComputer Organization & Architecture 2-7 (CS/IT-Sem-3) __ Ifthe two bits differ, then the multiplicand i i. Tram the Are sister, depending fon hia a fa to or subtracted 12, After addition or subbras ‘ion right shift occurs such Aer ACA, .) Snot ony shifted into A, ps Care bit Oye required to preserve the sign ofthe number inA and @ int FG] Draw the data path of 2's compliment multiplier. Give ‘-tson multiplication algorithm for 2's compli . " 5 _ pliment fractions. “Alsoillustrate the algorithm for 2’s compliment fraction by a suitable example. i AKTU 2017-19, Marks 07 hh of 2's compliment muitiplier : Refer Q. 2.3, Page 2-4B Ans Datapatl Unit-2. | Robertson algorithm : Rone 0, B Multiplicand Q « Multiplier and count «1. b IfQy= then perform A < A +B. & Shift right register F-A.Q by 1 bit 1’ Be 11 AND Q(0] OR F and count <— count - 1. 4, Ifeount > 1 Repeat steps 2 and 3, otherwise if Qy = 1 then perform ACA-Band set Q [0] =0. For example : We perform the multiplication of fraction Multiplicand = 0.625 Multiplier = 0.5 Equivalent binary representation 0,625 = 0101 ’s complement representation — 0.625 = 1010 + 1 (— 0.625) = 1011 Equivalent binary representation + 0.5 = 0100 2complement representation 0.5 = 1011+ 1-0.5= 1100 B o1o0ot Final product 0,625 « 05 = 09125, TOL = 0100 = 00101000Que 2.6, Answer 15=01111 Show step by step the m™ Booth’s algorithm when (+ 15) and - 18) ‘ume 5-bit registers that hold signed ™ ~ 13 = 2's complement of 13 = 1001 1 jriplication PFOCCSS uy, numbers are Mult, umbers+ FETT 201416, Man) Multiplicand (M) = 10011 eS TG,a [overation | SO A Enel i Tore 00000 o {| —_4 101 (5) } 10001 0 | Aca-M shift | 100 11000 1_| Shift {100 (4) | fms T [shit on gy o1011 1 [AcAeM 00101 o | shift | o10 fonts 0 | shit. | 001 @ 10011 o_[AcA-M 11001 1] shift [000 Result = (11001 Que 2.7. | Show the contents of the registers E, A, Q, SC during the process of multiplication of two binary numbers 11111 (multiplicand) 10101 (multiplier). The signs are not included. 's complement of +195) AKTU 2016-17, Marks 10 Answer Multiplicand B = 11111 E A Qn lisa 0 0000 | 10101 | 101 Q, = 1; add B 00000 11 Mit Shift right BAQ 0 o1i1i_| 11010 | 100 Q,=1iaddB out lu 00000 Shift right EAQ 0 0000 | o1o1 | o1 Q.= shift right EAQ 0 00000 00110 010 Q, = 0; shift right EAQ 0 oooo0 | ooo11 | 001 Q, if right EAQ 0 00000 | 00001 | 000ization & Architect ‘Computer Organizat are 2.9 B (CS/IT-Sem-3) Guess. | Show the multiplication process using Booth’s algorithm when the following numbers are multiplied: (- 13) by (+8) ‘Answer ‘True binary equivalent of + 8 = 01000 ‘True binary equivalent of + 13 = 01101 1’s complement of + 13 = 10010 +1 2's complement of + 13 = 10011 (-13) Multiplier = 01000 Multiplicand (B) = 10011 | A | @ | Ser Operation SC 90000 _| 01000 0 100 | 00 __| 00100 0 Ashr AQQ, ¥1 {_ 0000 _| 00010 0 Ashr AQQ, «1 ou | 00000 | 00001 0 Ashr-AQQ, .1 010 |-__+ = | 1101 | 00001 0 Add B +1toA 001 00110 | 10000 i Ashr AQQ,_1 1001 | 10000 1 Add BtoA 000 1100 | 11000 | “0 Ashr AQ, ,1 Result: 11] 11000 = ~ 104 (2's complement of (+ 104)) 11000 = ~ 104 2's compen Que2s, | Draw the flowchart of Booth’s algorithm for iplication process using Booth’s AKT 2018-19, Marks 07 algorithm for (- 7) x (+3). Answer Flowchart of Booth’s algorithm for multiplication + Refer Q. 2 Page 2-4B, Unit-2. Multiplication : Multiply (- 7) * (+ 3) Convert (-7) into 2's complement form oul 1's complement of (+7) adding 1 2x complement of (+ 7) (48) = 00112-10 B (CS/IT-Sem-3) Arithmetic and Logic Unjy ae) NN initial values 0111 add 0111 toA 0011 1001 1 Ashr ou AQ, Quer 0001 1100 1 Ashr AQ, Q,,, | 010 1001 add 1001 1010 1101 0110 0 Ashr AQ, @,,; | 001 110 1011 0 Ashr AQ, Q,,, | 000 Answer is 11101011 (7) x (+ 3) =~ 21 = 11101011 (2's complement of + 21) Que example. Answer 10. | Explain array multiplier method with the help of 1. The combinational circuit implemented to perform multiplication array multiplier. 2. The generalized multiplication process for array multiplier for two unsigned integers : Multiplicand A = A,A,A,Ay and multiplier B=B,B,B,B, is shown in Fig. 2.10.1 Ay A, Ay Ay + B, B, By By A,By A,B) A,B, AyB, <— PPO AB, A,B, A,B, AgB, <----—--- PPI A,B, A,B, A,B, A,B, pp2 A;B, A,B, A,B, AQB, PP3 <-- » Py Py + PPs Fig. 2.10.1, Manual multiplication proéess, on the corresponding multiplier bit is called Partial Product (PP) 4. Each partial product consists of four product components. Pye ° a P\= A,B, +A,B, alled | Each shifted multiplicand which is multiplied by either 0 or 1 depending. The eubsequent adders add each partial product with, 2-11B (CS/IT-Sem-8) Py = AgBy+A,B +. P,= A,B, +A,Bi AB, a 1 +AB, + y= AyD, +A,B,+ AB ACB a Ps= ABo +. A,B, oduct myer eh The component bit is a logical AN! ie multiplicand bit A, i., B,xA; Since the nee ans B, and coincide in the 1 bit case. ic and logic products Fig. 210.2 shows the circuit to ada the prod product components are represented havens Here, the make space. and separated to Pro PP FETT 1 mnsenan Bit of incoming partial product \Fig, 2.10.2. Block diagram of © jatational ulEIpLCE) sTefilladder occsrepresentedby square block. Thecariesineachparta product row of full adders ‘are connected to make 4bit ripple adder. Thus, the first 4-bit ripple adder adds the first two rows of product components to produce the first. partial product. ‘The carry output generated is: propagated to the most: significant product component used to produce the next partial product. the next product component.arithmeticand Loge Ung 2-128 (CS/T-Sem-3) : on-restori Que 2.11. ] Write down the step for restoring and a division operations. Answer ; Restoring division operation: 'ep 1: Shift A and Q left one binary position. A(ACA-B), | Step 2 : Subtract divisor fom A and place answer back IN 1 At Step 3: Ifthe sign bit ofA is 1, set Q, to 0 and add divis _ restore A); otherwise, set Q, 0 1. Featd 4: Repeat steps 1, 2 and 3 upto n times. lon-restoring division operation : Peet Step 1: Ifthe sign of A is 0, shift A and @ lft one bit position and subtra divisor from A; otherwise, shift A and @ let and ald distr Step 2:If the sign of A is0, set @, to 1; otherwise, set Qo Step 3: Repeat steps 1 and 2 forn times. Step 4: Ifthe sign of A is 1, add divisor to. proper positive remainder in A a« the end of» cycles. Que 2.12. | Draw the flow chart for restoring and non-restoring division operation. Answer Flowchart for restoring Step 4 is required to leave the sion operation is shown in Fig, 2.12.1. 3. hier [i bso Qi Count «n SRIAAT i - eet + | No Ye. Za] MiGeo ‘ASB (Count «Count = 1 Quitient in Q Remainder in A 2.12.1, Flow chart for restoring division operation.Organization & Architecture Computer 2-13B (CS/IT-Sem-3) ‘A flow chart for non-restoring division o, peration is shown in Fi g- 2.12.2. Ae Be Divisor D « Dividend Count is oD Fig. 2.12.2. Flow chart for Guedis.] Draw the data path of sequential n-bit binary divider. Give the non-restoring division algorithm for unsigned integers. Also illustrate algorithm for unsigned integer with a suitable AKTU 201 }, Marks 07 example.Arithmetic and Logic Unit 2-14B (CS/T-Sem-3) a ary divider : Datapath of sequential n-bit bin 16 Algorithm for non-restoring division : Refer Q. 2.11, Page 2-128, Unit-2. For example, consider 4-bit dividend and 2-bit divisor : 1010, Divisor = 0011 Q Register Initially 0 0 0 0 0 10 1 0 « Dividend a 0 ce O10: a First Cycle set@ Gi i 1 0 o 1 0f0 gun 1 1 1-0 0 1 ofo Add 0 0 0 11 Second Cycle set Qy ® tere 10 ge tt 0 aad 0 0 OE : Third Cycle wa Gera? ° Pf] fe shit 0 0 1 0 0 folfa Subtrat 1 1 1 0 2 oo Fourth Cycle Remainder (Pig. 248.204)Organization & Architecture Computer 215B (CS/IT-Sem-3) seon example after 4 cycles egistor A bali ; Positive and hence step 3 is not ae Perform the division process of 00001111 by 0011 (use a Dividend in Q,A shl _EAQ 0 Sad Bel or 1110 | 100 E=0, leave @, 0 110 | 1110 add B 0011 wstore partial remainder | 1 | 0001 . ou sh! _EAQ 0 | 0011 | 1100 add B+ 1101 E=1,set Q, tol 1 | 0000 | 1101 sh! _EAQ 0 0001 | 1010 | 010 add B+ i101 E=0, leave Q, 0 | 1110 | 1010 r add B oot 001 estore partial remainder | 1 | 0001 shl EAQ 0 0011 0100 add B+ 1101 000 1 | 0000 } 0102 Remainder | Quontient E=1,set@, tol GuedAs.| What do you mean by overflow 2 Describe the overflow detection. Answer Overflow: Ty Orerfow is a condition when two numbers with n digits are added and the cum is.a number occupying” + 1 digit : BT gmputer because the number of bits 2 Overflow is a problem in digit by an n-bit word. types of overflow : ‘ '¢ overflow refers to integer Jarger than that can cannot be accommodated 3. There are following three i. Positive overflow ¢ Positiv representations and refers toa 5M fe represented in a given number of bits. ymber that is enterPS snmetic and Logi 16B (gry, : ‘vithmetic Bie Uni sto floating Exponent overflow : Exponent overflow Be thatexceeda Tepresentations and refers to. positive &™P Maximum possible exponent value. werflow occurs When Significand overflow : Siguficand 970" Te sign results ig addition of two significant number of a carry out of the most significant bit. iii, ving the Qverflow detection : An overflow canbe detected bY ae TNE Ts cay into the : ; t equal, an ove sign bit position, If these two carries are MO Tfloy, condition is produced, For example : 4] PART-4 i ee i Floating Point Arithmetic Operations, Arithmetic and Logic — Unit Design. j Questions-Answers co point numbers. Answer | Answer Th +35 0 100011 -35 1 01101 +40 0 101000 -40 1 011000 <5 Doon 7 io 10101 / ‘Two carries are explicitly shown. Ifthe two carries are applied to exclusive OR gate, an overflow would be detected when the output og the gate is 1, Long Answer Type and Medium Answer Type Questions jue 2.16. | Explain the basic format used to represent floating e floating point representation has three fields : ‘The sign bit : The sign bit determines whether the number is negative or positive. 0 denotes a positive number and 1 denotes a negative number. ‘The exponent : The exponent field needs to represent both positive and negative exponents. To do this, a bias is added to the actual exponent in order to get the stored exponent. For IEEE single precisa the exponent field is of 8 bits and has a bins value of 127 Fer double precision, the exponent field is of 1] bits, and has a bias of 1023. The mantissa : The mantissa, also known ue the significand, represents the precision bits ofthe number, It jg ‘composed of an implicit leading bit and the fraction bits, “|ization & Architecture Computer O76" 2-17B (CS/IT-Sem-3) The gener structure of floating point number M Single precision feito H/- — 28 bits: z Bal : M Double precision je 1 bit E11 Bits 52 bits significant (mantissa) digits, E is exponent, B is scaling where 5 is 7 hnis 2 for binary number, 10 for decimal number. factor, whid weaamag] Write the steps for various floating point arithmetic operations: Taw | s rious floating point arithmeti ' Roa aia ‘and Gibeactca : hmetic operations are: Check for zeros ‘Align the mantissas ‘add or subtract the manti lize the result. tep Step 2: Add the expone Stop 3: Multiply the manti the product and determine the sign of the result. iii, Cheek for zeros. Step 2: Subtract the exponents Step 3: Divide the mantissas and determine the sign of the result. Step 4: Normalize the result Que 2.18. Explain the function of arithmetic circuit with the help Step of cireuit diagram. se operation of both addition and subtraction. It 4, and B, B, B, By in arithmetic circuit, of the full adder, is used :Itisan nnected with C, of addition and subtraction. controlled inverters. 7 Fig. 2.18.1. Symbol of EXOR gate.2-18 B (CS/IT-Sem-3) Arithmetic and Logie Uni Table : 2.18.1. Truth table of EXOR Gate. Input | Output fe feo ly Hl lolo la, x 0 1 0 1 Ag By Ag By Ay By a a g ADD/SUB r Fa Sf Fa il FA ip ce Cour Ss 8, Sy So Fig. 2.18.2. A d-bit parallel binary adder/subtractor. 3. If C= 0, the input variable X is either 0 or 1 will be transferred to output terminal. 4, IfC=1, the input variable X is either 0 or 1 will be complemented and transferred to output. By using this EXOR gate property we use this gate in the 4-bit adder / subtractor circuit. Case 1 : ADD/SUB = 1 i. Now, the controlled inverter (EXOR gate) produces the 1’s complement of B, B, B, By. Since 1 is given to C,, of the LSB bit of the adder, it is added to the complemented output of EXOR gate output, it is equal to 2's complement of B, B, B, By. ii The 2's complemented B, B, B, B, will be added to A, A, Ay Ay to produce the sum, the produced output of S, S, S, S, is the difference between A, A, A, A, and B, B, B, By. Case 2 : ADD/SUB = i. Now, the controlled inverter is transferred B, B, B, By four bit to full added with A, A, A, Ay to produce sum and carry. adder, this 4 bi Que 2.19. | Add -35 and -31 in binary using 8-bit registers, in signed 1's complement and signed 2’s complement. AKTU 2014-15, Marks 05 Answer sign bit ‘True binary number of True binary number of| gomputer Organization & Architect 2198 1's complement of oe re 018 (CAAT-Bem-2) | 1's complement of tet uF 1100 Typo oui) t Discard the g's Complement of a5 Th 9 1 ; 100 wim o1 Q's Complement of ~31- Tee 00 th 11100 ‘Adding 2s complement of ~35 and 31 - A 1 + eee jt nel t 7 13110 Discard sign bit Que 2.20. Draw the block diagram of control unit of basic ter. Explain in detail with control timing diagrams. AKTU 2016-17, Marks 15 comput | the carry Answer 1. The control ui control logic gates. 2. The instruction in nit consists of 2 decoders, 1 sequence counter, number of IRs divide into 3 parts: 15" bt toa flip-flop (FF) called I, Operation code, and bits Oto Ll. ‘The Op-code is decoded using 3#8 decoder (D, to D,). Bits Oto LL are applied to the control logic gates. ‘The output ofa 4-bit sequence counter are decoded into 16 timing signals (1, t0T )- 43, The SC responds to the posit clock. Initially CLRV P je active, in 1 positive transition SC = (0 timing signal Tis active as the output of the decoder. Thisin tum triggers those registers whose control inputs are connected to Ty. SCis: incremented and| the timing signals Ty, sn ee created. This continues ‘unless SCiis cleared. We can clear the SC with decoder output D, active, denoted as: Dsl, tive transition ofthe sceithe ane La 2-208 (CHT -Hom tion Rogintor (HO | no | fomer input | Tate (ie ai A aii [ f ; mtd | Control | Control foutputs 1x6 Decoder re -¢—— Increment (INR) | 4—— Clear (CLR) | 4— Clock ram ‘of control unit. vecomess active at the end of'T, that implements the contro 2.20.1, Block ding 1m the operation decoder b 4, Output D, f When T, isa the output of AND gate ents fanction DyT, becomes active. This signal applied to CLR input of SC, 5. Example of register transfer : Ty : AR © PC (Activities in Ty will be, Content of PC p $5) = 010, LD of AR is active, transfer ct ‘reneition, Ty is inactive, T, gets active) 6. -bit sequence counter and 4 16 decoder, dorcleared. Tyy Ty» Toy Tyr Ty Tw For example : Assume: At time Ty, coder output D, is active. SC is cleared to 0 if de« Timing diagram : Que 2.21, | Draw a flowchart for adding and subtracting two fixed point binary numbers where negative numbers are signed 1's | complement presentation. ‘AKTU 2018-19, Marks 07221 B (CS/IT-Sem-3) ‘Add operation END floating point numbers. Que222, | Explain IEEE standard for oR - are represen! in computer also give ating point umber format. numbers How floating point 32-bit flo IEEE 754 standard‘Arithmetic and Logic Unig paamcarrsem IEEE : tic (IEEE 754) is a technica, ‘The IEEE standard for floating point arithmet standard for floating point computation. 2 IBEE 754 numbers are divided into two types: . Single precision: . o . "The! numbers in 32-bit are single precision. i. The floating point 32 bits 31:30 23.22 9 s[ FE Sign of number B-bit signed 23-bit mantissa fraction + Signifies 0 exponent = Signifies 1 Fig. 2:22:11 Single precision. presented 32-bit floating point number in single precision is re as + 1M x 2°. noo Therelationship between E and B’ in single precision is given as B' = E +127. iv. The 8-bit assigned for exponent E’ (Modified exponent) is in the range 0 < B < 256 for normal values. Thus the actual exponent is in the range — 127 1 (0.125),» = (0.000), (1460.125),, = (10110110100.001), Step 2: Normalize the number. '10110110100.001 = 1.0110110100001 x 2° Single precision : For agiven floating point number, 1.0110110100001 x 2° S=0 E=10 ; M = 0110110100001 Bais (or) modified exponent for single precision B= l2i+E = 127+ 10 13%, = 10001001, Numbers single precision format2-24 B (CSAT-Ser Double precision + For Qi. Ans. Q2 Ans: Q3. Ans. Qs Ans, 110110100001 x 2"? 5: M =0110110100001 Following questions are very ‘arithmetic and Logic Uni mfr bit +8 bits [100010011 9110110100001. a given number, r double precision 10 + 1023 = (1033), = (10000001001), sf (st bits——| bi au Mt bits J J100000010014 0110110100001....0 important, These questions be asked in your. SESSIONALS as well as UNIVERSITY EXAMINATION. ee Describe sequential Arithmetic and Logic Unit (ALU) using) proper diagram. Refer Q. 2.1 Explain Booth’s multiplication algorithm in detail. Refer Q. 2.3. Draw the data path of 2's compliment multip! Robertson multiplication algorithm for 2’s compliment fractions, Also illustrate the algorithm for 2's compliment fraction by a suitable example. Refer Q. 2.5. Show step by step the multiplication process using, Booth's algorithm when (+ 15) and (~ 13) numbers are multiplied ‘Assume 5-bit registers that hold signed numbers. may x, Give the Refer Q. 26.Computer Organiz ation & Architecture ee ae show the contents of the re 25 B (C8/IT-Bem-3) Qo. a8 Q6 Pd Qt. Ans Qs Qo. Q.10. Q iL Q.12. Q.13. _ when the following numbers a rocess of multi; ister peltiplicand) ior ean Me two t eae SC during the Refer Q. 2.7. bs cr). The ignnanenen aut included, Show the multiplication process using Boot th’s algorithm re multiplied 13) by (+8) Refer Q. 2.8. Draw the flowchart of Booth's and show the multiplicati algorithm for (-7) x (+3), Refer Q. 2.9. algori Algorithm for multiplication Process using Booth’s Draw the data path of sequenti : quential n-bit bis . the non-restoring division ae binary divider. Give Also illustrate algorithm for unsi for unsigned integers suitable example. igned integer with a Refer Q. 2.13. Perform the division process of 0000 dividend of 8 bits). eee aes Refer Q. 2.14. ‘Add -35 and - 31 in binary using 8-bit registers, in signed I's complement and signed 2's complement. Refer Q. 2.19. block diagram of control unit of basic com] fh control timing diagrams. Draw the puter. Explain in detail witl Refer Q. 2.20. Draw a flowchart for addin: binary numbers where ne! ment presentation. tracting two fixed point g and sub’ ers are signed 1’s gative num comple Refer Q. 2.21 epresented in computer, mber How floating int numbers are r¢ n n also give THEE 754 standard 32-bit floating point nu format. Refer Q. 2.22. 09SQ-3B (CS/T.Sen, 2) Computer Organization & Architecture Arithmetic ang Logic Unit (2 Marks Questions) 21. What is look ahead carry adders ? a . ABE A look ahead carry adder is a type of adder which improves the ry ine cay Deed by reducing the Amount of time required to determine carry bits, ANS! Arithmetic cireuit It is a digital circuit which performs only arithmetic. ‘Oper: ations such as addition, subtraction ete. . t's It is a digital circuit which perform only logic 's AND, OR and NOT ete, ii, Micro-operation AKTU 2016-17, Marke 03 Ang i RTL: Register Transfer Language (RTL) is a convenient. tool for describing the internal rreanization of digital computers in concise and precise manner, It can also be used to facilitate the design Process of digital systems, ii, Micro-operation « The processor unit has soc rations to execute the major Phases Set of operations called micro-operations 24. What is the main advantage of RTL? to perform a set of of instruction eycle these'.Sem-3) pics. sat Arithmetic and Logie Uni of having ma a News wing reason? “lPessin, ® Modes in i The way of OPEEONES AF ogg dur; eee dependent on the adaresting pee tT program execution i ‘The addressing mode g e is due il Pecifies a rule or jst ction, the address field of the MSTUction beso ntetPFeting or modifying referenced. 'e the operand is actually How subtraction operation and 26 simplified inn digiten system °tMe® operations ean be Subtraction operation and other gery Pil tm by sg emp ae pain system, there are two tyneq of complemen t°& For each number i. r'scomplement i Vs compler 21. How many flip-lops are need, pone “4385 in BCD representauigeets For 4-bit decimal code, there are 4, i A For 4980 in BCD representaanee thereat Stone acne bit re flops used, State the condition for oink oe ormalized, int number to become A floating-point numbe = significant digit of the for 4.bit, decimal code and floating.» T is said ( mantissa is ny 29, When exponent overflow ang Anis Exponent overflow occurs shen a maximum possible exponent value Exponent underflow occurs when a Negative exponent exceeds the maximum possible exponent value, In such cases, the number is designed is zero, 0 be normal ized if the most 1on-zer9, underflow oecur ? ive expone ‘at exceeds the 210, Perform the following operation on signed numbers using Yscompliment method :(56),,+(-27),- AKTU 2017-18, Marks 02 111000 (binary form) 0111000 (signed binary form) 011011 (binary form) 100100 (1's complement) +1 56 = ame 5 100101 (2's complement) =2 1100101 (signed binary form) ow, (+ 56)g +(-27),g = 0111000 . * °° s100101 @oo11101 ; = (0011101), (signed binary number) (29,5 O80