COA

Module 1
Class: SE IT Sem: IV C Scheme

Prepared by
Dipashri Sonawale
Syllabus
NUMBER SYSTEM
DECIMAL NUMBER SYSTEM
BINARY NUMBER SYSTEM
Tutorial Problems
Complements
Complements : Eg – 1100 0101
 Complements : Eg – 1100 0101
• 1’s Complement :
1100 0101
0011 1010

• 2’s Complement: 0+0 =0 , 0+1 =1, 1+0 =1, 1+1 = 0,Carry=1

0011 1010
+ 1
_________
0011 1011
Representation of Negative Numbers
Signed Magnitude Representation
Signed Magnitude Representation
Introduction: Signed Binary Numbers
 Introduction: Signed Binary Numbers
• Magnitude:
 Introduction: Signed Binary Numbers
• Example: Explanation
 Introduction: Signed Binary Numbers
• Example:
THANK YOU!!!
 COA
Module 1
Class: SE IT Sem: IV C Scheme

Prepared by
Dipashri Sonawale
Syllabus
Half Adder
Half Adder
Half Adder
Full Adder
Full Adder
Full Adder
 Half Subtractor
• Half Subtractor is a combinational logic circuit.
• It is used for the purpose of subtracting two single bit
numbers.
• It contains 2 inputs and 2 outputs (difference and borrow).
 Half Subtractor Designing
• Half subtractor is designed in the following steps-
• Step-01:
• Identify the input and output variables-
• Input variables = A, B (either 0 or 1)
• Output variables = D, b where D = Difference and b = borrow
• Step-02:
• Draw the truth table-
Inputs Outputs
A B D (Difference) b (Borrow)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 Half Subtractor Designing
• Step-04:
• Draw the logic diagram.
• The implementation of half subtractor using 1 XOR gate, 1 NOT gate and 1 AND
gate is as shown below-
 Limitation of Half Subtractor
• Limitations:
• Half subtractors do not take into account “Borrow-in” from the
previous circuit.
• This is a major drawback of half subtractors.
• This is because real time scenarios involve subtracting the multiple
number of bits which can not be accomplished using half subtractors.
• To overcome this drawback, Full Subtractor comes into play.
 Full Subtractor
• Full Subtractor is a combinational logic circuit.
• It is used for the purpose of subtracting two single bit
numbers.
• It also takes into consideration borrow of the lower significant
stage.
• Thus, full subtractor has the ability to perform the subtraction
of three bits.
• Full subtractor contains 3 inputs and 2 outputs (Difference and
Borrow) as shown
 Designing a Full Subtractor
• Full subtractor is designed in the following steps-
• Step-01:
• Identify the input and output variables-
• Input variables = A, B, Bin (either 0 or 1)
• Output variables = D, Bout where D = Difference and Bout = Borrow
 Designing a Full Subtractor
• Full subtractor is designed in the following steps-
• Step-02:
• Draw the truth table-
Inputs Outputs
A B Bin D (Difference) Bout (Borrow)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
 Designing a Full Subtractor
• Step-04:
• Draw the logic diagram.
• The implementation of full adder using 1 XOR gate, 3 AND gates, 1 NOT gate and
1 OR gate is as shown below-
THANK YOU!!!
1. Fundamentals of Logic Design
Combinational Circuits
Multiplexer, Demultiplexer, Encoder & Decoder

Prepared By: Dipashri Sonawale

Multiplexer in Digital Electronics - Javatpoint
Syllabus
 Multiplexer
• A multiplexer is a combinational circuit that has 2 n input lines
and a single output line.
• Simply, the multiplexer is a multi-input and single-output
combinational circuit.
• The binary information is received from the input lines and
directed to the output line.
• On the basis of the values of the selection lines, one of these
data inputs will be connected to the output.
• A multiplexer is also treated as Mux.
 Multiplexer
• Types of Multiplexers:
• 2×1 Multiplexer
• 4×1 Multiplexer
• 8 to 1 Multiplexer
• 16 to 1 Multiplexer
 2x1 Multiplexer
• In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection

line, i.e., S0 and single outputs, i.e., Y.

• On the basis of the combination of inputs which are present at the

selection line S0, one of these 2 inputs will be connected to the output. 

• The block diagram and the truth table of the 2×1 multiplexer are given
below.
 2x1 Multiplexer
• The logical expression of the term Y is as follows:
Y=S0'.A0+S0.A1
• Logical circuit of the above expression is given below:
 4x1 Multiplexer
• In the 4×1 multiplexer, there is a total of
• four inputs, i.e., A0, A1, A2, and A3,

• 2 selection lines, i.e., S0 and S1 and

• single output, i.e., Y.

• On the basis of the combination of inputs that are present at the

selection lines S0 and S1, one of these 4 inputs are connected to
the output.
 4x1 Multiplexer
• The block diagram and the truth table of the 4×1
multiplexer are given below.
 4x1 Multiplexer
• The logical expression of the term Y is as follows:
Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3
• Logical circuit of the above expression is given below:
 8x1 Multiplexer
• In the 8 to 1 multiplexer, there are
• total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7,

• 3 selection lines, i.e., S0, S1and S2 and

• single output, i.e., Y.

• On the basis of the combination of inputs that are present at

the selection lines S0, S1, and S2, one of these 8 inputs are
connected to the output. 
 8x1 Multiplexer
• The block diagram and the truth table of the 8×1
multiplexer are given below.
 8x1 Multiplexer
• The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3

+S0'.S1'.S2 A4+S0.S1'.S2 A5

+S0'.S1.S2 .A6+S0.S1.S3.A7

• Logical circuit of the above expression is given

below:
 8x1 Multiplexer
• Logical circuit of the above expression is given below:
 8x1 Multiplexer using 4x1 and 2x1 MUX
• We can implement the 8×1 multiplexer using a lower
order multiplexer.
• To implement the 8×1 multiplexer,
• we need two 4×1 multiplexers and
• one 2×1 multiplexer.
• The 4×1 multiplexer has 2 selection lines, 4 inputs, and 1
output.
• The 2×1 multiplexer has only 1 selection line.
• For getting 8 data inputs, we need two 4×1 multiplexers.
• The 4×1 multiplexer produces one output. So, in order to
get the final output, we need a 2×1 multiplexer. 
 8x1 Multiplexer using 4x1 and 2x1 MUX
• The block diagram of 8×1 multiplexer using 4×1 and 2×1
multiplexer is given below.
 De-Multiplexer
• A De-multiplexer is a combinational circuit that has only 1 input
line and 2N output lines.
• Simply, the multiplexer is a single-input and multi-output
combinational circuit.
• The information is received from the single input lines and
directed to the output line.
• On the basis of the values of the selection lines, the input will be
connected to one of these outputs.
• De-multiplexer is opposite to the multiplexer.
• De-multiplexer is also treated as De-mux.
 De-Multiplexer
• Types of De-Multiplexer
• 1x2 De-Multiplexer
• 1x4 De-Multiplexer
• 1x8 De-Multiplexer
• 1x16 De-Multiplexer
 1x2 De-Multiplexer
• In the 1 to 2 De-multiplexer, there are
• only two outputs, i.e., Y0, and Y1,

• 1 selection lines, i.e., S0, and

• single input, i.e., A.

• On the basis of the selection value, the input will be connected

to one of the outputs.
 1x2 De-Multiplexer
• The block diagram and the truth table of the 1×2 multiplexer are given
below.
 1x2 De-Multiplexer
• The logical expression of the term Y is as follows:
Y0=S0’.A
Y1=S0.A
• Logical circuit of the above expressions is given below:
 1x4 De-Multiplexer
• In 1 to 4 De-multiplexer, there are
• total of four outputs, i.e., Y0, Y1, Y2, and Y3,

• 2 selection lines, i.e., S0 and S1 and

• single input, i.e., A.

• On the basis of the combination of inputs which are

present at the selection lines S0 and S1, the input
be connected to one of the outputs.
 1x4 De-Multiplexer
• The block diagram and the truth table of the 1×4 multiplexer are given
below.
 1x4 De-Multiplexer
• The logical expression of the term Y is as follows:
Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A
• Logical circuit of the expressions
 1x8 De-Multiplexer
• In 1 to 8 De-multiplexer, there are
• total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7,

• 3 selection lines, i.e., S0, S1and S2 and

• single input, i.e., A.

• On the basis of the combination of inputs which are

present at the selection lines S0, S1 and S2, the input
will be connected to one of these outputs. 
 1x8 De-Multiplexer
• The block diagram of the 1×8 de-multiplexer are given
below.
 1x8 De-Multiplexer
• The truth table of the 1×8 de-multiplexer are given below.
 1x8 De-Multiplexer
• Logical circuit of the above expressions is given below:
1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer
• The block diagram of 1×8 de-multiplexer using 1×4 and
1×2 de-multiplexer is given below.
Decoder
Block Diagram of Decoder
2 to 4 Line Decoder
2 to 4 Line Decoder…cntd
3 to 8 Line Decoder
3 to 8 Line Decoder…cntd
3 to 8 Line Decoder…cntd
 Encoder
• The combinational circuits that change the binary
information into N output lines are known as Encoders.
• The binary information is passed in the form of 2N input
lines.
• The output lines define the N-bit code for the binary
information.
• In simple words, the Encoder performs the reverse
operation of the Decoder. 
 Encoder
• Types of Encoders
• 4 to 2 line Encoder
• 8 to 3 line Encoder
• Decimal to BCD Encoder
• Priority Encoder
 4 to 2 line Encoder
• In 4 to 2 line encoder, there are
• total of four inputs, i.e., Y0, Y1, Y2, and Y3, and

• two outputs, i.e., A0 and A1.

• In 4-input lines, one input-line is set to true at

a time to get the respective binary code in the
output side.
 4 to 2 line Encoder
• Below are the block diagram and the truth table of the 4 to 2 line
encoder.
• Block Diagram:
 4 to 2 line Encoder
• The logical expression of the term A0 and A1 is as follows:
A1=Y3+Y2
A0=Y3+Y1
 8 to 3 line Encoder
• The 8 to 3 line Encoder is also known as Octal to
Binary Encoder.

• In 8 to 3 line encoder, there is a

• total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and

• three outputs, i.e., A0, A1, and A2.

• In 8-input lines, one input-line is set to true at a time

to get the respective binary code in the output side.
 8 to 3 line Encoder
• Below are the block diagram and the truth table of the 8 to
3 line encoder.
 8 to 3 line Encoder
• Truth Table:
 8 to 3 line Encoder
• The logical expression of the term A0, A1, and A2
are as follows:

A2=Y4+Y5+Y6+Y7

A1=Y2+Y3+Y6+Y7

A0=Y7+Y5+Y3+Y1
 8 to 3 line Encoder
• Logical circuit of the above expressions is
given below:
 8 to 3 line Encoder
• Uses of Encoders:
[Link] systems are very easy to use in all digital
systems.

[Link] are used to convert a decimal number

into the binary number. The objective is to perform a
binary operation such as addition, subtraction,
multiplication, etc.
 COA
Module 1
Class: SE IT Sem: IV C Scheme

Prepared by
Dipashri Sonawale
Syllabus
Minimization Of Boolean Expressions-
• Methods
• For a boolean expression consisting of n-variables, number of cells
required in K Map = 2n cells.
 K-MAP(Karnaugh Map)
• a systematic way of simplifying Boolean expressions.
• can minimize Boolean expressions of 3, 4 variables very easily using K-
map without using any Boolean algebra theorems. 
• take two forms Sum of Product (SOP) and Product of Sum (POS)
• is table like representation but it gives more information than TRUTH
TABLE.
• We fill grid of K-map with 0’s and 1’s then solve it by making groups.
•  is used for expressions containing 2, 3, 4, and 5 variables.
• In K-map, the number of cells is similar to the total number of variable
input combinations.
• For example, if the number of variables is three, the number of cells is
23=8, and if the number of variables is four, the number of cells is 24.
 K-MAP(Karnaugh Map)
• 2 Variable K-Map
• The number of cells in 2 variable K-map is four, since the number of
variables is two.
• There is only one possibility of grouping 4 adjacent min terms.
• The possible combinations of grouping 2 adjacent min terms are {(m0,
m1), (m2, m3), (m0, m2) and (m1, m3)}.
• The following figure shows 2 variable K-Map.
 K-MAP(Karnaugh Map)
• 2 Variable K-Map
• Two variable K Map is drawn for a boolean expression consisting of
two variables.
• The number of cells present in two variable K Map = 22 = 4 cells.
• So, for a boolean function consisting of two variables, we draw a 2 x 2
K Map.
• Two variable K Map may be represented as-
 K-MAP(Karnaugh Map)
• 3 Variable K-Map
• The number of cells in 3 variable K-map is eight, since the number of
variables is three.
• The following figure shows 3 variable K-Map.
 K-MAP(Karnaugh Map)
• 3 Variable K-Map: SOP(Sum of Product) form
• There is only one possibility of grouping 8 adjacent min terms.
• The possible combinations of grouping 4 adjacent min terms are
{(m0, m1, m3, m2),
(m4, m5, m7, m6),
(m0, m1, m4, m5),
(m1, m3, m5, m7),
(m3, m2, m7, m6) and
(m2, m0, m6, m4)}.
• The possible combinations of grouping 2 adjacent min terms are
{(m0, m1), (m1, m3), (m3, m2), (m2, m0), (m4, m5), (m5, m7), (m7, m6), (m6,
m4), (m0, m4), (m1, m5), (m3, m7) and (m2, m6)}.
 K-MAP(Karnaugh Map)
• 3 Variable K-Map: SOP(Sum of
Product) form
• Three variable K Map is drawn for a
boolean expression consisting of three
variables.
• The number of cells present in three
variable K Map = 23 = 8 cells.
• So, for a boolean function consisting of
three variables, we draw a 2 x 4 K Map.
• Three variable K Map may be represented
as-
 K-MAP(Karnaugh Map)
• 3 Variable K-Map: SOP(Sum of Product) form
 K-MAP(Karnaugh Map)
• 3 Variable K-Map: POS(Product of Sum) form
 K-MAP(Karnaugh Map)
• 4 Variable K-Map
• The number of cells in 4 variable K-map is sixteen, since the number
of variables is four.
• The following figure shows 4 variable K-Map.
 K-MAP(Karnaugh Map)
• 4 Variable K-Map
• Four variable K Map is drawn for a boolean
expression consisting of four variables.
• The number of cells present in four variable
K Map = 24 = 16 cells.
• So, for a boolean function consisting of four
variables, we draw a 4 x 4 K Map.
 K-MAP(Karnaugh Map)
• 4 Variable K-Map: SOP(Sum of Product) form
 K-MAP(Karnaugh Map)
• 4 Variable K-Map: POS(Product of Sum ) form
 K-MAP(Karnaugh Map)
• 4 Variable K-Map: POS(Product of Sum ) form
Simplification of Boolean expressions using
Karnaugh Map
• K-map takes both SOP and POS forms.
• So, there are two possible solutions for K-map, i.e., minterm and maxterm
solution.
• Karnaugh Map Simplification Rules-
• To minimize the given boolean function,
• We draw a K Map according to the number of variables it contains.
• We fill the K Map with 0’s and 1’s according to its function.
• Then, we minimize the function in accordance with the following rules.
• Rule-01:
• We can either group 0’s with 0’s or 1’s with 1’s but we can not group 0’s
and 1’s together.
• X representing don’t care can be grouped with 0’s as well as 1’s.
Simplification of Boolean expressions using
Karnaugh Map
• Rule-02:
• Groups may overlap each other.
• Rule-03:
• We can only create a group whose number of cells can be represented in
the power of 2.
• In other words, a group can only contain 2n i.e. 1, 2, 4, 8, 16 and so on
number of cells.
Simplification of Boolean expressions using
Karnaugh Map
• Rule-04:
• Groups can be only either horizontal or vertical.
• We can not create groups of diagonal or any other shape.
Simplification of Boolean expressions using
Karnaugh Map
• Rule-05:
•  Each group should be as large as possible.
Simplification of Boolean expressions using
Karnaugh Map
• Rule-06:
• Opposite grouping and corner grouping are allowed.
• The example of opposite grouping is shown illustrated in Rule-05.
• The example of corner grouping is shown below.

• Rule-07:
• There should be as few groups as possible.
Simplification of Boolean expressions using
Karnaugh Map
• Steps to solve expression using K-map- 
[Link] K-map according to the number of variables.
[Link] minterms or maxterms as given in problem.
[Link] SOP put 1’s in blocks of K-map respective to the minterms (0’s
elsewhere).
[Link] POS put 0’s in blocks of K-map respective to the maxterms(1’s
elsewhere).
[Link] rectangular groups containing total terms in power of two like
2,4,8 ..(except 1) and try to cover as many elements as you can in one
group.
[Link] the groups made in step 5 find the product terms and sum them up
for SOP form.
PROBLEMS BASED ON KARNAUGH MAP
• Problem-01: Minimize the following boolean function-SOP Form

Z= ∑A,B,C(1,3,6,7) 
• Red group : A’C
• Green Group : AB
• Summing these product terms we get –
(A’C + AB)
PROBLEMS BASED ON KARNAUGH MAP
• Problem-02: Minimize the following boolean function-SOP
F(P,Q,R,S)=∑(0,2,5,7,8,10,13,15) 

• Red group : QS
• Green Group : Q’S’
• Summing these product terms we get –
(QS + Q’S’)
 PROBLEMS BASED ON KARNAUGH MAP
• Problem-03: Minimize the following boolean function-SOP

F(A,B,C)=π(0,3,6,7)
• Red group : A’+B’
• Brown Group : B’+C’
• Yellow Group : A+B+C
• Summing these product terms we get –
(A’+B’)(B’+C’)(A+B+C)
PROBLEMS BASED ON KARNAUGH MAP
• Problem-04: Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
• Solution-
• Since the given boolean expression has 4 variables, so we draw a 4
x 4 K Map.
• We fill the cells of K Map in accordance with the given boolean
function.
• Then, we form the groups in accordance with the above rules.
PROBLEMS BASED ON KARNAUGH MAP
• Problem-04: Minimize the following boolean
function-
F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
• Solution-
PROBLEMS BASED ON KARNAUGH MAP
•Problem-04: Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
• Solution-
Now,
F(A, B, C, D)
= (A’B + AB)(C’D + CD) + (A’B’ + A’B + AB + AB’)C’D + (A’B’ +
AB’)(C’D’ + CD’)
= BD + C’D + B’D’
 
Thus, minimized boolean expression is-
F(A, B, C, D) = BD + C’D + B’D’
PROBLEMS BASED ON KARNAUGH MAP
• Problem-05: Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
• Solution-
• Since the given boolean expression has 4 variables, so we draw a 4
x 4 K Map.
• We fill the cells of K Map in accordance with the given boolean
function.
• Then, we form the groups in accordance with the above rules.
PROBLEMS BASED ON KARNAUGH MAP
• Problem-05: Minimize the following boolean
function-
F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
• Solution-
PROBLEMS BASED ON KARNAUGH MAP
• Problem-05: Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
• Solution-
• Now,
F(A, B, C, D)
= (A’B’ + A’B + AB + AB’)(C’D + CD) + (A’B’ + AB’)(C’D’ + C’D)
= D + B’C’

• Thus, minimized boolean expression is-

• F(A, B, C, D) = B’C’ + D
PROBLEMS BASED ON KARNAUGH MAP
• Problem-06: Minimize the following boolean function-
• F(A, B, C, D) = Σm(1, 3, 4, 6, 8, 9, 11, 13, 15) + Σd(0, 2, 14)

• Solution-
• Since the given boolean expression has 4 variables, so we draw a
4 x 4 K Map.
• We fill the cells of K Map in accordance with the given boolean
function.
• Then, we form the groups in accordance with the above rules.
PROBLEMS BASED ON KARNAUGH MAP
• Problem-06: Minimize the following boolean function-
• F(A, B, C, D) = Σm(1, 3, 4, 6, 8, 9, 11, 13, 15) + Σd(0, 2, 14)

• Solution-
PROBLEMS BASED ON KARNAUGH MAP
• Problem-06: Minimize the following boolean function-
• F(A, B, C, D) = Σm(1, 3, 4, 6, 8, 9, 11, 13, 15) + Σd(0, 2, 14)

• Solution-
• Now,
F(A, B, C, D)
= (AB + AB’)(C’D + CD) + (A’B’ + AB’)(C’D + CD) + (A’B’ + AB’)
(C’D’ + C’D) + (A’B’ + A’B)(C’D’ + CD’)
= AD + B’D + B’C’ + A’D’

• Thus, minimized boolean expression is-

F(A, B, C, D) = AD + B’D + B’C’ + A’D’
THANK YOU!!!
1. Fundamentals of Logic Design
Sequential Circuits
Flip-Flops

Prepared By: Dipashri Sonawale

Syllabus
 Flip Flops
•  In the sequential logical circuit, the flip flop is the basic
storage element.
•  is a circuit with two stable states that can be used to store
binary data.
• The stored data can be changed by applying varying inputs.
• Types:
1. SR Flip Flop
2. J-K Flip-flop
3. D Flip Flop
4. T Flip Flop
 SR Flip Flop
• most common flip flop used in the digital system.
• flip-flop circuit has a set input (S) and a reset
input (R)
• In SR flip flop, when the set input "S" is true, the
output Y will be high, and Y' will be low.
• when you Set “S” as active, the output “Q” would
be high, and “Q‘” would be low.
• Once the outputs are established, the wiring of the
circuit is maintained until “S” or “R” go high, or
power is turned off.
 SR Flip Flop
• The truth table of SR Flip-Flop

S R Q Q’
0 0 0 1
0 1 0 1
1 0 1 0
1 1 ∞ ∞
 SR Flip Flop
• The circuit diagram of SR Flip-Flop
• In this circuit diagram, the output is changed (i.e. the
stored data is changed) only when you give an active clock
signal. Otherwise, even if the S or R is active, the data will
not change. 
 JK Flip Flop
• Due to the undefined state in the SR flip-flops, another flip-flop
is required in electronics.

• The JK flip-flop is an improvement on the SR flip-flop where

S=R=1 is not a problem.

• used to remove the drawback of the S-R flip flop, i.e., undefined
states.
 JK Flip Flop
• Truth Table: Block Diagram
 JK Flip Flop
• The input condition of J=K=1, gives an output inverting the
output state.
• In simple words, If J and K data input are different (i.e. high and
low), then the output Q takes the value of J at the next clock
edge.
• If J and K are both low, then no change occurs.
• If J and K are both high at the clock edge, then the output will
toggle from one state to the other. J
• K Flip-Flops can function as Set or Reset Flip-flops.
 JK Flip Flop
• Circuit Diagram
 D Flip Flop
• very popular with digital electronics.
• They are commonly used for counters and
shift registers and input synchronization.
• In the D flip-flops, the output can only be
changed at the clock edge, and if the input
changes at other times, the output will be
unaffected.
• The change of state of the output is
dependent on the rising edge of the clock.
• The output (Q) is the same as the input and
can only change at the rising edge of the
clock.
 D Flip Flop
• Truth Table
Clock D Q Q’
↓»0 0 0 1
↑»1 0 0 1
↓»0 1 0 1
↑»1 1 1 0
 T Flip Flop
• Toggle flip-flops

• A T flip-flop is like a JK flip-flop. 

• These are basically single-input versions of JK flip-flops.

• This modified form of the JK is obtained by connecting

inputs J and K together.

• It has only one input along with the clock input.

• These flip-flops are called T flip-flops because of their

ability to complement their state i.e. Toggle
 T Flip Flop
• Truth Table: T Q Q (t+1)
0 0 0
1 0 1
0 1 1
1 1 0
 Master-Slave Flip Flop
• In "JK Flip Flop", when both the inputs and CLK set to 1 for a
long time, then Q output toggle until the CLK is 1.

• Thus, the uncertain or unreliable output produces.

• This problem is referred to as a race-round condition in JK flip-

flop and
• avoided by ensuring that the CLK set to 1 only for a very short time.
 Master-Slave Flip Flop
• Circuit Diagram
 Master-Slave Flip Flop
• The master-slave flip flop is constructed by combining two JK flip flops.

• These flip flops are connected in a series configuration.

• In these two flip flops, the 1st flip flop work as "master", called the master
flip flop, and the 2nd work as a "slave", called slave flip flop.

• The master-slave flip flop is designed in such a way that the output of the
"master" flip flop is passed to both the inputs of the "slave" flip flop.

• The output of the "slave" flip flop is passed to inputs of the master flip
flop.
 Master-Slave Flip Flop
• In "master-slave flip flop", apart from these two flip flops,
an inverter or NOT gate is also used.

• For passing the inverted clock pulse to the "slave" flip flop,
the inverter is connected to the clock's pulse.

• In simple words, when CP set to false for "master", then CP

is set to true for "slave", and when CP set to true for
"master", then CP is set to false for "slave".
 Master-Slave Flip Flop
• Working:
• When the clock pulse is true, the slave flip flop will be in the isolated
state, and the system's state may be affected by the J and K inputs.
• The "slave" remains isolated until the CP is 1.
• When the CP set to 0, the master flip-flop passes the information
to the slave flip flop to obtain the output.

• The master flip flop responds first from the slave because the
master flip flop is the positive level trigger, and the slave flip flop is
the negative level trigger.
 Master-Slave Flip Flop
• Working:
• The output Q'=1 of the master flip flop is passed to the slave
flip flop as an input K when the input J set to 0 and K set to 1.
The clock forces the slave flip flop to work as reset, and then
the slave copies the master flip flop.
• When J=1, and K=0, the output Q=1 is passed to the J input of
the slave. The clock's negative transition sets the slave and
copies the master.
• The master flip flop toggles on the clock's positive transition
when the inputs J and K set to 1. At that time, the slave flip
flop toggles on the clock's negative transition.
• The flip flop will be disabled, and Q remains unchanged when
both the inputs of the JK flip flop set to 0.
THANK YOU!!!