PH3EC2 Vapour Growth and Epitaxial Growth Lecture 3: Epitaxial Growth Techniques Lecturers Dr. Shinoj VK 3.1 Epitaxial growth Epitaxy means the growth of a single erystal film on top of a crystalline substrate. For most thin film applications (hard and soft coatings, optical coatings, protective coatings) itis of litte importance. However, for semiconductor thin film technology itis crucial. Epitaxy is a greck word composed of two parts, namely pi and on and taxy which means on and ordered arrangement respectively-Thus epitaxy refers to ordered arrangement ou some materials; oriented growth of epilavers on a single crystalline substrate, so that the two atomic planes in contact have planar unit eells that match each other. Epitaxy is a term applied to the process of growing a monocrystalline film on a substrate. Epitaxy is termed as homoepitaxy when a crystal is grown epitaxially on a substrate of the same material, as in silicon film grown on silicon substrate. It is ‘termed as heteroepitaxy when a crystal is grown on a foreign substrate, asin a silicon film grown on sapphire cr gallium arsenide grown on a silicon substrate. Epitaxial growth techniques have largely supersedled the bulk growth for electronic circuit fabrication because the devices to be fabricated needs only few micron dimensions. The use of epitaxial growth, therefore reduces the growth time, wafering cost and eliminates the wastages caused during growth, cutting, polishing ete ‘The major advantage of the epitaxy is the uniformity in the composition, controlled growth parameters and better understanding of the growth itself 3.1.1 Different Epitaxial techniques Several epitaxial techniques have been used for the growth of epilayers of IIL-V, II-VI compound semieond tors and other materials. The , prominent among these techniques are Liquid Phase Epitaxy (LPE), Vapour Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Chemical Beam Epitaxy (CBE) and Atomic Layer Epitaxy (ALE) ete, 3.1.2 Advantages © Better structural & Electrical properties © Growth is carried out at low temperature. decrease in concentration of both chemical and crystalline defects. Also, the Melt is subjected to less chemical contamination from surrounding ‘The ability to control material thickness and carrier concentration Possibility to grow p-n junetion & other multilayer structures '* Superior electrical properties due to the lower defect density 332 Lecture 3: Epitaxial Growth Techniques 3.2. Liquid Phase Epitaxy ‘The liquid phase epitaxial (LPE) growth apparatus simply allows a growth solution of the desired composition to be placed in contact with the substrate for a certain time under controlled temperature conditions. In this technique, supersaturation necessary for deposition is achieved by reducing the temperature. The relationship between the temperature and solubility as predicted by the phase diagram has to be utilized in understanding the growth process, Besides thermodynamic consideration, there are other factors such ‘as diffusion of constituents in the solution, nucleation and the mechanism of geowth at the surface and convection as the result of temperature and compositional gradients that affect the LPE process Liquid phase epitaxy means the growth of thin films from metallic solution on an oriented crystalline sub- strate. The solvent clement can either be a constituent of the growing solid e.g. In or Ga, or it can be some other low melting metals like Sn, Bi or Pb, which is incorporated into the solid only as a dopant ‘The solvent contains a small quantity of solute e.g. As in Ga for epitaxial growth of GaAs layers which is ‘transported towards the liquid-solid interface. The process is best controlled if this transport occurs only by diffusion, ic. the driving force in the solution is a concentration gradient of the solute. The growth boats are commonly designed such that essentially, only diffusion perpendicular to the interface occurs; convection and surface tension related transport are suppressed. The temperature gradient is minimized by utilizing larger dimension of the substrate compared to the height and radius of curvature. Applying these constraints, the LPE process can be treated as an one-dimensional diffusion process in which the growth rate is found to be ted. diffusion 3.2.1 Apparatus ‘The liquid phase epitaxial (LPE) growth apparatus simply allows a growth solution of the desired composition to be placed in contact with the substrate for a certain time under controlled temperature conditions. In this technique, supersaturation necessary for deposition is achieved by reducing the temperature. The relationship between the temperature and solubility as predicted by the phase diagram has to be ut in understanding the growth process. Besides thermodynamic consideration, there are other factors such as diffusion of constituents in the solution, nucleation and the mechanism of growth at the surface and convection as the result of temperature and compositional gradients that affect the LPE process. Figure 3.1: Schematic diagram of LPE tipping growth apparatus ‘There are three principal LPE growth techniques: tipping, dipping and sliding. In the tipping technique, the substrate is held tightly at the upper end of a graphite boat and the growth solution is placed at. the other end. Initially the substrate wafer is well clear of the solution and the furnace is heated to form solution, ‘The solution is brought into contaet with the substrate by tipping the substrate. ‘The furnace is then slowly cooled and an epitaxial layer is grown on the substrate, The solution remains in contact with the substrate for the defined temperature interval and growth is terminated by tipping the furnace back to its originalLecture 3: Epitaxial Growth Techniques 33 position. ‘The solution remaining on the film surface is removed by wiping and dissolving in a suitable solvent. The original tipping furnace is shown in Figure 3.1 Radiation shies exnaust _— thermocouple Figure 3.2: LPE growth apparatus employing the dipping technique ‘The dipping technique uses a vertical furnace as shown in Figure 32. ‘The solution is contained in a graphite or alumina crucible at the lower end of the furnace. The substrate fixed in a movable holder is initially positioned above the solution. At the desired temperature, growth is initiated by immersing the substrate in the solution and it is terminated by withdrawal of the substrate from the solution. Figure 3.3: Horizontal slider LPE system ‘The apparatus used for the tipping and dipping techniques is very simple and easy to operate, However, growth of multiple layers by these techniques would require considerably more complex apparatus. The third LPE technique, the sliding technique, uses a multibin graphite boat to grow multiple epitaxial layers, Figure 3.3 shows a LPE system with sliding technique. The principal components of this apparatus ‘are a massive split graphite barrel with a graphite slider, a fused silica growth tube to provide a protective ‘atmosphere and a horizontal resistance furnace. The graphite barrel has the desired number of solution chambers depending on the number of layers to be grown, and the slider has two slots for the precursor seed substrate and the growth substrate. The substrate is brought into contact with the solutions by motion ofLecture 3: Bpitaxial Growth Techniques the barrel over the slider. This operation ean easily be automated. ‘The fused silica tube is usually within ‘heat pipe thermal liner in the furnace to ensure uniform temperature. Alternatively, a multizone furnace without a heat pipe can also be used. Growth is usually carried out in an atmosphere of hydrogen. 3.3. Molecular Beam Epitaxy Molecular beam ¢} fa heated substrate jtaxy is a process of depasiting epitaxial thin films from molecular or atomic beams on der ultrachigh vacuum (UHV) conditions. Figure 3.4 shows a schematic diagram of a typical MBE system. ‘The beams are thermally generated in Knudsen-type effusion cells which contain the constituent elements or compounds of the desized epitaxial films. The temperature of the cells are accurately controlled to give the thermal beams of appropriate intensity. The beam fluxes emerging from ‘these non-equilibrium effusion cells are generally determined experimentally in most cases using movable nude ation gauge placed in the substrate position, The cells are made from non-reactive, refractory materials ‘which can withstand high temperatures and they do not contribute to the molecular beams. Pyrolytic Boron Nitride (PBN) or high purity graphite are used as the cell materials. The cell consists of an inner crucible ‘and an outside tube which is wound with Ta or Mo wires for resistive heating. A chemically stable W-Re thermocouple facilitates precise control of the cell temperature which is very essential for achieving constant growth rates since small temperature fluctuations of the order of 441°C can result in +2 to 4% fluctuations in molecular beam intensity. The various cells are all placed and angled in such a way that their beams converge ‘on the substrate for epitaxial growth. Individual shutters provided for each cell and the cell temperat ‘can be computer controlled to achieve high reproduci individually surrounded by a liquid nitrogen shroud to prevent cross heating and cross contamination, nterventions. The cells are lity and little human RHEEO Gun Molecular Beams ~ LN, Cayopane! scam Simm RHEED Sciven Figure 3.4: Schematic of MBB system e has a number of advantages over other techniques. The most important aspect of MBE position rate (typically less than 3,000 nm per hour) that allows the filins to grow epitaxial. These deposition rates require proportionally better vacuum to achieve the same impurity levels as other deposition techniques. A particular advantage is that it permits growth of crystalline layers at temperatures where solid state diffusion is negligible. Since chemical decomposition is not required for growth, deposition species need require only enough energy to migrate along the substrate surface to crystalline bonding site. The impurity dopant incorporation during molecular beam epitaxial growth is possible by having an additional source of the dopant. As a result, MBE has rapidly established itself as a versatile technique for growing elemental and compound semiconductor films. Thus using MBE, it is possible to produce multilayered structures including superlattices with layer thickness as low as 10” for DH lasers and wave-guide applications.Lecture 3: Epitaxial Growth Techniques 35 However, there are few limitations in the epitaxial growth of compound semiconductors by MBE technique. ‘The ultra high vacuum apparatus is very expensive, Frequent shutdowns are required to replenish the source materials and opening the UHV apparatus. A major problem is the difficulty in growing phosphorus- containing materials. Phosphorous is found to he bouns pumps. around the system ultimately collected in vac 3.4 Vapour Phase Epitaxy ‘The principles of VPE ean be described in the following steps: 1. Transport of reactants to the substrate region 2. Transfer of reactants to substrate surface 3. Adsorption of reactants on substrate 4. Surface processes such as reaction and kinetics 5. Desorption of products 6. Transfer of products to main gas stream 7. Exhausting of gases away from reaction chamber ‘The steps 2 and 6 involve transfer of reactants to and fro from the erystal transport process. The steps 3,4 and 5 represent chemical reactions on the cry urface and are called mass tal surface. The Schematic Figure 3.5: Schematic diagram of vapour phase epitaxial growth process diagram of vapour phase epitaxial growth process is shown in figure 3.5. Vapour Phase Epitaxy (VPE) is ‘one of the commonly used techniques for the growth of II-V compound semiconductors. In this technics growth is carried out by vapourizing the source material for III-V compounds: inorganic or organic materials which react with the other materials to form the compound semiconductors on the substrate. Growth is controlled by the partial pressures of the each of the components of the source materials. Two different forms of the vapour phase epitaxial growth are: ‘© chloride vapour phase epitaxy ‘© hydride vapour phase epitaxy36 Lecture 3: Epitaxial Growth Techniques ‘The main practical difference between the two system is just the input gas supply. ‘The two process be ontlined in the table below: ‘The chloride VPE involves group V transport using trichloride (e.g-AsCls) and group III transport by the formation of chloride (e.g. GaCl). Crystal growth is carried out in a hot walled reactor and the chemical reactions are reversible making it possible to etch as well as grow. Inherent advantages of trichloride VPE over other vapour phase growth methods arise from the fact that AsCly and PCs can be distilled into very pure liquids, AS, + 4GaCl + 2H = 4GaAs + AHCL (a) Hydride VPE is an epitaxial growth technique often employed to produce semiconductors such as GaN, GaAs, InP and their related compounds, in which hydrogen chloride is reacted at elevated temperature with the group-III metals to produce gascous metal chlorides, which then zeact with ammonia to produce the grouplII nitrides. Both the source reactions and the deposition reactions are done inside a hot walled quartz reactor. The reactions occur under near equilibrium conditions, and since they are reversible, controlled in- situ etching is possible,Lecture 9: Metal-semiconductor junctions Contents 1 Introduction 1 2 Metal-metal junction 1 2.1 Thermocouples . . 2 3. Schottky junctions 4 3.1 Forward bias 9 3.2. Reverse bias : : eves 1 4 Ohmic junction 2 1 Introduction Formation of electronic devices requires putting together two or more dissim- ilar materials (semiconductors, metals, insulators). The interface between these materials becomes crucial because it affects the electrical properties (transport) of the devices. This interface is called the junction. An ideal junction is one where there are no defects formed at the interface. Forming ideal junctions is challenging and most real materials have defects at. the in- terface which can affect the electronic properties. But we can get an idea of the interaction between materials by studying ideal junetion. 2 Metal-metal junction Consider a junction formed between 2 metals with different work functions, as shown in figure 1. Metals are characterized by an incomplete energy band (valence and conduction band overlap) with the top of the energy band beingMM5017: Electronic materi Is, devices, and fabrication Pt Mo vacuum, vacuum Dp; = 5.36eV mo = 4.20ev Figure 1: Junction between Mo and Pt. Mo has a smaller work function than Pt. When a junction is formed electrons from Mo move to Pt until the Fermi level lines up and the junction is in equilibrium. Adapted from Principles of Electronic Materials - $.0. Kasap. the Fermi energy. The distance from the Fermi level to the vacuum level is led the work function (6). Tn figure 1 the two metals are Pt and Mo with work functions of 5.36 and 4.20 eV respectively. Actual junctions are formed usually by vapor deposition of one metal on top of the other. Usually some form of post deposition annealing is also used to form the interface and reduce defect density. The most important rule when a junction is formed is that the Fermi levels must line up at equilibrium (no external bias). This can be understood by using figure 1, where there are electrons in Mo at a higher energy level than those in Pt. ‘These electrons can occupy the empty energy levels located above the Pt Fermi level. Because electrons move from Mo to Pt a net positive charge develops on the Mo side and a net negative charge on the Pt side. Thus, a contact potential is developed at equilibrium between the two metals. This contact potential is related to the difference in the work functions, and is shown in figure 2. For Mo-Pt junction the contact potential is 1.16 V. 2.1 Thermocouples Metal-metal junctions are used to form thermocouples, which are used for accurate temperature measurements. Thermocouples are an example of tem- perature measurement by a contact technique, while pyrometers are examplesM5017: Electronic materials, devices, and fabrication py ~ Dito = 1.16 eV = eAV 5.36 eV 420ev Figure 2: Junction formed between Mo and Pt at equilibrium, with a contact potential given by the difference between the work functions. The contact potential prevents further motion of electrons from Mo to Pt. Adapted from Principles of Electronic Materials - 8.0. Kasap. of non-contact temperature measurement. To understand the working of a thermocouple we need to consider the Seeback effect, summarized in figure 3. When a metal is heated at one end and the other end is kept cold, electrons at the hot end are more energetic than those at the cold end. These electrons have a greater thermal velocity and can move towards the cold end. This creates a potential within the metal with the hot end at a positive potential with respect to the cold end, see figure 3. The potential created is called the Sceback potential and it depends on the temperature difference between the hot and cold end. ty av= | sar (a) EN S is called the Seeback coefficient and is a material dependent parameter and also a function of temperature. The Seeback coefficient is approximate related to the Fermi energy by the Mott and Jones equation, which is valid for a larger number of metals. 24 we CHT 3eEr x here is a numerical constant that depends on the charge transport proper- ties of the metal. Seeback coefficient values for different metals are listed in Q)MM5017: Electronic materi Is, devices, and fabrication © ‘ ot cot ‘temper, st — S$" tL ee 5 : 5 Park A meee aa Lhe Contador ihre $< Wire st] > {8 _ © 8 8+ B-8]- mi) se@ 6 6.e > cot +e “@ @° @*d%@ Figure 3: Schematic of the Seeback effect showing the potential development in a metal with a temperature gradient. There is a greater energy of electrons at the hot end which then flow to the cold end leasing to development on an in-built potential. The potential depends on the temperature difference and a material parameter called the Seeback coefficient. Adapted from Principles of Blectronic Materials - 8.0. Kasap. table 1 If a junction is formed between two dissimilar materials and one end is placed at the hot end (e.g. a furnace whose temperature is to be measured) and the other end placed at the cold end (room temperature) then a contact potential is developed at both ends. This contact potential is diffe the Seehack coefficients of the two materials are different. So a net potential develops in the system given by ent since T AV = [ (Sa — Sa)AT (3) ri where $4 and Sp are the Secback coefficients of the two metals. The setup is shown schematically in figure 4. Typically, thermocouple potentials are tabulated for different temperatures for standard thermocouple materials. These tables are used when measuring the temperature of the unknown sam- ple. There are different thermocouples used for specific temperature regions, as shown in figure 5. 3 Schottky junctions When a metal and semiconductor are brought into contact, there are two types of junctions formed depending on the work function of the emicon-MM65017: Electronic materials, ‘Table 1: Sceback coefficients for some typical metals at two different. tem- peratures and values for xr. ‘The Ep values are also listed. Adapted from Principles of Electronic Materials - $.0. Kasap. Metal | S at 273 AK | S at 300K | Ep © (uv K (WK) | (eV) Al 16 “18 278 Aw 79 Lo “148 Cu 170 Lt “179 K “125 38 Ti ie “07 Mg =I 138 Na -5 2.2 Figure 4: Temperature measurements using a thermocouple consisting of tow dissimilar metals. There is a potential difference at the two junctions arising from the different Seeback coefficients of the two materials, Adapted from Principles of Electronic Materials - $.0. Kasap.MM5017: Electronic materi levices, and fabrication a8 ea 8 8 TaemacoupleVetage fi 8 Temperature fo) Figure 5: Thermocouple potential vs. temperature for different types of thermocouples. ‘The potential can be measured using a standard digital voltmeter and converted into temperature. Souree http://www.mosaic- industries.com/embedded-systems/microcontroller-projects/temperature- measurement /thermocouple/types-wire-element ductor and its relation with the metal 1. Schottky junction - dy, > Osemi 2 Ohmic junction - dm < Psemi Consider a junction formed between a metal and n-type semiconductor, as shown in figure 6. The Fermi level of the semiconductor is higher (since its work function is lower) than the metal. Similar to a metal-metal junction, when the metal-semiconductor junction is formed the Fermi levels must line up at equilibrium. Another way to look at this is that there are electrons in the conduction level of the semiconductor which can move to the empty energy states above the Fermi level of the metal. This leave a positive charge on the semiconductor side and due to the excess electrons, a negative charge on the metal side, shown in figure 7, leading to a contact potential. When a contact is formed between two metals, the charges reside on the surface. This is due to the high electron density found in metals (typically 10”? em=4). On the other hand, when a contact is formed between a metal and semiconductor, due to the low charge density on the semiconductor side (typically 10!7 em) the electrons are removed not only from the surfaceication MMS5017: Electronic materials, devie level Metal n-type semiconductor Before contact Figure 6: Schottky jumction between metal and n-type semiconductor before contact. The work function of the semiconductor is smaller than the metal so that electrons can move from semiconductor to metal, forming a contact potential. Adapted from Principles of Electronic Materials - $.0. Kasap. Vo KS 2 ® ® Depletion region {Bono ions) Figure 7: Schematic showing the metal, n-type semiconductor, and the Schottky junction between them. There is a depletion layer in the n-type jiconductor due to transfer of electrons to the metal. This leads to the formation of a contact potential. Adapted from Principles of Electronic Ma- terials - $.0. Kasap.MM5017: Electronic materi Is, devices, and fabrication Figure 8: Schottky junction showing the band bending on the semiconductor side, Semiconductor bands bend up going from the semiconductor (posi- tive) to metal (negative) since this is the same direction as the electric field. Adapted from Principles of Electronic Materials - 8.0. Kasap. but also from a certain depth within the semiconductor. This leads to the formation of a depletion region within the semiconductor, shown in fig- ure 7. ‘Thus, when a Schottky junction is formed between the metal and semicon ductor, the Fermi level lines up and also a positive potential is formed on the semiconductor side, Because the depletion region extends within a certain depth in the semiconductor there is bending of the energy bands on the semi- conductor side. Bands bend up in the direction of the electric field (field goes from positive charge to negative charge, opposite of the potential direction) This means the energy bands bend up going from n-type semiconductor to metal, shown in figure 8. The Fermi levels line up and there is a certain region in the semiconductor (denoted by W’) where the bands bend (this is the depletion region). Another name for the depletion region is the space charge layer. There is a built in potential in the Schottky junction, Vo, and from figure 8 this is given by the difference in work functions. Vo = Om — deemi @) ‘The work function of the metal is a constant while the semiconductor work function depends on the dopant concentration (since this affects the Fermi 8MM5017: Electronic materi levices, and fabrication level position). The contact potential then represents the barrier for the electrons to move from the n-type semiconductor to the metal. Initially, when the junction is formed electrons move to the metal to create the depletion region. The contact potential thus formed prevents further motion of the electrons to the metal.There is also a barrier for electrons to move from metal to semiconductor. ‘This is called the Schottky barrier and denoted by op in figure 8. This is given by On = (dm — On) + (Be — Een) = Om — Xn (5) where y;, is the electron affinity of the n-type semiconductor. At equilibrium the motion of electrons from the semiconductor to metal is balanced by the contact potential so that there is no net current. The Schot- tky junction can be biased by application of an external potential. There are two types of 1. Forward bias - metal is connected to positive terminal and n-type semi- conductor connected to negative terminal 2. Reverse bias - metal is connected to negative terminal and n-type semi- conductor connected to positive terminal The current flow depends on the type of bias and the amount of applied external potential. 3.1 Forward bias In a forward biased Schottky junction the external potential is applied in such a way that it opposes the in-built potential. Since the region with the highest resistivity is the depletion region near the junction, the voltage drop is across the depletion region. Under external bias the Fermi levels no longer line up, but are shifted with respect to one another and the magnitude of the shift: depends on the applied voltage. Energy band diagram of the Schottky junetion under forward bias is shown in figure 9. Thus, electrons injected from the external cireuit into the n-type semiconductor have a lower barrier to surmount before reaching the metal. This leads to a current in the cirenit which increases with increasing external potential. The current in a Schottky diode under forward bias is given by J = Jy lose) = 1) 6) where J is the current density for an applied potential of V. Jp is a constant and depends on the Schottky barrier (p) for the system and the expression 9M5017: Electronic materials, devices, and fabrication Mets! ___mtype semiconductor Figure 9: Schottky junction under forward bias. Adapted from Principles of Electronic Materials - 8.0. Kasap. is on Jo = AT? exp(- 2% 7 lo P ke? ”) where A is the Richarison constant for thermionic emission and is a material property. Equation 6 shows that in the forward bias the current exponentially increases with applied potential, 3.2 Reverse bias In the case of a reverse bias the external potential is applied in the same ¢ rection as the junction potential, as shown in figure 10. Once again the Fermi levels no longer line up but the barrier for electron motion from the n-type semiconductor to metal becomes higher. The electron flow is now from the metal to the semiconductor and the barrier for this is given by the Schottky barrier (x). So there is a constant current in reverse bias, whose magnitude is equal to Jy (as given in equation 7). From calculations it can be shown that the current in the forward bias is orders of magnitude higher than the current in reverse bias (this arises due to the exponential dependence on potential). So a Schottky junetion acts as a rectifier i.e. it conducts in forward bias but not in reverse bias. The 7 —V’ characteristics of the junction is shown in figure 11. There is an exponential increase in current in the forward bias (I quadrant) while there is a small current in reverse bias (IV quadrant). 10MM5017: Electronic material and fabrication Vet 5 2 fetve-t Von) | Ee = Figure 10: Schottky junction under reverse bias. Adapted from Principles of Electronic Materials - 8.0. Kasap. Figure 11: I~ V characteristies of a Schottky junction showing rectifying properties. Adapted from Principles of Electronic Materials - S.0. Kasap. cnMM5017: Electronic materi levices, and fabrication LY plot for Schottky lode Forward bios Curent ma Reverse bicr mA Voltage () Figure 12: I — V characteristics of a Schottky junction between n-Si and Au. The barrier potential energy is 0.83 eV and the Richardson constant is 110 Acm™?K~?. The plot is at room temperature and generated using MATLAB. The y-axis is in mA in the forward bias quadrant and 1A in the bias quadrant. reverse ‘The forward and reverse bias currents for a Schottky junnetion formed be- tween Si and Au can be calculated using equations 6 and 7. Consider n-type Si with donor concentration of 10" em~?. The dopant concentration fixes the Fermi level position in the semiconductor and hence its work function. For Au-Si the measured value of the Schottky barrier is 0.83 eV. The Richardson constant for this junction is 110 Aem~?-*. Using equation 7 it is possi- ble to calculate the reverse saturation current density in this junction. This is a constant, independent of the reverse bias voltage, and has a value of 0.12 Aem™. The forward bias current density depends on the applied volt age, equation 6, and increases exponentially with the applied voltage. The LV characteristics of this junction is plotted in figure 12. The plot is similar to that shown in figure 11, and rectification can be seen from the fact that forward bias current is more than three orders of magnitude higher than the reverse bias current and the value increases with applied voltage. 4 Ohmic junction A Schottky junction is formed when the semiconductor has a lower work fune- tion than the metal. When the semiconductor has a higher work function the junction formed is called the Ohmic junction. Once again it is possi- ble to draw the energy band diagram of the junction in equilibrium (Fermi levels line up). This is shown in figure 13. At equilibrium, electrons move 12M5017: Electronic materials, devices, and fabrication Acomaion ion aah enone Mal” hina leo ‘Metal ntypesemicondestor (0) Reto contact (8) Ate contac Figure 13: Ohmie junction (a) before and (b) after contact. Before contacts the Fermi levels are at different positions and they line up on contact to give an accumulation region in the semiconductor. Adapted from Principles of Electronic Materials - S.0. Kasap. from the metal to the empty states in the conduction band so that there is an accumulation region near the interface (on the semiconductor side). The accumulation region has a higher conductivity than the bulk of the semicon- ductor due to this higher concentration of electrons. Thus, a Ohmic junction behaves as a resistor conducting in both forward and reverse bias. ‘The re- sistivity is determined by the bulk resistivity of the semiconductor. One of the interesting applications of Ohmic junctions is in thermoelectric devices, where a small volume can be cooled by application of direct currents. For Ohmic junctions, depending on the direction of current flow (forward or reverse biass), heat can be generated or absorbed. This is shown in figure 14. This is called Peltier effect and is applicable to junctions between any two dissimilar materials. So, when current flows through a metal semiconductor Ohmic junction, heat will always be released or absorbed. This can be used as a practical cooling device, as shown in the schematic in figure 15. Both p- and n- type semiconductors are used and the current flow is such that one end is always cold (heat absorbed) while the other end is hot (heat released). There are different metals that form Ohmic contacts with semiconductors. ‘A partial list of such combinations is shown in table 2. This list is important because it gives the acceptable metals for each semiconductor that can be used in fabrication of devices. For Si, earlier Al was used for making ele trical contacts, which was then replaced by AL-Cu alloys. Both form Ohmic contacts with Si. These have now been replaced by Cu (higher conductiv- ity). But, Cu is poisonous to Si and hence cannot directly come into contact with the semiconductor. Usually, Ti or TiN is used to make electrical con- 13MM5017: Electronic materi Is, devices, and fabrication (a) Erm "Ohmi eortac resien Metal type semicondoctor Ohmic coneet reaion ype Semiconductor Figure 14: Current flow through an Ohmic junction can lead to heat: (a) absorption or (b) release. This depends on the external bias, that determines the direction of heat flow. When electrons move from metal to higher energy levels in the semiconductor heat is absorbed and the reverse happens when electrons flow from semiconductor to metal. Adapted from Principles of Electronic Materials - 8.0. Kasap. 4MM65017: Electronic materials, devices, and fabrication Electrical insulation —— tse ee cenducto) n-type semiconductor —| ‘t Body fo be cooled (heat source) p-type semiconductor Metal Heat sink = |t DC supply Figure 15: Schematic of the Peltier cooler using both p- and n- type semi- conductors. One end of the cooler is connected to the body from which heat is absorbed (cooled) and the other end is connected to a heat sink, where it is released. Adapted from Principles of Electronic Materials - $.0. Kasap.M5017: Electronic materials, devices, and fabrication ‘Table 2: Combination of semiconductors (n and p) and metals (alloys) that normally form Ohmic contacts. Adapted from Principles of Electronic Ma- terials - 8.0. Kasap. n-semiconductor | Metal p-semiconductor | Metal Ge Al, Au, Bi, || Ge Ag, Al, Au, Sb, Sn Cu, Ga, In, Ni, Pt, Sn Si Ag, Al, Ni, | Si Ag, Al, Au, In, Sb, Ti, Ni, Pt, Sn, In, Pb, Ga, Ge, Ti, TIN GaAs AgSu Gaas AgZa ‘GaP Al, AwSi, | GaP AuwZn, Ga, Aw-Sn, In-Sn Zn, Ag-Zn GalsP GaAsP AuZn GaAlAs GaATAS AZ Tas TnAs Al TnGaAs TnGaAs Awa, Cas CdTe CdTe ‘Au, In-Ni, Pt. Rh ZaSe Tu, In-Ga, Pe SiC W. SiC ALS, Si, Ni tact with Si, and then Cu is deposited. Ti or TiN is chosen because it also forms Ohmic contaets with p and n type Si, see table 2, and can be eas- ily deposited by chemical vapor deposition. For integrated devices electrical contacts to the outside circuit components are done using evaporated met- als and Ohmic contacts are formed. This is because the electrical contact should not impose a rectifying behavior on the device. Thermal processing of metal-semiconductor contacts can lead to inter-diffusion and formation of metal silicides. Pt-Si forms a number of silicide phases like PtSi, PtySi, and PtsSi. Similarly, Ti-Si forms TiSig, TizSi, and TisSi. Thus the contact is no longer between a metal-semiconduetor but between a silicide-semiconduetor This can affect the electrical properties of the junction. 16Sh S102 MOS Diode insulator mt a nm ae, oY Where d. is the thi hickness to be used in these actual . of the insulator, e(insulator) is the perminiyds!3,tre » and €(Si0,)= 3.5% 10" pernitiviy of Oe S agree 10°!" Fem. For other the t Semiconductors 36 curve: fo those in Fig. 9 can be constructed by using Eas: The ideal MIS curves shown ii < a s nin Figs, 10 throu; sed in on, oa to compare with copettiatatal 5 vi io onder- stand MIS systems. a 7.3 Si-SIO, MOS DIODE pot oe pe MIS diodes, the a SOS! (M09) diode tala Ne Pa, 2 ant The exact naturé“of the Si-SiO; “interface is not yet fully Pombosition An appealing picture’ of the interface is that the chemical position of the interfacial region, as‘a consequence of 1, IS a single-crystal silicon follow fi sa See followe: amon SiO, (the compound SiO, is stoichiometric when x = chiometric when 2>x > 1). For a practical MOS diode, interface traps and hide charnes. exist that Will in one way or another, affect the ideal characteristics. oT asic classifications of these traps and charges are shown” in Fig. 15: (1) interface trapped charges Q,, which are charges located at the Si-SiO; interface with energy states in the silicon-forbidden bandgap and which can exchange charges with silicon in a short time; Qu can possibly y excess silicon), excess oxygen, and impurities; (2) fixed oxide charges Q,, which are located at or near the ‘are immobile under an applied electric field; (Gy oxide trapped Qe, Which can be Created, for example; by x-ray radiation or injection; these traps are distributed inside the oxide layer; e ionic charges Q,,, Sucl sodium ions, which are mobile the oxide under bias-temperature aging conditions. Q's are the effective net charges per unit area (i.e., C/em’). the effective net number of charges per unit area, one can e corresponding subscripts, that is, N = Qlq in number of scause interface-trap levels are distributed across the silicon we shall define an interface-trap density, Du: Dy= 14Qe — jumber of charges/em’-eV. G2) tq dE‘anil gesios MOS DIO? pr for donor interface traps and Fsa(Bi) = =o a 1#5 exp (Egg) for acceptor interface traps, where E, is the energy of the interfi and & is the ground-state degeneracy, which is 2 for donor nad 4 ba ‘when a voltage 1S applied, the interface-trap levels move up or down the valence ‘and conductance bands while the Fermi level remains fixed. A change ‘of charge in the interface tap occurs when it crosses the Fermi level. ‘This change of charge contributes to the MIS capacitance and ters the ideal MIS curve. The basic equivalent circuit™ incorporating the jnterface-trap effect is shown in Fig. 16a. In the figure, C, and Cp are the insulator capacitance and the semiconductor depletion-layer capacitance, respectively, and are identical to those shown in the insert of Fig. 9. C, and R, are the capacitance and resistance associated with the interface traps, and are functions of surface potential. The product CR, is defined as the interface-trap lifetime, which determines the frequency behavior of the The parallel branch of the equivalent circuit in Fig. 16a can interface traps- be converted into a frequency-dependent capacitance C, in parallel with 2 frequency-dependent conductance G,, a8 shown in Fig. 16b, where G G=O+pee G4) G, Cor Ses —— (3: o ite 4 (o) (>) 4, where Ox and A, are 85) it circuit includin interface-trap effect ‘i ‘ berger, Ref. 24.) ‘ce-trap density. (After Nicollian and Goetz!a Mis Diode and Charge-Coupled Device thi epletion region to the surface; R,, is the resistance associated Bs the cerrent fo of holes between the valence band and the interface traps, with the current flow of electrons between the conductance band and the interface traps, and with the flow of the majority carriers from the butk. to the surface; and Ryn is the resistance associated with the finite genera- tion and recombination within the depletion layer, which is found to be the dominant factor in controlling the frequency response of the inversion layer. The interface trap capacitance C, can be sumed to be essentially zero (C, € Cy) under heavy inversion conditions. Figure 22d shows that, in the heavy inversion region, the interface traps have only a minor effect on the MIS characteristics. 7.3.2 Oxide Charges Oxide charges include the oxide fixed charge Q) the oxide trapped charge Q,,, and the mobile ionic charge Qm, as shown in Fig. 15. 7 The fixed oxide charge Q, has the following properties: It is fixed ane cannot be charged or discharged over a wide vari i ite in the order of 30 A of the Si-SiO; interface;’ its density is not gre: affected by the oxide thickness or by the type or concentration of it tities in the silicon; it is generally positive and depends on oxic annealing conditions, and on silicon orientation. It has been suggestec excess silicon (trivalent silicon) or the loss of an electron from e oxygen centers (nonbridging oxygen) near the Si-SiQ2 interface origin of fixed oxide charge. In electrical measurements, Q, can be ed as a charge sheet located at the Si-SiQ, interface. Figure 23 shows the shift along the voltage axis of a high-frequen C-V curve when positive or negative Q, is present at the interface.’ T voltage shift is measured with respect to an ideal CV curve where Q; = For both n-type and p-type substrates, positive Q, causes the C-V to shift to more negative values of gate bias with respect to the ideal curve, while negative Q, causes the C-V curve to shift to more p gate voltage. The voltage shift of the C-V curve caused by Q; can be explained wi the help of Fig. 24, which shows a cross section through an MOS dic having positive Q, and a negative gate bias. Charge neutrality every negative charge on the gate to be compensated by an equ opposite charge in the oxide and the silicon. For the ideal case, Q= entire compensation charge comes from the ionized donors. Howeve a practical MOS diode with a positive Q,, part of the compensating must consist of Q, and the rest of ionized donors. Figure 24 shows § field lines from a terminating on negative charges on the gate and | field lines from ionized donors terminating on the gate than would e Q, =0. Because fewer ionized donors are required, the silicon depl layer width will be smaller than with Q, = 0 at any given gate bias. TSESIO: Mos Diode tb) itt along the voltage axis due to * {2) For p-type semiconductor. (b) For n-type. Ref. 7.) * itance will be higher than for the ideal depletion and weak inversion V curve toward more Negative gate bias | For negative Q, the C-V curve shifts le magnitude of the shift is given by‘S*-$:0: MOS Diogo due to the oxide trapped charge is given by Ve Sew EEG [ sncter ae] where Q. is the effective net charge in bulk oxide traps per unit aren at the Si-SiO, interface. and puix) is the volume oxide-trap density, The total voltage shift due to all the oxide charges it given by f AV =AV,4AV.+AV. = % re where Q. =(Q; + Q. +Qz) is the sum of the effective net oxide change per & unit ares al the Si-SiO, interface. 7.3.3 Work-Function Difference and External Influences: Work-Function Difference For an ideal MIS diode, it hae assumed that the work-function difference (Fig. 2) for an n-type (assuming negli ‘curve, will be shifted from the ideal Vea = be B= ba where Vis is called the flat-band voltage shift. If negligible oxide trapped charges exist, Eq. 49 reduces to Vea = bus- 2. ; band for the Si-SiO; interface has been on sstwonton 7” SiO; bandgap is foundp-n Junction Diode vet) istics. (@) characteristics. eluding Auger recom" Dannhauser, and Krausse, Ret. 54.) Recombinat jon only. (b) Including bination as well. ( ‘After Burtscher, Fig. 43 Forward current-voltag carrier-carrier scattering. (¢) Incl jer-carrier scattering, and i i 1 of carrier—ca ane i region, curve (b) includes the effec! rrietay worsening Ota curve (0) ficludes Auger recombination as well. The stete ty worried device characteristics is revealed in this progression: TSC Yio ee recombination and carrier-carrier scattering S‘ q formance. progressio’ 2.8 HETEROJUNCTION heterojunction is a junction formed between two dissimilar. semicor ductors. When the two semiconductors have the same type of conductivity, ‘the junction is called an isotype heterojunction. When the conductivity” types differ, the junction is called an anisotype heterojunction \In 1951, j kley~proposed the abrupt heterojunction to be “used” as” an efficient emitter—base junction in a bipolar transistor. In the same year, Gubanov published theoretical papers on heterojunctions.° Kroemer later analyzed a , ‘similar, although graded, heterojunction as a wide-gap emitter.” Since then, heterojunctions have been extensively studied, and many important ap- _ plications have been made, among them the r 1 injection — Taser, light-emitter diode, photodetect solar een eee forming periodic layered heterojunction, yet pot cell. In addition, by Junctions with layer thickness of the order _ Scanned By Scanner GoP T= ae in Meterojunetion 4. The heterojunctions of 100 A, we have the so-called superlattice st¥ Purohit,” and have been reviewed by Milnes and Feucht,"* Sharm and Casey and Panish." 2.8.1 Basic Device Model The energy-band model of an ideal abrupt heterojunction ewok face traps was proposed by Anderson” based on the previons Word oe jockey. We consider this model nexi, since it can ndeauarey Cee ce Most transport processes, and only slight modification of the mu NN to account for nonideal cases such as interface traps. Figure “°6 * vacuuM LEVEL LECTRON lENERGY Fig. 44 (a) Energy-band diagram for two isolated semiconduct in which sp charge neutrality is assumed to exist in each region. (b) Energy-band diagram of ani “1p anisotype heterojunction at thermal equilibrium. (After Anderson, Ref, 60.) i, - Scanned By Scanner Goen ane Jereman Ont , tm uctors. The two RerRY-end diagram of two isolated piece et ape Ey, different . med to have ait ern aiftere ctron affinities Semiconductors were a Permittivit different work function? ee that eneray required to & Work function and electron aMinity are arf coe from the bottom of the and fromutside the material Femove an electron from the Fermi level cath Conduction band Fe, respectively. to ® porlien iMjuction-band edges in (vacuum level), The difference in enetay of tHE CONLUC NL tence. band Ec an the two semiconductors is represented BY cee as 1 Sdges by AE,. Figure 44a shows that BEc = UX? by choosing AE rule AE¢ = Ay may not be a valid assumption orains unaltered.“ ®8 an empirical quantity, the Anderson model femiconductors, the energy. | en a junction is formed between thes for an n-p anisotype 44b oe band profile at equilibrium is as shown in Fig. 1° eon both sides in heterojunction. Sin Fermi level m' ¢ band ed; equilibrium and a penne level is everywhere parallel €0 Me (AEc) tnd and is continuous, the discontinuity in conduction-Dit Rn See valence-band edges (AEv) is invariant with doping in te semiconductors). and x are not functions of doping (i.€ nondegenerat ‘fe partial Galles The total built-in potential Vs: is equal to the sum of foe Dee Voltage (Vs, + Vs:), where Voi and Vex are tne ee ectively. Supported at equilibrium by semiconductors 1 and ae ined by solvin, The depletion widths and capacitance can be obtaine® Ne S0'ing Poisson's equation for the step junction on either side of the intetfacs. One boundary condition is the continuity of electric displacement, that is, «:E, = &E, at the interface. We obtain y= [ oie)" (i) @Noi(e:Noi + €2Na2) QNaxleNp: + Nan). ), This electron affinity and a = qNoiNar€s€2 . 120) Ce laa + Nak Va vil a The relative voltage supported in each semiconductor is Vor- Vi _ Naréz (121) Vn-=Vi Nose: where V=V,+V;. It is apparent that the foregoing expressions will reduce to the expression for the p-n junction (homojunction) discussed in Section 2.3, where both sides of the heterojunction have the same materials. The case of an n-n isotype heterojunction of the two semiconductors is somewhat different. Since the work function of the wide-gap semiconduc- tor is smaller, the energy bands will be bent oppositely to those for the n-p Scanned By Scanner GoMeterajunction we case® (see Fig. 4Sa)."' The relation between Vss~ Vs and Vor ‘ can he. found from the boundary condition of continuity of electric alee aeons at the interface. For an accumulation in region | governed by Boltzmann statistics (for detailed derivation, see Section 7.2), the electric displacement ® at x9 is given by Di EBi(x0) = ‘ warn EE (xn yg 22-1) vv] fa -—— SUBSTRATE vo) te) Fig. 45 (a) Energy-band diagram for an ideal n-n isotype heterojunction. (After Chang, Ref. 61.) (b) and (c) Energ) ind diagrams for ideal p-n and p-p heterojunctions, "respectively. (After Anderson, Ret. 60.) “The convention is to list the material with the smaller bandgap as the first symbol. Scanned By Scanner Gopon Junction Diode Jetivn in region 2 is . ae lectric displacement ot the interface for a denice iv rb _ val’. (123) Vir — Vi) and (Vir = : NoxlesNor is of the Dy = EF :(20) = Rear Ver Equating Eqs. 122 and 123 gives a relation between U 2) that is quite complicated. However. if the (atl ¢ Order of unity and Vac Vai+ Vox) ® ki7a. we obt qs: Yl) = ve -¥) “Also shown Where V is the total applied voltage and is equal t0 (Vs Coens et Bie in Fig. 45 are the idealized equilibrium enerey-bane (Ore (narrow-gap p-type and wide-gap n-type) and p:P Meter TO ceregt. For the current-voltage characteristics we shall cons gaenedies ing case shown in Fig. 45a. The conduction mechanism 1 BMT te thermionic emission (refer to Chapter 5 for details) and Biven by* (124) il (125) J=AtTiexp(- where A® is the effective Richardson constant, Substituting Eq. 124 into Eq. 125 yields the current-voltage relationship: Jal Y \[exo(2r)- | (126) where he gaye exo( te This expression is somewhat different from that for metal-semiconductor contact. The value of Jo is different and so is its temperature dependence. The reverse current never saturates but increases linearly with voltage at large V. In the forward, the dependence of J on qV/kT can be ap- proximated by an exponential function or J ~ exp(qV/nkT). 2.8.2 Heterojunction Devices The successful application of heterojunctions to various devices is due mainly to the epitaxial technology to grow lattice-matched isotype or anisotype heterojunctions with virtually no interface traps. Hetero- junctions have been used in bipolar devices as wide-gap emitters and in unipolar devices for MESFET applications. We consider them in Chapters 3 and 6, respectively. The most important applications of heterojunctions are in photonic devices, including semiconductor lasers, photodetectors, __ and solar cells. We shall consider their characteristics in detail in Chapters 12 BY through 14. . Scanned By Scanner GoMeterojunetion i DISTANCE Fig. 46 (a) Composition variation. (b) Equilibrium energy-band diagram. (c) Energy- band diagram under forward bias for a sawtooth-shaped composition grading structure. {After Allyn, Gossard, and Weigmann, Ref. 63.) In this section we consider briefly a few novel heterojunction configura- tions that may have potential applications. Figure 46a shows” a unipolat rectifying structure having a sawtooth-shaped composition grading of ter- nary compound Al,Gay-,As sandwiched between layers of n-type GaAs. As the composition x increases from 0 to 0.4, the bandgap of Al,Gay-:As - _ increases linearly from 1.42¢V to 1.92 eV, which gives rise to the equilib- rium energy-band diagram shown in Fig. 46b. Under forward bias, the voltage drop occurs across the graded layer, reducing the slope of the potential barrier and allowing increased thermio: emission over the barrier (Fig. 46c). In the reverse bias, the electrons will be inhibited from passing through the abrupt potential discontinuity at the sharp edge of the sawtooth. Rectification characteristics have been observed for this device operated at 77 and 300K. The superlattice structures include (1) a multilayered heterojunction arrangement with typical layer thickness of the order of 80 to 100 A, and (2) a periodic alternation of the doping of only one semiconductor to form a Scanned By ScannerGo *i Fig. 48 Mobility versus temperature for bulk GaAs and modulation-doped superlattice 3) o struc! periatticn $d superiattice structure, jure of GaAs (1.42 eV) ). 43 " 1s undoped su! sn Adena ergy sam 8 (After Dingle et al., Ref. 64.) it is wn to produce Series of homojunctions. Molecular-beam epitaxy eT penanen atomically smooth layers and to allow very’ vam of GAaA$- layer thicknesses. The schematic energy: ‘The structure is Al,Ga,.,As superlattice structure is sh Undoped. Therefore, the Fermi level lies near wulation-doped precise © band iat ey Fig. 472- shown” ne middie of the bandgap. 20000; MODULATION - DOPED (5x10%em">) MOBLITY (em2y-s) 3 eutk (2 10") L sents 5000} 300 % 100) 200 TUK) structure. (Atter Dingle ot al., Ret. 64.) Scanned By Scanner Goneterencee 9 por composition x = 0.3, the bandgap difference is about 300 meV, We can iadutate the doping BY ‘synchronizing the deposition of Al and Si (a donor meALGa.-sAs) 80 that only. the ‘Al.GavAs layers are doped with Si The energy-band diagram for the ‘modulation-doped superlattice Whe Fermi level now moves closer to the conduction: ‘band edge lies lower in energy than impurities ie shown in Fig. 476. band edge. Since the GaAs conduction the AL.Gai-sAs donor states, electrons from the donors will move into the GaAs regions. Now | mobile carriers are confined to the GaAs layers, and their parent donor impurities (in the ‘Al,Gai-2As layers) are spatially separated from each other. ‘Thus the electron density in the GaAs channel may greatly exceed the density of the neutral and ionized impurity scatter~ ing centers in the channel, leading to considerable change In mobility behavior in the temperature and carrier density regime, where impurity scatterings are important. Figure 48 shows the measured mobility parallel to the multilayer as a function of temperature. Note that the modulation- doped superlattice structure has a substantially higher mobility than that of the bulk material. If a voltage dicular to the multilayers, resonant tunneling may Occur, is applied perpen' u giving enhanced tunneling voltages near the quasi-stationary states of well. These properties may lead to many useful device possil REFERENCES nductors and p-n Junction 1 W. Shockley, “The Theory of p-n Junctions in Semicot d Holes in Semiconductors, Transistors,” Bell Syst. Tech. J., 28, 435 (1949); Electrons an D. Van Nostrand, Princeton, N. J., 1950. C.T. Sah, R. N. Noyce, and W. Shockley Junction and p-n Junction Characteristic: J. L. Moll, “The Evolution of the Theory of the Current Junctions,” Proc. IRE, 46, 1076 (1958). For example, see A. G. Grove, Physics and Technology New York, 1967. 5. RN. Hall and W. C. Dunlap, “p-n Junctions Prepared Rev,, 80, 467 (1950). 6 M. Tanenbaum and D. E. Thomas, Syst. Tech. J., 35, 1 (1956). 7 C.J. Frosch and L. Derrick, “Surface Protection and Selective Masking during Diffusion in Silicon,” J. Electrochem. Soc., 104, 547 (1957). \ $5. A. Hoerni, “Planar Silicon Transistor and Diodes,” IRE Electron Devices Meet., Washington, D.C., 1960. y H.C. Theuerer, J. J. Kleimack, H. H. Loar, Transistors,” Proc. IRE, 48, 1642 (1960). ickar, ‘Ion Implantation in Silicon-Physics, 10 For a review; see, for example, K. A. perceising and Microelectronic Devices,” in R. Wolfe, Ed., Applied Solid State Science, Vol. 5, Academic, New York, 1975. ‘arrier Generation and Recombination in p-n * Proc. IRE, 45, 1228 (1957). Voltage Characteristics of p-n » o of Semiconductor Devices, Wiley, a y Impurity Diffusion,” Phys. “Diffused Emitter and Base Silicon Transistors,” Bell and H. Christenson, “Epitaxial Diflused Scanned By Scanner GoURET: Inter Engineering and Tei -7308 ology eISSN: 2319-1163 | pISSN: 2321 A GaAs/AlGaAs/InGaAs PPEUDOMORPHIC HEMT STRUCTURE FOR HIGH SPEED DIGITAL CIRCUITS Parita Mehta’, Lochan Jolly” 'M.E.EXTC (Pursuing), Electronics & Telecommunication Department, Thakur College of Engineering and Technology, Maharashtra, India * Professor, Electronics & Telecommunication Department, Thakur College of Engineering and Technology, Maharashtra, India Abstract A double heterojunction GaAVAIGaAV/InGaAs pseudomorphic depletion mode HEMT has been developed at the gate length of ‘80nm. The device properties are tested for different biasing potentials atthe input and output side. The device és found to exhibit a cut off frequency of 80Ghz.Further, the logic suitability of the device is supported by developing the basic gates used for digital communication ie., Inverter, Nand and Nor. Thus, enhancement in digital communication can be obtained with the use of HEMTs which provide high speed, low noise applications. Furthermore, with the implementation of universal gates using HEMTs, any digital circuit can be easily implemented. The paper reports a complete method from developing of the structure in Visual TCAD (VICAD) 10 further implementing a circuit using the developed structure. Keywords: HEMT, TCAD, Pseudomorphic, Logic Gates, Digital Applications 1. INTRODUCTION ‘The emergence of III-V compound semiconductors has given a promising choice for channel material of future. These devices rely on the use of heterojunctions for their ‘operation and high electron mobility transistors (HEMTs) are one of the most mature ones of the new generation of the TIE-V semiconductor transistors, The heterojunctions in thes devices are formed between semiconductors of different compositions and bandgaps, eg. GaAs/AIGaAs and InGaAs/InP. These novel devices offer potential advantages microwave, millimeter-wave, and high speed digital integrated circuit (IC) applications over the homojunction devices. With heterojunctions, device designers ean vary the band structure (and hence the electric field) as well as the doping level and thus obtain significant improvements in charge transport properties. In the HEMT, the epitaxial layer structure is designed so that free electrons in the channel are physically separated from the ionized donors, and electron mobility is enhanced by reducing ionized scattering [1] 1.1 Heterostructures A heterostructure ot heterojunctions occurs when contact is made between two semiconductor materials with different band-gap energies. Heterojunction FETS have shown great promise for high speed devices where the conventional MOSFET technology is reaching its limit due to various short channel effects and velocity saturation effects. The band-gap in the III-V semiconductors can be engineered by varying the mole fraction of the constituents and hence the device properties can also be tailored [2]. Heterojunction devices present difficult challenges to both device fabrication and device modeling engineers. The Volume: fabrication process requires doping density. layer thickness and material composition to be altered abruptly during the growth of the device structure. Extremely thin heterostructures are required in modem HEMT devices. Doping layer thickness and composition must all be very tightly controlled to produce a useful device. Fabrication of heterostructures also requires consideration of material lattice constants, thermal expansion coefficients and interface states [3] Fig. 1 shows the band diagram for a p-n heterojunction. The p-ype material (GaAs) has a smaller band-gap than the n= type material (AlGaAs). Hetons ANGaAs Sungtion |: Energy band diagram for a p-n heterojunction ‘The band discontinuities exist in both the conduction band and valence band. In Fig.1 these discontinuities are labeled as “AB.” and “AE,". The amount of conduction and valence band discontinuity for two materials forming a heterojunction is determined by a number of factors, including the band-gap energies and electron affinities of each of the materials [3] 5 Issue: 10 | Oct-2016, Available @ http://ijret.esatjournals.org 88.URET: Inter nal Journal of Research in Engineer Fig. 2 presents the band diagram for a Schottky barrier placed on a semiconductor heterostructure typically exploited for HEMT fabrication. The wide band-gap material is doped n-type, but is depleted of free carriers by the reverse or zero-biased Schottky contact. etype Schottky | AIGAAS ' 1 ‘undoped GaAs Get 1 t ' Fig 2: Energy Band diagram for a Schottky contact made to a heterostructure ‘The narrow band-gap material is lightly doped p-type. The ‘most important feature of the band diagram related to HEMT operation occurs at the heterojunction interface between the two materials. At this boundary, the band-gap discontinuities cause the conduction band of the narrow ‘band-gap material to dip below the Fermi level. The free carrier concentration is very high where the dip occurs. This region of high cartier concentration is very extremely thin and is the primary property of the heterostructure exploited in the fabrication of HEMT [3] 2. DEVICE STRUCTURE, Introduced in 1981, the conventional AIGaAvGaAs high clectron mobility transistor has offered both high speed and excellent gain, noise performance at microwave and millimeter-wave frequencies (3]. The HEMT represents an evolutionary improvement in the GaAs MESFET and has been used extensively in both hybrid and monolithic circuits. The HEMT has two ohmic contacts (source and drain) and a Schottky gate which modulates the flow of current in the channel between the two contacts. [As shown in Fig2, because of the conduction band discontinuity, AE, between the high band-gap AIGaAs and the undoped GaAs, clectrons are localized to a thin (=80A) two- dimensional electron gas layer on the Gas side of the AIGaASGaAs heterojunction interface. Because there are ‘no donor atoms intentionally present in the undoped GaAs layer, electrons in the 2-DEG channel do not undergo impurity scattering and hence exhibit high mobility and velocity. This structure scheme gives the HEMT not only superior electron transport properties in the channel but also much higher sheet charge density for high frequency ‘operation [1 Volume: g and Technology eISSN: 2319-1163 | pISSN: 2321-7308 n+ GaAs Capping Layer n+ AlGaAs Donor Layer AlGaAs Spacer Layer Undoped 2-DEG Channel —”” GaAs Bufer Layer Undoped Semi-insulating GaAs Substrate ‘GaAs based conventional HEMT ‘As shown in Fig.3 , the conventional AIGaAs/GaAs HEMT structure is typically composed of (a) n+ GaAs capping layer, (b) n+ AIGAAs donor or gate-bartier layer, (c) undoped AlGaAs spacer layer, (d) undoped GaAs channel, (©) undoped GaAs buffer, and () GaAs semi-insulating substrate ‘One way of improving the HEMT performance is to use InGaAs as the two-dimensional electron gas material instead of GaAs as shown on Fig.4. The benefits of using a thin InGaAs layer as the pseudomorphic channel in a HEMT include the enhanced electron transport in InGaAs as ‘compared to GaAs, improved confinement of carriets in the quantum well channel, and larger conduction band discontinuity at the AIGaAs/InGaAs hetero-interface which allows even higher current density and transconductance than possible with a AIGaAs/GaAs conventional HEMT. 2.1 GaAs based Pseudomorphic HEMT layer design n+ GaAs Capping Layer n+ AlGaAs Donor Layer TAIGaAs Spacer Layer Undoped InGaAs Channel Layer Undoped 2DEG Channel GaAs Bufer Layer Undoped ‘Semi-insulating GaAs Substrate Figure 4: GaAs based pseudomorphic HEMT The following sub-sections describe each layer and its importance for the HEMT structue. i. Capping Layer: ‘The GaAs capping layer, typically heavily doped with Si at approximately 10"%em™ provides good ohmic contact to the HEMT, reduces the device resistance, and also protects the AlGaAs donor layer from surface oxidation and depletion, !5 Issue: 10 | Oct-2016, Available @ http:/fijret.esatjournals.org 89LRT: International Journal of Research in En AlGaAs Donor Layer: ‘The AlGaAs donor layer should be depleted from both the AlGaAsGaAs heterojunction interface and the ‘Schottky gate to eliminate the parallel conduction of the AlGaAs in a HEMT. The donor layer is typically uniformly doped with Si at a very high doping level of | ‘approximately 10"/em* An important parameter in the ‘Al,Ga; «As donor layer is the AIAs mole fraction x. The conduction band discontinuity, AE. at the AlGa, Vigated IVI SSl222 —vidnin2V) BRERER gaR8G8 Time [s] © Fig 13: (a) Nor gate circuit schematic, (b) Nor gate circuit implementation, (¢) Output waveforms at S00 MHz 4.3 Nand Gate @ Volume: = Sass ob) ‘Nand gates and Nor gates being universal gates can be used for the implementation of any logic circuit in digital applications. The speed of communication is enhanced and also the noise is reduced. Fig. 15 and Fig. 16 show the implementation of the Nand and Nor gates using the developed HEMT structure, Vigan (V1 ee V(gate2)[V] —=Vedrain2)[V] VoltagelV] 1.60E-08 1.63E-08 © Fig 14: (a) Nand gate circuit schematic, (b) Nand gate circuit implementation, (e) Output waveforms at S00 MHz From Fig. 14(¢), 15(6) and 16(0), it is observed that, when two or more devices are connected in series, or parallel the difference between level 0 and level 1 reduces which for a series combination is further reduced as compared to the parallel combination, 5, FUTURE SCOPE We have found that the InGaAs HEMTs exhibit very promising logic characteristics. However, realizing the logic potential of InGaAs HEMTs will require a new device design with better electrostatic integrity. With further device ‘optimization in the form of scaled insulator thickness, positive Vr and a self-aligned gate design, InGaAs HEMTs could well be the technology of choice when the CMOS roadmap comes to an end (71[81. !5 Issue: 10 | Oct-2016, Available @ http:/fijret.esatjournals.org 93URET: Inter I Journal of Research in E 6. CONCLUSION In summary, we have developed a pseudomorphic HEMT structure for the implementation of logic gates which are the basic building blocks of the digital communication. The research supports the logic suitability of HEMT by using it in logic circuits. An attempt to take the digital ‘communication to a complete new level in terms of speed and noise is made in this research. As we look forward, HEMTs are uniquely positioned to expand the reach of lectronies in communications, signal processing, clectrical power management and imaging. REFERENCES [1] Fazal, Ali, HEMTs and HBTs: Device, Fabrication and Circuit, Artech House, pp. 1-6, 1991. [2] N.V. Uma Reddy, M.V, Chaitanya Kumar, “InGaAs! GaAs HEMT for High Frequency Applications”, International Journal of Soft’ Computing and Engineering (IJSCE), vol. 3, issue 1, Mar 2013. [3] Golio, John, Microwave MESFETs and HEMTs, Artech House, pp.24-70, 1991. [4] B.K.Mishra, Lochan Jolly, S.C Patil, “In, ,Ga,As a next generation material for photodetectors,” Cyber journal, JSAM, pp.9-16, April 2011 LH, Kim and J. A. del Alamo, “Beyond CMOS: Logic suitability of Ing GaAs HEMT." in Proc. CS ‘Mamtech, pp. 251-254, 2006. [6] B K Mishra, Lochan Jolly, Sonia Behra, “Submicron Model for illuminated gallium nitride HEMT", International Conference and Workshop on Emerging Trends in Technology, pp. 7-12, 2011 [7] Niamh Waldron, Dae-Hyun Kim, Jestis A. del Alamo, “A Self-Aligned InGaAs HEMT Architecture for Logic Applications”, IEEE Transactions on Electron Devices, vol.57, no.1, pp.297-304, Jan 2010. [8] LA. Del Alamo, “The High Electron Mobility ‘Transistor at 30: Impressive Accomplishments and Exciting Prospects,” CS Mantech Proc., pp. 17-22, 2011 BIOGRAPHIES Parita Mehta is currently pursuing her ME. in Electronics and ‘Telecommunication with Thakur College of Engineering and Technology, Mumbai University. Her research interests include device modeling in VLSI and Nanotechnology. Dr. Lochan Jolly completed her PhD in 2012 from the SNDT university and Matech in 2005 from IIT Bombay. She has 18 years of teaching experience. Her area of research is device modeling for high speed communication network. Volume: 5 Issue: 10 | Oct-2016, Available @ http: g and Technology eISSN: 2319-1163 | pISSN: 2321-7308 94,MESFET O e MESFET = Metal Semiconductor Field Effect Transistor = Schottky gate FET. e The MESFET consists of a conducting channel positioned between a source and drain contact region. e The carrier flow from source to drain is controlled by a Schottky metal gate. e The control of the channel is obtained by varying the depletion layer width underneath the metal contact which modulates the thickness of the conducting channel and thereby the current.BACK CONTACTMESFET O ° The key advantage of the MESFET is the higher mobility of the carriers in the channel as compared to the MOSFET. ° The disadvantage of the MESFET structure is the presence of the Schottky metal gate. e It limits the forward bias voltage on the gate to the turn-on voltage of the Schottky diode. e This turn-on voltage is typically 0.7 V for GaAs Schottky diodes. e The threshold voltage therefore must be lower than this turn-on voltage. e Asa result it is more difficult to fabricate circuits containing a large number of enhancement-mode MESFET.Basic Structure O e GaAs MESFETs are the most commonly used and important active devices in microwave circuits. e In fact, until the late 1980s, almost all microwave integrated circuits used GaAs MESFETs. e Although more complicated devices with better performance for some applications have been introduced, the MESFET is still the dominant active device for power amplifiers and switching circuits in the microwave spectrum.Basic Structure DEPLETION REGION GATE SOURCE n-TYPE CHANNEL BUFFER SEMI-INSULATING GaAs Schematic and cross section of a MESFETBasic Structure e The base material on which the transistor is fabricated is a GaAs substrate. e A buffer layer is epitaxially grown over the GaAs substrate to isolate defects in the substrate from the transistor. e The channel or the conducting layer is a thin, lightly doped (n) conducting layer of semiconducting material epitaxially grown over the buffer layer. e Since the electron mobility is approximately 20 times greater than the hole mobility for GaAs, the conducting channel is always n-type for microwave transistors.Basic Structure [ F< O ve SEMLINSULATING Gate Finally, a highly doped (n*) layer is grown on the surface to aid in the fabrication of low-resistance ohmic contacts to the transistor. This layer is etched away in the channel region. Alternatively, ion implantation may be used to create the n channel and the highly doped ohmic contact regions directly in the semi-insulating substrate. Two ohmic contacts, the source and drain, are fabricated on the highly doped layer to provide access to the external circuit. Between the two ohmic contacts, a rectifying or Schottky contact is fabricated. Typically, the ohmic contacts are Au—Ge based and the Schottky contact is Ti-Pt—Au.