UNIVERSITI KUALA LUMPUR
MALAYSIAN SPANISH INSTITUTE
SAB36603
ADVANCE DIGITAL DESIGN AND FPGA
LAB 1
INTRODUCTION TO FPGA EDA TOOL (QUARTUS II)
PREPARED BY:
STUDENT’S NAME ID NUMBER
NUR BATRISHA BALQIS BINTI MOHD SURAIS 54215119229
NURUL FARHANA BINTI MOHD FADZLI 54215119170
NURUL FARHANAH BINTI ZAKARIA 54215119177
LECTURER’S NAME: ENCIK MOHD REZAL BIN MOHAMED
1. OBJECTIVES
These labs introduce Quartus II software by designing simple digital circuits, compiling the design,
making simulations to view the outputs of the design, and eventually programing the device to test
the design physically:
The objectives of these labs are:
1. To learn how to create design entries and perform compilation and simulation using the
Quartus II software.
2. To design a simple 4‐bit full adder.
3. To familiarize ourselves with schematic‐based design flow for FPGA implementation using
logic gates and hierarchical modeling.
2. INTRODUCTION
A "project" in the Quartus II software is the entire collection of design files, configuration files, and
hierarchy details for a design. The Block Design File (*.bdf) is used to demonstrate the processes
required to develop a full adder project followed by a 4‐bit full adder project. The lower‐level design
files will be represented as blocks in this top‐level block. It demonstrates how to build a symbol file
produced by a hardware description language. Also provided are instructions for developing a unique
Mega function version. The lab's first project serves as an example of the top‐down design approach.
The Altera Quartus II design environment is introduced in the second section and is used to develop
FPGA‐based designs utilising the Altera DE2 board. To generate designs, use the schematic entry
method. A design must first be compiled before it can be tested for functionality and timing accuracy
(via simulation). To fix problems or performance bottlenecks, the verification and timing analysis
processes may necessitate going back to the early stages of the design cycle. The design can be
implemented in the FPGA on the Altera DE2 board if it complies with the specifications.
3. PROCEDURES
3.1 Create a Project
1. Choose File > New Project Wizard. If this is the first time you open the New Project Wizard,
the Introduction page will be displayed. Click Next to proceed to the first page of the wizard.
2. Type the directory name in the working directory box or use the Browse icon to select the
directory. For this example, type C:/Projects/adder4.
3. Type a name for the project in the project name box. For this example, type adder4.
4. Type adder4 as the name of the project in the top‐level design entity box.
5. Click Next. The Add Files page of the New Project Wizard appears. Because adder4 is a new
project, there are no files to add to this project yet. If the design files already exist for this
project, use the Browse icon to select the files, and click Add to add them to the project.
6. Click Finish to create the project and accept the default settings for the remaining wizard
prompts. The project is now created. The top‐level design entity name appears in the Hierarchy
tab of the Project Navigator window.
3.2 Create a Block Diagram
Step 1: Create a New Block Design File
1. Choose File > New. The New dialog box will appear.
2. Select Block Diagram/Schematic File under Design Files.
3. Click OK. A new Block Editor window appears.
4. Choose File > Save As. The Save As dialog box will appear.
5. Select the folder where you want to save the BDF file. The Save As dialog box
automatically displays the project directory path as the directory for saving the file.
6. In the File name box, type full_adder.
7. Ensure that Add file to current project is selected.
8. Click Save to save the file and add it to the project.
Step 2: Create the full_adder
1. In the Block Editor window, click the Symbol Tool icon on the toolbar.
2. Select xor symbol from the Libraries (under primitives > logic), and insert it to the design
space, as show in figure below.
3. Repeat Step 2 to insert two xor, two and2, and one or2.
4. Next, insert three input pins and two output pins (under primitives > pin).
5. Double‐click each pin to change the pin name.
6. Click the Orthogonal Node Tool icon on the toolbar. Connect the components as shown
below using the mouse by clicking, dragging, and releasing the mouse pointer.
7. Save the file.
Step 3: Create the full_adder Block
1. Create a new Schematic File and save as adder4.bdf in the same project folder.
2. In the Block Editor window, click the Block Tool icon on the Block Editor toolbar.
3. Click a blank space in the Block Editor and drag the Block Tool pointer until the block is the
size you want.
4. Click the Selection Tool button on the toolbar.
5. With the Selection Tool, double‐click the block_name default block name.
6. To rename the block_name default block name, type full_adder and press Enter.
7. With the Selection Tool, select the full_adder block.
8. Choose Block Properties (right‐click). The General tab of the Block Properties dialog box
appears.
9. Under I/O, type Cin in the Name box as the first port name, and in the Type list, select
INPUT.
10. Click Add. The Cin port name appears in the Existing block I/Os list. Similarly, complete the
rest of the input/output ports.
11. Click OK. You have now specified the input and output ports of the full_adder block.
12. Select the full_adder block.
13. Choose AutoFit (right‐click). This command resizes the border of the full_adder block to fit
proportionally around the I/O ports table, and ensures that all data about the block is visible.
Step 4: Create the 4‐bit adder, adder4
1. Select the full_adder block and make four copies by copy/paste.
2. Add three input pins and two output pins.
Step 5: Arrange the Blocks, Primitives, and Megafunction
Click the Selection Tool icon on the toolbar, or press Esc, to activate the Selection Tool. Drag
the blocks, primitives, and megafunction to arrange them as shown in the illustration below.
Step 6: Change the Block Editor Display Options
1. Choose Tool > Options. The General page of the Options dialog box is displayed.
2. In the Category list, select Block/Symbol Editor. The Block/Symbol Editor page appears.
3. In the Block/Symbol Editor page, select or clear the appropriate settings, according to your
preferences.
4. To modify the colors of screen elements and fonts used in the Block Editor window, in the
Category list, select Colors or Fonts under Block/Symbol Editor. Select or clear the
appropriate settings in the corresponding pages.
5. Click OK.
Step 7: Name the Pins
1. With the Selection Tool, double‐click the default pin_name pin name of the first input pin
symbol you entered.
2. To rename the pin_name default block name, type the new name and press Enter.
3. Repeat steps 1 and 2 to rename each of the pins with the following names:
4. Choose File > Save.
3.3 Connect Symbols and Blocks
Step 1: Draw Conduit Lines
1. Click the Orthogonal Conduit Tool icon on the toolbar.
2. Click the pinstub of the Cin input pin to define the start of the conduit, and then drag the
mouse pointer to draw a line that connects to the border of the first full_adder block. A
"mapper" symbol appears automatically on the edge of the full_adder block where the
conduit connects to the block. A mapper allows you to map I/O port(s) in the block to
signal(s) in the conduit.
3. Repeat steps 1 through 2 to make additional connections between the symbols and blocks
shown in figure below.
Step 2: View Conduit Properties
1. Click the Selection Tool icon on the toolbar.
2. Select the conduit that connects the INPUT pin Cin to the first full_adder block, and choose
Properties (right‐click). The Conduit Properties dialog box appears.
3. Click the Signals tab. The Connections list shows the signal connections for the selected
conduit.
4. Ensure that the signals are correct, and then click OK.
5. For A[3..0], B[3..0], and S[3..0], the port mapping should be manually defined. Edit the
signals property for A[3..0] as shown below:
6. The figure below shows the results after port mapping for ports A, B, and S:
Step 3: Draw Lines with the Selection Tool
1. Click the Selection Tool icon on the toolbar.
2. Place single wires for carry signals by drawing a line that connects the full_adder blocks to
one another. The Selection Tool automatically chooses the conduit line style.
3. Choose File > Save.
Step 4: Overview – Mapping Signals between Blocks
Step 5: Map Signals Explicitly
1. Double‐click the mapper symbol. The General tab in the Mapper Properties dialog box will
appear.
2. Click the Mappings tab.
3. In the I/O on block list, select Cout.
4. In the Signals in conduit box, type C1.
5. To map the connection, click Add. The mapping appears in the Existing mappings list.
6. Click OK. The signal Cout is added to the bus, and a mapper table appears that shows the
mapping information.
7. Repeat steps 1 to 6 to continue mapping connections between I/O signals in blocks to
differently named I/O signals in other blocks for the rest of the full_adder blocks.
8. Choose File > Save. The BDF is complete.
4. Compilation
4.1 Compile the Design
Step 1: Start a Full Compilation
1. Choose Processing > Start Compilation. The Compiler immediately begins to process the
adder4 design. As the design compiles, the Tasks window automatically displays, in
percentage, the total compilation progress and the time spent in each module of the
compilation.
2. If you receive a message indicating that the full compilation was successful and there are no
errors displayed in the Messages window, click OK to close the message box.
Step 2: Locate the Source of a Message
1. In the Messages window, click the icon to expand the Found 1 design units, including 1
entity, in source file adder4.bdf information message.
2. Double‐click the Found entity 1: adder4 expanded information message. The adder4.bdf file
opens.
3. Should there be any error in the compilation process, the description and possible solution to
rectify the error can be obtained by right clicking the error message.
Step 3: View the Compilation Report
1. In the left pane of the Compilation Report window, click the icon to expand any report window
folder.
2. In the left pane of the Report window, select the Report section you want to open. The
report appears in the right pane of the window.
5. Simulation
5.1 Create a Waveform File for Simulation
Step 1: Create a New Vector Waveform File
1. Choose File > New. The New dialog box appears.
2. To select VWF as the file type, click University Program VWF under Verification/Debugging Files.
3. Click OK. The Waveform Editor opens, displaying an empty waveform file.
4. To change the end time for the file, choose Edit > End Time.
5. In the Time box, type 700 and select ns in the list.
6. Click OK.
7. To save the file as adder4.vwf, choose File > Save As. The Save As dialog box
appears.
8. In the Save in list, select the adder4 directory.
9. In the File name box, type adder4.
10. Click Save.
Step 2: Add Input and Output Nodes to the File
1. To find the node names you want to add to the file, choose Edit > Insert > Insert Node Or
Bus. Click on Node Finder, the Node Finder appears.
2. In the Node Finder, select Pins: all in the Filter list.
3. To find the nodes you want to add to the VWF, click List.
4. In the Nodes Found list, select the A, B, Cin, Cout, and Cin pins and drag them into the Name
column of the VWF.
5. Close the Node Finder
Step 3: Edit the Cin Input Node Waveform
1. If necessary, click the Selection Tool icon on the toolbar.
2. To select the entire Cin input node waveform, click the Selection Tool on the "handle" of the
Cin node. The entire node, including the waveform, is highlighted.
3. Click Forcing Low icon in the toolbar. The value of Cin becomes zero.
Step 4: Edit the An Input Bus Waveform
1. To select the entire A input bus waveform, click the Selection Tool on the waveform's handle. The
entire bus, including the waveform, is highlighted.
2. Click Arbitrary Value icon in the toolbar. The Arbitrary Value dialog box appears.
3. In the Radix list, select Hexadecimal.
4. In the Numeric or named value list, type 4.
5. Click OK. When a message asks if you want to change the radix of the other nodes in the A input
bus waveform, click Yes. The A input bus waveform is displayed with a hexadecimal value of 4.
Step 5: Edit the B Input Bus Waveform
1. To select the entire B input bus waveform, click the Selection Tool on the waveform's handle. The
entire bus, including the waveform, is highlighted.
2. Choose Arbitrary Value toolbar button. The Arbitrary Value dialog box appears.
3. In the Radix list, select Hexadecimal.
4. In the Numeric or named value list, type 2.
5. Click OK. When a message asks if you want to change the radix of the other nodes in the A input
bus waveform, click Yes. The A input bus waveform is displayed with a hexadecimal value of 2.
6. To save the file, choose File > Save.
5.2 Simulate the Design
Step 1: Run the Simulator
1. In the waveform editor, choose Run Timing Simulation icon (from the Simulation menu or
main toolbar). The Simulator immediately begins to simulate the adder4 design entity using
the specified timing simulation and the adder4.vwf vector source file A popup window will
show the progress of the simulation, then automatically close when it is complete.
2. A second Simulation Waveform Editor window as in Figure below then opens the output
waveform. The results of the simulation are updated in a new pop‐up Simulation Waveform
Editor.
3. The output waveform is read‐only, so any changes in simulation must be done by modifying
the adder4.vwf file and restimulating the circuit
5.3 Analyze the Simulation Results
Step 1: View the Simulation Waveform Section
1. If necessary, in the left pane of the Simulator Report window, select Simulation Waveforms.
The Simulation Waveforms section appears in the right pane of the Report window.
2. To see the entire waveform, choose Fit in Window.
The Waveform Editor allows you to manipulate the data in the following ways:
You can change the radix used to display group values by selecting a group, choosing
Properties (right‐click), and selecting a new radix in the Radix list.
You can move the master time bar right and left to successive transitions by clicking the
movement arrows. You can also drag the master time bar by its handle.
You can zoom in and out with the Zoom Tool icon on the toolbar, and with the Zoom In,
Zoom Out, Fit in Window, and Zoom commands (View menu).
You can create additional time bars and use them to measure distances between transitions.
Step 2: Create a Time Bar
1. With the Selection Tool, click the master time bar handle and drag it until the Master Time
Bar box displays 40.0 ns.
2. Move the Selection Tool pointer in the waveform to the time of 80 ns. At the top of the
window, the Pointer box displays 100.0 ns, the time where the pointer is located. Note that
the Interval box displays 60.0 ns, the time difference between the master time bar and the
Selection Tool location.
3. Double‐click in the waveform drawing area, a new time bar appears on the waveform at
100.0 ns.
4. The text +60.0 ns is shown above the second time bar, indicating the time difference from
the new time bar to the master time bar
6. Conclusion
Based on this Lab 1, we have successfully designed a simple 4‐bit full adder. As the name
implies, a 4‐bit full adder can add four input bits. The definition of a 4‐bit full adder is a
logical circuit that accepts a carry signal and two 4‐bit expressions as inputs and outputs a 4‐
bit output along with the carry signal. The XOR Gate, AND Gate, and OR Gate make up the 4‐
bit full adder circuit.
As seen from the result displayed in the simulation waveform above, we can analyse the
result of 4‐bit full adder as follow:
The 4‐bit full adder operates in interesting manner. The addition of input bits is done by the
XOR Gates. We connect two AND gates to the circuit in order to complete the addition
circuit so that the carry is produced when the addition result connects to the OR gate. In the
designing of circuit, we simply make a small circuit of AND Gate and XOR Gate Then we
create a 2‐bit complete adder circuit. The highlight of the circuit is that we'll duplicate the
block and arrange four blocks so that each block's input carry becomes its output carry. This
cycle will continue and at the fourth block we get the resultant carry of whole calculation.
