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System In Package (SiP) and
Stacked Package Solutions
Denis Soldo and Robert Myoung
Applications Engineers
Ansoft Corporation
2006 Worldwide Application Workshop
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Objectives
System in Package Overview
SiP Engineering Challenges
Ansoft SiP SI solution
Conclusion
3
What is System-in-Package (SiP)?
Higher levels of integration are driven by technological
advancements in silicon, electrical performance
requirements and form factor constraints.
SiP is the evolution of earlier MCM packaging concepts.
SiP contains one or more die
Combinations of wire-bond and flip-chip
Memory and logic are combined with passives, filters, antennas
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SiP Benefits
SiP provides a unified solution to the system architect
Smaller system size
Increased system density
Lower system power consumption
Cost reduction
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SiP/3D Package Concepts
Multiple Component
Variations of die configurations including side by side, stacked or both
providing the smallest form factor solution.
Combinations of logic, silicon interposers, passives etc.
Package-in-Package
Package structure that stacks a fully tested Internal Stacking Module
(ISM) on top of a Base Assembly Package (BAP) to form a single
package solution.
Package-on-Package
Package structure in which fully tested packages are assembled
vertically.
Individual package complexities can vary.
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System-in-Package
WB/MCM
WB/Die stack
SMD
Si-based
Flip-chip
Laminate Leadframe Wafer
based based level
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SiP Applications
Cell phones features throughout the history
Basic phone call
SMS messages
Photo, video, music, sports, Live TV, web…..
Diverse application type
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SiP Integration Levels
Samsung SPH-X4200 cell phone layout
3G CDMA technology
Memory requirements for cell phones are increasing
Different companies collaboration
AMD
Stacked Memory Package
AMD/Fujitsu Flash Die
Samsung SRAM Die
Fujitsu
Stacked Memory Package
AMD/Fujitsu Flash Die
Source: Portelligent
NEC FCRAM Die
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SiP Engineering Challenges
Today’s 3D SiP architecture is evolving now!
Interactions of various components
Variations of die stacking approaches
3D nature of wirebonds and bumps and balls
Competing signalling architectures
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SiP Engineering Challenges
Virtual design and validation
High performance-low cost package design
Packages and dies from different companies
More complex than single-chip package
Intra-die bondwire coupling
Coupling between stacked packages
Seek the best EDA tools available
Build a virtual prototyping methodology around Architects and
Engineers.
Understanding the methods in which solvers work.
Choose the right tools (methods)
Co-design between IC and package is vital
Moving from traditional design and analysis methods to a virtual
engineering team environment
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Objectives
System in Package Overview
SiP Engineering Challenges
Ansoft SiP SI solution
Conclusion
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Ansoft SiP SI Solution
(emphasis on PoP)
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Ansoft SiP SI Solution
Top Package Bottom Package
Vendor A Vendor B
Automation
System Initial Design
Performance Validation
Electrical,
Optimization Thermal and
Mechanical
Final System System Jitter,
Verification Eye Diagram
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Package on Package
Source: Amkor
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Package-on-Package
(courtesy of Amkor)
Top package : Memory device (DRAM and flash)
Bottom package : High density digital or mixed-signal logic
devices
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Design Validation Optimization Final System Verification
Design Validation
Merge Package Layouts
Full Package RLC
Crosstalk Analysis
Design Validation Optimization Final System Verification 17
Package/PCB Merge Utility
Overview of Ansoft Merge utility
• 3rd party top package
• 3rd party bottom package
• Merge .siw files to preserve:
• All R, L, C Components
• All IO, IC Discrete Device
Footprint and Pin Information
Design Validation Optimization Final System Verification 18
Package/PCB Merge Utility
Overview of Ansoft Merge utility
Design Validation Optimization Final System Verification 19
Package/PCB Merge Utility
Overview of Ansoft Merge utility
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Package on Package/View
Design Validation Optimization Final System Verification 21
Full Package RLC Extraction
TPA v5.0 TM
Designed to handle complex SiP layouts
Stacked die
Cascaded wirebonds
Die-to-die wirebonds
Trace-to-trace wirebonds
Full package and selected nets extraction
Full 3D DC resistance computation
User-defined (sketched) wirebond profiles
Source: NXP
Design Validation Optimization Final System Verification 22
PoP Validation
TPA v5.0 TM
Initial Layout Validation
Simulation data
Selected Nets
Design Validation Optimization Final System Verification 23
PoP Validation
®
TPA v5.0 data in DesignerSI /Nexxim
TM TM
Quick validation
Crosstalk data of critical nets
Nominal case
Merged Design
Top and bottom package
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Design Validation Optimization Final System Verification
Optimization:
Automation
Electrical
Thermal
Mechanical
Design Validation Optimization Final System Verification 25
Automation
AnsoftLinks v4.0 TM
Prepare the Design for Optimization
Automated 3D Model creations
Q3D project
HFSS project
Automatically defined
Ports and Boundaries
Design Validation Optimization Final System Verification 26
Electrical, Thermal, Mechanical
Routing (trace width and spacing)
Bondwire profile
Solderball profile
Design Validation Optimization Final System Verification 27
Optimize Bondwire profile
®
Q3D Extractor simulation data
Critical design parameter
True 3D bondwire modelling
Impact of wire length and
bondwire radius on resistance
Bondwire Diameter
Bondwire Length
URAM_D0
URAM_D1
URAM_D3
URAM_D5
Design Validation Optimization Final System Verification 28
Wire Length Resistance Effect
URAM_D0
URAM_D1
URAM_D3
URAM_D5
Bondwire resistance will increase dramatically
due to increase in wire length
Design Validation Optimization Final System Verification 29
Bondwire Diameter Optimization
Optimize bondwire radius
25.4 um to 20 um
Cost savings in gold
URAM_D0
URAM_D1
URAM_D3
URAM_D5
Design Validation Optimization Final System Verification 30
Optimize Simulation Run Times
Distributed Solve
Distributed solve enables engineers to distribute the computational load of a
parametric design sweep or frequency sweep across a network or cluster of
computer workstations.
Distributed Solve enables engineers to efficiently characterize an entire design
space in a fraction of the time it takes a single computer
Host Computer
…
…
Remote Computers
(Up to 10 remote computers per Distributed Solve license)
Design Validation Optimization Final System Verification 31
Optimize Simulation Run Times
Trace width and spacing parameterization using Q3D
Distributed Solve Option in action
DSO In Progress
Trace width
Design Validation Optimization Final System Verification 32
Optimize Simulation Run Times
DSO Setup
25 Parametric Case
HeadNode: Dual-Dual-Core
AMD 2.2GHz 16GB RAM
Nodes: 16 Dual Processor
AMD 2.6GHz 8GB RAM
Nominal Case
6 hrs 51 min
DSO Solution Time
26 min !!!
6hr 51 min
Time Savings
15x speed up !
DSO Solution Time
Design Validation Optimization Final System Verification 33
Optimize 3D Routing
3D EM Based circuit co-design
Changed Routing
Trace length and spacing
Crosstalk analysis
Optimized Case
Component Editor
50mV improvement !
Nominal Case (pink)
Improved Case (blue)
DesignerSI /Nexxim
TM ®
Near-End Crosstalk noise data
Schematic view
Tr=200ps
Design Validation Optimization Final System Verification 34
Thermal Effects
ePhysics TM
Critical 3D Thermal and stress
analysis
Thermal analysis
∆ T: 64.56[C] ∆ T: 61.51[C]
Thermal distribution on bondwires
Single vs. double bondwire
Thermal distribution wire pads
No wirebonds present
Design Validation Optimization Final System Verification 35
Mechanical Effects
ePhysics
TM
Reduced design cycle time limits
the use of testing to evaluate
reliability.
Solderball interconnect reliability
Stress induced strains in solder
joints
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Design Validation Optimization Final System Verification
Final System Verification
Input/Output driver effects
Eye Diagram
Jitter
Design Validation Optimization Final System Verification 37
Final System Verification
®
Time domain simulations using Nexxim
Rise time = 200 ps
Dynamically linked parameterized Q3D project
IBIS v4.0 driver model for DDR 2
1
Vcc vcc2
1e-009
0.1pF
1.8V
U1
Nexxim2
1
0 pullup 0
Port1
Tx Port2
E244 logic_in out
0
0.1pF
enable out_of_in
pulldown
0
1
0
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Conclusions
3D complexity of SiP packages is dramatically increased
with huge time to market demands
Electrical, mechanical and thermal validation and
optimization of 3D packages is vital for meeting high
performance goals
Analysis thru virtual prototyping increases engineering
efficiency and reduces cost.
Parametric Co-design analysis is required
Ansoft offers 3D EM simulations combined with powerful
circuit simulations when solving SiP SI challenges
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Acknowledgments
Special Thanks to:
NXP
Amkor
for their contribution and assistance with creating
this material.
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Thank You!
Ansoft Corporation
2006 Worldwide Application Workshop
