Sequential Statements
Based on slide from Pong P. Chu
Outline
1. VHDL process
2. Sequential signal assignment statement
3. If statement
4. Case statement
5. Simple for loop statement
COEN313 - 2
1. VHDL Process
• Contains a set of sequential statements to be
executed sequentially
• The whole process is a concurrent statement
• Can be interpreted as a circuit part enclosed inside of
a black box
• May or may not be able to be mapped to physical
hardware
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• Two types of process
– A process with a sensitivity list
– A process with wait statement
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A process with a sensitivity list
• Syntax
process(sensitivity_list)
declarations;
begin
sequential statement;
sequential statement;
...
end process;
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• A process is like a circuit part, which can be
– active (known activated)
– inactive (known as suspended).
• A process is activated when a signal in the sensitivity
list changes its value
• Its statements will be executed sequentially until the
end of the process
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• E.g, 3-input and circuit
signal a,b,c,y: std_logic;
process(a,b,c)
begin
y <= a and b and c;
end process;
• How to interpret this:
process(a)
begin
y <= a and b and c;
end process;
• For a combinational circuit, all input should be
included in the sensitivity list
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A process with wait statement
• Process has no sensitivity list
• Process continues the execution until a
wait statement is reached and then
suspended
• Forms of wait statement:
– wait on signals;
– wait until boolean_expression;
– wait for time_expression;
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• E.g, 3-input and circuit
process
begin
y <= a and b and c;
wait on a, b, c;
end process;
• A process can has multiple wait statements
• Process with sensitivity list is preferred for
synthesis
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2. Sequential signal
assignment statement
• Syntax
signal_name <= value_expression;
• Syntax is identical to the simple
concurrent signal assignment
• Caution:
– Inside a process, a signal can be assigned
multiple times, but only the last assignment
takes effect
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• E.g.,
process(a,b,c,d)
begin -- yentry := y
y <= a or c; -- yexit := a or c;
y <= a and b; -- yexit := a and b;
y <= c and d; -- yexit := c and d;
end process; -- y <= yexit
• It is same as
process(a,b,c,d)
begin
y <= c and d;
end process;
• What happens if the 3 statements are
concurrent statements?
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Process
• A process is a finite group of
instructions:
– It’s executed each time a signal in its
sensitivity list change
– The instruction are executed sequentially
inside the process
– The new value of signals are available at
the end of the process
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Example 1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY another_mux_def IS
PORT ( data_in1,data_in2 : IN STD_ULOGIC;
select_in : IN STD_LOGIC;
output : OUT STD_ULOGIC);
END ENTITY;
ARCHITECTURE beh OF another_mux_def IS
BEGIN
p0: PROCESS (data_in1, data_in2, select_in)
BEGIN
IF select_in = '0' THEN
output <= data_in1;
ELSE
output <= data_in2;
END IF;
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END PROCESS; END beh;
simulation
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Example 2
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ARCHITECTURE beh_bug OF another_mux_def IS
BEGIN
p0: PROCESS (data_in1, select_in)
BEGIN
IF select_in = '0' THEN
output <= data_in1;
ELSE
output <= data_in2;
END IF; simulation result
END PROCESS;
END beh_bug;
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Execution inside a process
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY sig_ass IS END ENTITY;
ARCHITECTURE beh OF sig_ass IS
SIGNAL sum1,sum2 : INTEGER;
BEGIN
p0: PROCESS
BEGIN
WAIT FOR 10 ns;
sum1 <= sum1 + 1;
sum2 <= sum1 + 1;
END PROCESS;
END beh;
Start simulation with the value 0 for sum1 and
sum2; COEN313 - 17
simulation
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Signal assignment
Time sum1 sum2
0 0 0
10 0 0
10 + 1 Δ 1 1
20 1 1
20 + 1 Δ 2 2
30 2 2
30 + 1 Δ 3 3
Signals are updated at the end of a process. If a process
is reading the value of signal, it will read the old (non-
updated value!)
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Another example!
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY and_or IS
PORT ( a,b,c,d : IN STD_LOGIC;
output : OUT STD_ULOGIC);
END ENTITY;
ARCHITECTURE beh OF and_or IS
SIGNAL x,y : STD_LOGIC;
BEGIN
my_process : PROCESS (a,b,c,d)
BEGIN
x <= a OR b;
y <= c OR d;
output <= x AND y;
END PROCESS;
END beh;
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Simulation/Synthesis
• compile well!
• simulation shows a
problem!
• synthesis with a
warning concerning the
x,y signals! to a
correct circuit!
• post-level simulation
will show a mismatch
between the VHDL
code and the netlist
obtained from
synthesis!
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Why the simulation fails?
my_process : PROCESS (a,b,c,d)
BEGIN
x (new_value)<= a(event_value) OR b(old_value);
y (new_value)<= c(old_value) OR d(old_value);
output(new_value) <= x(old_value) AND y(old_value)
END PROCESS;
Assume an event occurs on a, I.e, a changes value!
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Why the simulation fails?
my_process : PROCESS (a,b,c,d)
BEGIN
x (new_value)<= a(old_value) OR b(event_value);
y (new_value)<= c(old_value) OR d(old_value);
output(new_value) <= x(old_value) AND y(old_value);
END PROCESS;
Assume an event occurs on b, I.e, b changes value!
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Why the simulation fails?
my_process : PROCESS (a,b,c,d)
BEGIN
x (new_value)<= a(old_value) OR b(old_value);
y (new_value)<= c(event_value) OR d(old_value);
output(new_value) <= x(old_value) AND y(old_value);
END PROCESS;
Assume an event occurs on c, I.e, c changes value!
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Why the simulation fails?
my_process : PROCESS (a,b,c,d)
BEGIN
x (new_value)<= a(old_value) OR b(old_value);
y (new_value)<= c(old_value) OR d(event_value);
output(new_value) <= x(old_value) AND y(old_value);
END PROCESS;
Assume an event occurs on d, I.e, d changes value!
Signals are updated at the end of a process. If a process
is reading the value of signal, it will read the old (non-
updated) value! COEN313 - 26
Why the simulation fails?
my_process : PROCESS (a,b,c,d)
BEGIN
x (new_value)<= a(event_value) OR b(old_value);
y (new_value)<= c(old_value) OR d(event_value);
output(new_value) <= x(old_value) AND y(old_value);
END PROCESS;
Assume an event occurs on a and d , I.e, a,d change value!
Signals are updated at the end of a process. If a process
is reading the value of signal, it will read the old (non-
updated value!) COEN313 - 27
How to solve this bug!
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- suppose that the and_or entity has been
-- already compiled!
ARCHITECTURE beh_fix1 OF and_or IS
SIGNAL x,y : STD_LOGIC;
BEGIN
my_process : PROCESS (a,b,c,d)
BEGIN
x <= a OR b;
y <= c OR d;
-- output <= x AND y;
END PROCESS;
output <= x AND y;
END beh_fix1; COEN313 - 28
Simulation/Synthesis
• compile well!
• simulation well!
• synthesis well!
• the resulting
hardware is the
same as for
and_or(beh).
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my_process : PROCESS (a,b,c,d)
BEGIN
x (new_value)<= a(event_value)OR b(old_value);
y (new_value)<= c(old_value) OR d(old_value);
END PROCESS;
output(new_value)<= x(new_value)AND y(new_value);
the new value of x and y is made available to the
rest of CSA!
Assume an event occurs on a, I.e, a changes value!
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How to solve this bug! (another solution)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- suppose that the and_or entity has been
-- already compiled!
ARCHITECTURE beh_fix2 OF and_or IS
SIGNAL x,y : STD_LOGIC;
BEGIN
my_process : PROCESS (a,b,c,d,x,y)
BEGIN
x <= a OR b;
y <= c OR d;
output <= x AND y;
END PROCESS;
END beh_fix1; COEN313 - 31
• compile well!
Simulation/Synthesis
• simulation well!
• synthesis well!
• the resulting hardware is
the same as for
and_or(beh).
my_process : PROCESS (a,b,c,d,x,y)
BEGIN
x (new_value)<= a(event_value) OR b(old_value);
y (new_value)<= c(old_value) OR d(event_value);
output (new_value) <= x(new_value) AND y(new_value);
END PROCESS;
Assume an event occurs on a and d , I.e, a,d change value!
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3. Variable assignment
statement
• Syntax
variable_name := value_expression;
• Assignment takes effect immediately
• No time dimension (i.e., no delay)
• Behave like variables in C
• Difficult to map to hardware (depending
on context)
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• E.g.,
process(a,b,c)
variable tmp: std_logic;
begin
tmp := '0';
tmp := tmp or a;
tmp := tmp or b;
y <= tmp;
end process;
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• interpretation:
process(a,b,c)
variable tmp0, tmp1, tmp2: std_logic;
begin
tmp0 := '0';
tmp1 := tmp0 or a;
tmp2 := tmp1 or b;
y <= tmp2;
end process;
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• What happens if signal is used?
process(a,b,c,tmp)
begin -- tmpentry := tmp
tmp <= '0'; -- tmpexit := ‘0’;
tmp <= tmp or a; -- tmpexit := tmpentry or a;
tmp <= tmp or b; -- tmpexit := tmpentry or b;
end process; -- tmp <= tmpexit
• Same as:
process(a,b,c,tmp)
begin
tmp <= tmp or b;
end process;
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3. IF statement
• Syntax
• Examples
• Comparison to conditional signal assignment
• Incomplete branch and incomplete signal assignment
• Conceptual Implementation
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Syntax
if boolean_expr_1 then
sequential_statements;
elsif boolean_expr_2 then
sequential_statements;
elsif boolean_expr_3 then
sequential_statements;
...
else
sequential_statements;
end if;
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E.g., 4-to-1 mux
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E.g., 2-to-22 binary decoder
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E.g., 4-to-2 priority encoder
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Comparison to conditional
signal assignment
• Two statements are the same if there
is only one output signal in if statement
• If statement is more flexible
• Sequential statements can be used in
then, elsif and else branches:
– Multiple statements
– Nested if statements
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e.g., find the max of a, b, c
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e.g., 2 conditional sig assignment codes
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• 2 conditional sig assign implementations
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e.g., “sharing” boolean condition
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Incomplete branch and
incomplete signal
assignment
• According to VHDL definition:
– Only the “then” branch is required; “elsif”
and “else” branches are optional
– Signals do not need to be assigned in all
branch
– When a signal is unassigned due to
omission, it keeps the “previous
value” (implying “memory”)
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Incomplete branch
• E.g., • It implies
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• fix
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Incomplete signal assignment
• E.g.,
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• Fix #1: • Fix #2
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Conceptual implementation
• Same as conditional signal assignment
statement if the if statement consists
of
– One output signal
– One sequential signal assignment in each
branch
• Multiple sequential statements can
be constructed recursively
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e.g.
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e.g.
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4. Case statement
• Syntax
• Examples
• Comparison to selected signal assignment statement
• Incomplete signal assignment
• Conceptual Implementation
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Syntax
case case_expression is
when choice_1 =>
sequential statements;
when choice_2 =>
sequential statements;
...
when choice_n =>
sequential statements;
end case;
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E.g., 4-to-1 mux
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E.g., 2-to-22 binary decoder
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E.g., 4-to-2 priority encoder
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Comparison to selected
signal assignment
• Two statements are the same if there
is only one output signal in case
statement
• Case statement is more flexible
• Sequential statements can be used in
choice branches
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Incomplete signal
assignment
• According to VHDL definition:
– Signals do not need to be assigned in all
choice branch
– When a signal is unassigned, it keeps the
“previous value” (implying “memory”)
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Incomplete signal assignment
• E.g.,
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• Fix #1:
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• Fix #2:
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Conceptual implementation
• Same as selected signal assignment
statement if the case statement
consists of
– One output signal
– One sequential signal assignment in each
branch
• Multiple sequential statements can
be constructed recursively
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e.g.
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5. Simple for loop statement
• Syntax
• Examples
• Conceptual Implementation
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• VHDL provides a variety of loop constructs
• Only a restricted form of loop can be synthesized
• Syntax of simple for loop:
for index in loop_range loop
sequential statements;
end loop;
• loop_range must be static
• Index assumes value of loop_range from left to
right
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• E.g., bit-wide xor
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• E.g., reduced-xor
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Conceptual implementation
• “Unroll” the loop
• For loop should be treated as “shorthand” for
repetitive statements
• E.g., bit-wise xor
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• E.g., reduced-xor
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Synthesis of
sequential statements
• Concurrent statements
– Modeled after hardware
– Have clear, direct mapping to physical structures
• Sequential statements
– Intended to describe “behavior”
– Flexible and versatile
– Can be difficult to be realized in hardware
– Can be easily abused
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• Think hardware
• Designing hardware is
not converting a C
program to a VHDL
program
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Parity generator using a signal
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY parity_generator IS
PORT ( in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
parity_out : OUT STD_LOGIC);
END parity_generator;
ARCHITECTURE rtl OF parity_generator IS
SIGNAL parity_internal : STD_LOGIC;
BEGIN
PROCESS (in1, parity_internal)
BEGIN
parity_internal <= '0';
FOR index IN in1'RANGE LOOP
parity_internal <= parity_internal XOR in1(index);
END LOOP;
END PROCESS;
parity_out <= parity_internal;
END rtl;
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Parity generator using a signal (Cont’D)
PROCESS (in1, parity_internal)
BEGIN
parity_internal <= '0';
parity_internal <= parity_internal XOR in1(3);
parity_internal <= parity_internal XOR in1(2);
parity_internal <= parity_internal XOR in1(1);
parity_internal <= parity_internal XOR in1(0);
END PROCESS;
in1(3:0) 0001 0011 0111 1111
parity_internal U U U U
parity_out U U U U
è parity_internal is initialized to U at simulation start-up.
è signals are updated only at the END of the PROCESS.
è If you initialize parity_internal to ‘0’, the simulator enter
an infinite loop of delta cycles without advancing the
simulation time.
COEN313 - 81
Parity generator using a signal (Cont’D)
• In general, if within a
combinational process, a
signal appears on both
sides of the signal
assignment operator,
combinational feedback
will be inferred
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Parity generator using a variable
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY parity_generator IS
PORT ( in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
parity_out : OUT STD_LOGIC);
END parity_generator;
ARCHITECTURE rtl OF parity_generator IS
BEGIN
PROCESS (in1)
VARIABLE parity_internal : STD_LOGIC;
BEGIN
parity_internal := '0';
FOR index IN in1'RANGE LOOP
parity_internal := parity_internal XOR in1(index);
END LOOP;
parity_out <= parity_internal;
END PROCESS;
END rtl;
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Parity generator using a variable (Cont’D)
PROCESS (in1)
BEGIN
parity_internal := '0';
parity_internal := parity_internal XOR in1(3);
parity_internal := parity_internal XOR in1(2);
parity_internal := parity_internal XOR in1(1);
parity_internal := parity_internal XOR in1(0);
parity_out <= parity_internal;
END PROCESS;
in1(3:0) 0001 0011 0111 1111
parity_internal 1 0 1 0
parity_out 1 0 1 0
è variables are updated immediately.
è variables holds a new value after each execution
of variable assignment à Temporal separation
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Parity generator using a
variable (Cont’D)
è In synthesis, a new
wire will be created to
hold the
temporary value. à
Spatial separation.
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