`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// ECE369 - Computer Architecture
// Laboratory 2
//
//
// Student(s) Name and Last Name: FILL IN YOUR INFO HERE!
//
//
// Module - register_file.v
// Description - Implements a register file with 32 32-Bit wide registers.
//
//
//
// Email this module to the TA
//
// INPUTS:-
// ReadRegister1: 5-Bit address to select a register to be read through 32-Bit
// output port 'ReadRegister1'.
// ReadRegister2: 5-Bit address to select a register to be read through 32-Bit
// output port 'ReadRegister2'.
// WriteRegister: 5-Bit address to select a register to be written through 32-Bit
// input port 'WriteRegister'.
// WriteData: 32-Bit write input port.
// RegWrite: 1-Bit control input signal.
//
// OUTPUTS:-
// ReadData1: 32-Bit registered output.
// ReadData2: 32-Bit registered output.
//
// FUNCTIONALITY:-
// 'ReadRegister1' and 'ReadRegister2' are two 5-bit addresses to read two
// registers simultaneously. The two 32-bit data sets are available on ports
// 'ReadData1' and 'ReadData2', respectively. 'ReadData1' and 'ReadData2' are
// registered outputs (output of register file is written into these registers
// at the falling edge of the clock). You can view it as if outputs of registers
// specified by ReadRegister1 and ReadRegister2 are written into output
// registers ReadData1 and ReadData2 at the falling edge of the clock.
//
// 'RegWrite' signal is high during the rising edge of the clock if the input
// data is to be written into the register file. The contents of the register
// specified by address 'WriteRegister' in the register file are modified at the
// rising edge of the clock if 'RegWrite' signal is high. The D-flip flops in
// the register file are positive-edge (rising-edge) triggered. (You have to use
// this information to generate the write-clock properly.)
//
// NOTE:-
// We will design the register file such that the contents of registers do not
// change for a pre-specified time before the falling edge of the clock arrives
// to allow for data multiplexing and setup time.
////////////////////////////////////////////////////////////////////////////////
module RegisterFile(ReadRegister1, ReadRegister2, WriteRegister, WriteData,
RegWrite, Clk, ReadData1, ReadData2);
/* Please fill in the implementation here... */
input [4:0] ReadRegister1,ReadRegister2,WriteRegister;
input [31:0] WriteData;
input RegWrite,Clk;
output reg [31:0] ReadData1,ReadData2;
//reg [31:0] Registers = new reg[32];
reg [31:0] Registers [0:31];
initial begin
Registers[0] <= 32'h00000000;
Registers[8] <= 32'h00000000;
Registers[9] <= 32'h00000000;
Registers[10] <= 32'h00000000;
Registers[11] <= 32'h00000000;
Registers[12] <= 32'h00000000;
Registers[13] <= 32'h00000000;
Registers[14] <= 32'h00000000;
Registers[15] <= 32'h00000000;
Registers[16] <= 32'h00000000;
Registers[17] <= 32'h00000000;
Registers[18] <= 32'h00000000;
Registers[19] <= 32'h00000000;
Registers[20] <= 32'h00000000;
Registers[21] <= 32'h00000000;
Registers[22] <= 32'h00000000;
Registers[23] <= 32'h00000000;
Registers[24] <= 32'h00000000;
Registers[25] <= 32'h00000000;
Registers[29] <= 32'd252; // this value should point to the top of data
memory, dont forget byte addressing
Registers[31] <= 32'b0;
end
always @(posedge Clk)
begin
if (RegWrite == 1)
begin
Registers[WriteRegister] <= WriteData;
end
end
always @(negedge Clk)
begin
ReadData1 <= Registers[ReadRegister1];
ReadData2 <= Registers[ReadRegister2];
end
endmodule
second
// Code your design here
module reg_file
#(
p=8
w=2
)
(input wire clk,wr_ena,
input wire [w-1:0],w_addr,r_addr,
input wire[B-1:0]w_data,
output wire[B-1:0]r_data);
//signal
reg[B-1:0]array_reg[2**W-1:0]
//wrrite operation
always @(posedge clk)
if(wr_en)
array_reg[w_addr]<=w_data;
//read operation
assign r_data=array_reg[r_addr];
endmodule
