HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

No.1 Vo Van Ngan Street, Thu Duc Dist., HCMC, VN

DIGITAL IC DESIGN
USING HDL

NGUYEN THANH NGHIA

9/27/2021 11
NGUYEN THANH NGHIA
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering
No.1 Vo Van Ngan Street, Thu Duc Dist., HCMC, VN

CHAPTER 6:
SYNTHESIS OF VHDL
CODE

NGUYEN THANH NGHIA

9/27/2021 22
NGUYEN THANH NGHIA
 Outline
1. Fundamental limitations of EDA software
2. Realization of VHDL operator
3. Realization of VHDL data types
4. VHDL synthesis flow
5. Timing considerations
6. Synthesis guidelines.

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 Chapter 6: Synthesis of VHDL code
 Synthesizing VHDL code is the process of
realizing the VHDL description using the
primitive logic cells from the target device’s
library.
 In Chapters 4 and 5, we discussed how to
derive a conceptual diagram from VHDL
statements.
 The conceptual diagram can be considered as
the first step in realizing the code.
 The diagram is refined further during
synthesis.
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 Chapter 6: Synthesis of VHDL code
 This chapter explains:
• the realization of VHDL operators
• data types
• provides an in-depth overview on the
synthesis process,
• discusses the timing issue involved in
synthesis.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
 Developing a large digital circuit is a complicated
process and involves many difficult tasks.
 We have to deal with
complex algorithms
and procedures and
handle a large amount
of data.

Computers are used to facilitate the process.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
 The ideal scenario is that human designers would
only need to develop a high-level behavioral
description and EDA software would perform:
• Synthesis
• Placement
• Routing
• Automatically derive the optimal circuit
implementation.
 This is unfortunately not possible.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
 The limitation comes from the theoretical
study of computational algorithms.
 For the purposes of discussion, we can separate
an EDA software tool into a core and a shell.
• The core is the algorithms that perform the
transformation or optimization,
• The shell wraps the algorithm, including data
conversion, memory and file management and
user interface.
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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
 Although the shell is important, the core
algorithms ultimately determine the quality
and efficiency of the software tool.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTABILITY

 If an algorithm exists, the problem is

computable.
 Otherwise, the problem is uncomputable.
 An example of an uncomputable problem is
the “halting problem”.
 Informally speaking, any attempt to examine
the “meaning” of a program is uncomputable.
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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY

 The computation complexity can be further

divided into:

Time complexity Space complexity

 Time complexity is  Space complexity is a
a measure of the measure of hardware
time needed to resources, such as
complete the memory, needed to
computation. complete the computation.
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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY

 Since most statements on time complexity can be

applied to space complexity as well, in the
remaining section we focus on time complexity.

Time
complexity

Space
complexity
Space
complexity

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Chapter 6: Synthesis of VHDL code

The end!

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 The computation time of an algorithm depends

on:
• The size of the input
• Type of processor
• Programming language
• Compiler
• and even personal coding style.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 Difficult to determine the exact time needed

to complete execution of an algorithm.
 To characterize an algorithm, we normally
focus on the impact of input size.
 Instead of determining the exact function for
computation time, we usually consider only
the order of this function.
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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 The order is defined as follows:

 Given two functions, f(n) and g(n), we say
that f(n) is O(g(n)) (pronounced as f(n) is big-0
of g(n) or f(n) is of order g(n)) if two
constants, n0 and c can be found to satisfy:
 f(n) < cg(n) for any n, n > n0.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 The g(n) function is normally a simple

function, such as n, nlog2n, n2, n3 or 2n.
 For example, all the following functions are
O(n2):
• 0.1n2
• n2+5n+9
• 500 n2 + 1000000
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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 Big-O notation is essentially a scaling factor

or growth rate, indicating the resources
needed as input size increase.
 Commonly encountered orders are O(1),
O(log2n), O(n), O(nlog2n), O(n2), O(n3) and
O(2n).

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 O(n) indicates the linear growth rate, in

which the required computation resources
increase in proportion to the input size.
 O(1) means that the required computation
resources are constant and do not depend on
input size.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 O(log2n) indicates the logarithmic growth

rate, which changes rather slowly. For a
problem with O(1) or O(log2n), the input size
has very little impact on the resources.
 O(n2) and O(n3) have faster growth rates and
the required computation resources become
more significant as the input size increases.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 O(2n) indicates the exponential growth rate

and the computation time increases
geometrically.
 Note that an increment of 1 in input size
doubles the computation time.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 An example using these functions is shown in Table

6.1, which lists the required computation times of
algorithms of varying computation complexity.

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 Chapter 6: Synthesis of VHDL code
1. Fundamental limitations of EDA software
COMPUTATION COMPLEXITY: BIG-O NOTATION

 For a circuit with n inputs, there are 2n possible input

combinations.

 If we assume that the testing equipment can check 1

million patterns per second, exhaustively testing a 64-
bit circuit takes about 600,000 years to complete.
64
2
6
 600.000
10 * 60 * 60 * 24 * 365

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Chapter 6: Synthesis of VHDL code

The end!

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
1 • Realization of logical operators

2 • Realization of relational operators

3 • Realization of addition operators

4 • Synthesis support for other operator

5 • Realization of an operator with constant operands

6 • An example implementation

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF LOGICAL OPERATORS

 Logical operators can be mapped directly to

logic gates, and their synthesis is straightforward.
 The AND, NAND, OR and NOR operators have
similar area and delay characteristics.
 The XOR and XNOR operators are slightly more
involved and their implementation requires more
silicon area and experiences a larger propagation
delay.
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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF LOGICAL OPERATORS

 In VHDL, a logical operation can be applied

over operands with multiple bits.

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF LOGICAL OPERATORS

 Since each bit of the input operates

independently, the area of the circuit grows
linearly with the number of input bits (i.e.,
on the order of O(n)), and the propagation
delay is a constant (i.e., on the order of O(1)).

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF RELATIONAL OPERATORS

 There are six relational operators in VHDL:

=, /=, <, <=, > and =>.
 According to their hardware implementation,
these operators can be divided into:
• The equality group, which includes the = and
/= operators,
• The greater-less group, which includes the
other four operators.
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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF RELATIONAL OPERATORS

 In the equality group, operators can easily be

implemented by a tree-like structure.
eq  (a0  b0 )(a1  b1 )
eq  (a0  b0 )(a1  b1 )(a2  b2 )
 For this implementation, the circuit area grows
linearly with the number of input bits (i.e.,
O(n)), and the delay grows at a relatively slow
O(log2n) rate.
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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF RELATIONAL OPERATORS

 In the greater-less group, the operation exhibits

a strong data dependency of input bits.
 For example, to determine the “greater than”
relationship:
• We first have to compare the most significant
bits of two operands and, if they are equal, the
next lower bits and so on.
• This leads to larger area and propagation delay.
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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF RELATIONAL OPERATORS

 Because of the circuit complexity, these

operators can be implemented in a variety of
ways, each with a different area-delay
characteristic.
 In the minimal-area implementation, both area
and delay grow linearly (i.e., O(n)) with the
number of input bits.

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF RELATIONAL OPERATORS

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF ADDITION OPERATORS

 The addition operator (+) is the most basic

arithmetic operator.
 Several other operators, including
subtraction (-), negation (- with one operand)
and absolute value (abs), can easily be
derived from the addition operator.

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF ADDITION OPERATORS

 Since the adder is the basis of other arithmetic

operations, its implementation has been studied
extensively and a wide range of circuits that
exhibit different area-delay characteristics has
been developed.
 The minimal-area circuit, sometimes known
as a serial or ripple adder, can easily be
implemented by cascading a series of 1-bit full
adders.
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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF ADDITION OPERATORS

 In this implementation, both area and delay

grow linearly (i.e., O(n)).

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
SYNTHESIS SUPPORT FOR OTHER OPERATORS

 Synthesis support for other more complicated

operators is sporadic.
 It depends on individual synthesis software, the width
of the input operands as well as the targeted device
technology.
 Some high-end synthesis software can automatically
derive multiplication operator (*) and shift operators
(sll, srl, sla, sra, rol and ror of VHDL, and shift-left, shift
right, rotate-left and rotate right of the IEEE numeric std
library).
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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
SYNTHESIS SUPPORT FOR OTHER OPERATORS

 Because of the hardware complexity, we must

be extremely careful if these operators are
used in a VHDL code.
 Synthesis software rarely supports
division-related operators (/, mod and rem) or
the exponential operator (**) or any operators
associated with floating-point data-type
operands.
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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS

 The operands of VHDL operators can

sometimes be a constant expression, which
does not depend on the value of any input
signal.
• Operator with all constant operands.
• Operator with partial constant operands.

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS

 Operator with partial constant operands.

 Most VHDL operators have two operands.
 Sometimes one of the operands is a constant,
as in count+1.
y <= rotate_right(x,3);
y <= x(2 downto 0) & x(7 downto 3);

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS

 The logic expression of this operation is.

( x3  y3 ).( x2  y2 ).( x1  y1 ).( x0  y0 )
 If one operand is a constant, say, y3y2y1y0 =
0000, the expression can be simplified to.

x3 .x2 .x1.x0

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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
AN EXAMPLE IMPLEMENTATION

 It will be helpful to have a comprehensive

table that lists the areas and delays of
synthesizable operators.
 However, because of the complexity of the
synthesis process and device technology, a
small variation in VHDL code, synthesis
algorithm, or device parameters will lead to
different results.
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 Chapter 6: Synthesis of VHDL code
2. Realization of VHDL operators
AN EXAMPLE IMPLEMENTATION
 Table 6.2 shows one synthesis result for several representative
operators of different input widths in a 0.55-micron CMOS.

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Chapter 6: Synthesis of VHDL code

The end!

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
1 • Use of the std-logic data type

2 • Use and realization of the ‘Z’ value

3 • Use of the ‘-’ value

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE OF THE STD-LOGIC DATA TYPE

 VHDL supports a rich set of data types.

 During synthesis, these data types must be
mapped into binary representations so that they
can be realized in a physical circuit.
 Recall that there are nine possible values in the
std_logic data type.
 Among them, ‘0’ and ‘1’ are interpreted as logic
0 and logic 1 and are used in regular synthesis.
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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE OF THE STD-LOGIC DATA TYPE

 ‘L’ and ‘H’ are interpreted as weak 0 and

weak 1, as in wired logic.
 Since modem device technologies no longer
use this kind of circuitry, the two values should
not be used.
 ‘U’, ‘X’ and ‘W’ are meaningful only in
modeling and simulation, and they cannot be
synthesized.
NGUYEN THANH NGHIA 48
 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE OF THE STD-LOGIC DATA TYPE

 The two remaining values, ‘Z’ and ‘-’, which

represent high impedance and “don’t care”
respectively, have some impact on synthesis.
 The ‘Z’ value means high impedance or an
open circuit.

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE AND REALIZATION OF THE ‘Z’ VALUE

It is not a value in Boolean algebra but a

special electrical property exhibited in a
physical circuit.
 Only a special kind of component, known as
a tri-state buffer, can have an output of this
value.

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE AND REALIZATION OF THE ‘Z’ VALUE

 The symbol and function table of a tri-state

buffer are shown in Figure 6.1.

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE AND REALIZATION OF THE ‘Z’ VALUE

 Only a special kind of component, known as a

tri-state buffer, can have an output of this value.
 The symbol and function table of a tri-state
buffer are shown in Figure 6.1.

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE AND REALIZATION OF THE ‘Z’ VALUE

 High impedance cannot be handled by regular

logic and can exist only in the output of a tristate
buffer.
 The VHDL description of the tri-state buffer of
Figure 6.1 is.
y <= a_in when oe = '1' else
'Z';

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE AND REALIZATION OF THE ‘Z’ VALUE

 Since a tri-state buffer is not an ordinary logic value, it

is a good idea to code it in a separate statement.
 For example, consider the following VHDL
description. with sel select
with sel select tmp <= '1' when "01" | "11",
y <= 'Z' when "00", '0' when others;
'1' when "01" | "11", y <= tmp when sel/= 00 else
'0' when others; 'Z';

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE AND REALIZATION OF THE ‘Z’ VALUE

 VHDL description of a bidirectional I/O

port.
 As a silicon device packs more circuitry
into a chip, the number of I/O signals
increases accordingly.
 A bidirectional I/O pin can be used as either
an input or an output and thus makes more
efficient use of an I/O pin.
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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE AND REALIZATION OF THE ‘Z’ VALUE

 Most FPGA and memory devices utilize

bidirectional I/O pins.
 The schematic of a simple circuit with
bidirectional I/O port, bi, is shown in Figure 6.3.

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE AND REALIZATION OF THE ‘Z’ VALUE
 The VHDL segment for the single-buffer diagram of Figure 6.3 is
entity bi_demo is
port (
bi: inout std_logic;
...
begin
sig_out <= output_expression;
...
some_signal <= expression_with_sig_in;
...
bi <= sig_out when dir = 1 else 'Z';
sig_in <= bi;
...
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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE AND REALIZATION OF THE ‘Z’ VALUE

 To accommodate the dual-buffer

configuration of Figure 6.4, we just need to
modify the last statement to reflect the change:

Sig_in <= bi when dir = 0 else 'Z';

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE OF THE ‘-’ VALUE

 Don't-care is not a valid logic value in

Boolean algebra but is used to facilitate the
design process.
 Don't-care can be used as an input value to
make a function table clear and compact.

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE OF THE ‘-’ VALUE

 Don't-care is not a valid logic value in Boolean

algebra but is used to facilitate the design process.
Input Output Input Output
req code req code
1 0 0 1 0 1 - - 1 0

1 0 1 1 0 0 1 - 0 1
0 0 1 0 0
1 1 0 1 0
0 0 0 0 0
1 1 1 1 0
0 1 0 0 1 Input Output

0 1 1 0 1 a b f
0 0 0
0 0 1 0 0
1 1 1
0 0 0 0 0
0 0 1
1 1 -

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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE OF THE ‘-’ VALUE

 When used as an output value, don't-care

indicates that the exact value is not
important.
 This happens when some of the input
combinations are not used.
 During the synthesis process, we can assign
a value that helps to reduce the circuit
complexity.
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 Chapter 6: Synthesis of VHDL code
3. Realization of VHDL data type
USE OF THE ‘-’ VALUE

 Consider the priority function of Table 6.3. We may

be tempted to code the circuit as follows:
y <= "10" when req = "1--" else
"01" when req = "01-" else
"00" when req = "001" else
"00";
 The code is syntactically correct.
 However, in a physical circuit, an input signal can
only assume a value of '0' or '1' but never '-', and thus the
req="1--" and req="01-" expressions will always be
false.
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Chapter 6: Synthesis of VHDL code

The end!

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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow

1 • Rt-level Synthesis

2 • Module generator

3 • Logic synthesis

4 • Technology mapping

5 • Effective use of synthesis Software

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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
 Synthesizing VHDL code is the process of
realizing a VHDL description using the
primitive logic cells from the target device’s
library.
 It is a complex process.

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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
 To make it manageable, we normally divide
VHDL synthesis into steps, including:
• High-level synthesis
• Gate-level synthesis (commonly known as
logic synthesis)
• RT-level synthesis
• Cell-level synthesis (commonly known as
technology mapping).
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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
 High-level synthesis transforms an
algorithm into an architecture consisting of a
data path and control path.
 Basically, the entire circuit is transformed
and optimized level by level, from an RT-level
netlist to a gate-level netlist and then to a cell-
level netlist, as shown in the left column of the
flowchart.

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Chapter 6: Synthesis of VHDL code

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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
1. RT-LEVEL SYNTHESIS

 RT-level synthesis transforms a behavioral

VHDL description into a circuit constructed
by components from a generic RT-level
library.
 The term generic implies that the
components are common to all technologies
and thus the library is not technology
dependent.
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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
1. RT-LEVEL SYNTHESIS

 The components can be classified into three

categories:
• Functional units,
• Routing units
• Storage units.

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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
1. RT-LEVEL SYNTHESIS

 Functional units are used to implement the

logic, relational and arithmetic operators
encountered in VHDL code.
 Routing units are various multiplexers used to
construct the routing structure of a VHDL
description, as discussed in Chapters 4 and 5.
 Storage units are registers and latches, which
are used only in sequential circuits and are
discussed in Chapter 8.
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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
1. RT-LEVEL SYNTHESIS

 RT-level synthesis includes the derivation

and optimization of an RT-level netlist.
 During the process, VHDL statements are
converted into corresponding structural
implementation, somewhat similar to the
derivation of conceptual diagrams discussed
in Chapters 4 and 5.

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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
1. RT-LEVEL SYNTHESIS

 The some optimization techniques, such as:

• operator sharing,
• common code elimination
• constant propagation.
 can be applied to reduce circuit complexity or
to enhance performance.
 Good design can drastically alter the RT-level
structure and help software to derive a more
effective implementation.
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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
2. MODULE GENERATOR

 Some RT-level components, such as logical

operators and multiplexers, are simple and
can be mapped directly into gate-level
implementation.
 They are known as random logic since they
show less regularity and can be optimized
later in logic synthesis.

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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
2. MODULE GENERATOR

 The other components are quite complex

and need special software, known as a module
generator, to derive the gate-level
implementation.
 These components include: adder,
subtractor, incrementor, decrementor,
comparator and, if supported, shifter and
multiplier as well.
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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
3. LOGIC SYNTHESIS

 Logic synthesis is the process of generating a

structural view using an optimal number of
generic primitive gate-level components, such as
a NOT gate, AND gate, NAND gate, OR gate and
NOR gate.
 Again, the term generic means that the
components are not tied to a particular device
technology and there is no detailed information
about the components’size or propagation delay.
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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
3. LOGIC SYNTHESIS

 At this level, a circuit can be expressed by a

Boolean function, and these generic components
are essentially the operators of Boolean algebra.
 Logic synthesis can be divided into two-level
synthesis and multilevel synthesis.
 The most commonly used two-level form is the
sum-of-products form, in which the first level of
logic corresponds to and gates and the second
level to or gates.
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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
3. LOGIC SYNTHESIS

 An example is shown in Figure 6.8(a). Other

two-level forms can easily be derived from the
sum-of- products form.

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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
3. LOGIC SYNTHESIS

 Because of the large number of fan-ins for the

and and or gates, the two-level sum-ofproducts
form can only be implemented by using a special
ASIC structure, known as programmable logic
array (PLA), and, with some modification, by
using programmable array logic (PAL)-based
CPLD devices.
 Logic synthesis generates an optimized netlist
that utilizes generic components.
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 Chapter 6: Synthesis of VHDL code
4. VHDL synthesis flow
4. TECHNOLOGY MAPPING

 Technology mapping is the process of

transforming the netlist using components
from the target device’s library.
 These components are commonly referred
to as cells, and the technology library is
normally provided by a semiconductor
vendor who manufactured (as in FPGA
technology) or will manufacture (as in ASIC
technology) the device.
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 Chapter 6: Synthesis of VHDL code
5. Timing considerations

1 • Propagation delay
2 • Synthesis With Timing Constraints
3 • Timing Hazards

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
 A digital circuit cannot respond instantaneously,
and the output is actually a function of time.
 The most important time-domain characteristic
is the propagation delay, which is the time required
for the circuit to generate a valid, stabilized
output value after an input change.
 It is one of the major design criteria for a circuit.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
1. PROPAGATION DELAY

 A digital system normally has multiple

input and output ports, and each input-output
path may exhibit a different delay.
 We consider the worst-case scenario and use
the largest input-output delay as the system’s
propagation delay.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
1. PROPAGATION DELAY

 The propagation delay reflects how fast a

system can operate and is usually considered
as the performance or the speed of the system.
 Combined with the circuit size (area), they
are the two most important design criteria of
a digital system.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
1. PROPAGATION DELAY

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
1. PROPAGATION DELAY: SYSTEM DELAY

 Once cell delays are known, we can

calculate the delay of a path by adding the
individual cell delays along the path.
 A digital system typically has many paths
between input and output ports, and their
delays are different.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
1. PROPAGATION DELAY: SYSTEM DELAY

 Since the system has to accommodate the

worst-case scenario, the system delay is
defined as the longest delay.
 The corresponding path is considered as the
longest path and is known as the critical path.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
2. SYNTHESIS WITH TIMING CONSTRAINTS

 The circuit area and system delay are two

major design criteria.
 In most applications, we cannot find a design or
an implementation that is optimized for both
criteria.
 A faster circuit normally is more complex and
needs more silicon real estate, and a smaller
circuit normally has to sacrifice some performance.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
2. SYNTHESIS WITH TIMING CONSTRAINTS

 Since a typical area-delay curve is shown in

Figure 6.18.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
2. SYNTHESIS WITH TIMING CONSTRAINTS

 An example is shown in Figure 6.19.

 optimized
for area.

System delay
is reduced

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
3. TIMING HAZARDS

 The propagation delay of a system is the

time required to generate a valid, steady-state
output value.
 Timing hazards are the fluctuations
occurring during the transient period.
 In a digital system, many paths may lead to
the same output port.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
3. TIMING HAZARDS

 Since each path’s delay is different, signals

may propagate to the output port at different
times.
 Before the output port produces a steady-
state value, it may fluctuate several times.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
3. TIMING HAZARDS: STATIC HAZARDS

 A static hazard is the condition that a

circuit’s output produces a glitch when it
should remain at a steady value.
 It is further divided into static-1 hazard
and static-0 hazard.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
3. TIMING HAZARDS

 An example:

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
3. TIMING HAZARDS

 Assume that a and c are ‘1’ and that b changes

from ‘1’ to ‘0’.

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 Chapter 6: Synthesis of VHDL code
5. Timing considerations
3. TIMING HAZARDS

 There are some techniques to eliminate

hazards caused by a single input change.
 For example, we can add a redundant product
term to eliminate the previous static hazard:
Sh  a.b  b.c  a.c

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Chapter 6: Synthesis of VHDL code

The end!

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