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N NIssued DecipheredN
Date N
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B v1.0
m m
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Security Classification Compal Secret Data
t i c . c Compal Electronics, Inc. tics.c
a
01.DA6001LH010,PCB 1O2
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2011/06/29 2011/06/29
iDate Block Diagramsemati
Title
02.DA400230020,PCB LS-C701P REV2 POWER BTN/B_435MW232L01
mIssued Deciphered Date
ematCONFIDENTIAL
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03.DA6001DM010,PCB 1EM LS-C706P REV1 ODD/B_435MW432L01
hema hem atOF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,h h m
c04.DA400232010,PCB 1EM LS-C703P REV1 HDD/B_435MW332L01 c c AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODYc
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INC. AND CONTAINS
Size Document Number c
he S he kS he DEPARTMENT e kSche
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S 05.DA4002AU010,PCB 1O2 LS-D701P REV1 TP/B_435O5Q32L01
kS
OF THE COMPETENT DIVISION OF R&D

1EM LS-C70AP REV1 SSD/B_435O1P32L11ok hELECTRONICS, Custom v1.0

EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CKL50
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06.DA6001IT010,PCB MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL INC.

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Date: Thursday, March 09, 2017 Sheet 2 of 59
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2011/06/29 Deciphered Date 2011/06/29 Title

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Rev

ot ot ot
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
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o CKL50
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

N teb N teb N teb b

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
N t e
Thursday, March 09, 2017 Sheet 3 of 59

o o o o
A B C D E

N N N N
 ot o ot o ot o ot o
5 4 3 2 1

N teb
[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS] N teb N teb N teb
o o o o
N N N N
G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5
m m m m
co co co co c
+3VL_RTC +3VL_RTC

s. o
tPCH01_Min
c
: 9m
ms
c s. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. t . t
SOC_RTCRST# SOC_RTCRST#
a s a s
+19VB m
e ti emat
i
emat
i m tic +19VB m tic
h a h h hema hema
Schem Sc em Sc em c c
+3VLP/+5VLP +3VLP/+5VLP
kS he kS he
D D

Sc
EC_ON
tPCH04_Min : 9 ms
o okSch o okSch ookSc
EC_ON
ookSc
k k
+5VALW/+3VALW/+3VALW_DSW
eboo eboo b
e oo +5VALW/+3VALW/+3VALW_DSW b
e oo
ot ot ot ot
Pull-up to DSW well if not implemented.
PM_BATLOW#
N teb N teb N teb PM_BATLOW#
N teb
o o o o
PCH_PWR_EN (SLP_SUS#) N N N N
PCH_PWR_EN (SLP_SUS#)

+3V_PRIM +3V_PRIM

+1.8V_PRIM +1.8V_PRIM
m m m m
co co co com
EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#
c
s. om s. om s. om s. o s.
gate may choose to completely ignore it

i c c i c c i c c i c c ic c
at cs. at cs. at cs. at cs. at cs.
+1.0V_MPHYPLL +1.0V_MPHYPLL

i i i m ti m ti
emat
+1.0V_PRIM_CORE
h h emat h emat hema
+1.0V_PRIM_CORE
hema
c e m tPCH34_Max : 20 ms c m c m c c
S h+1.0V_PRIM tPCH06_Min : 200 us
kS he kS he kS he +1.0V_PRIM
kS he
Sc SUSACK# ookSc ookSc ookSc ookSc
b
e oo: 10 ms b
e oo b
e oo SUSACK# b
e oo
ot tPCH02_Min ot ot ot
PCH_DPWROK N teb N teb N teb PCH_DPWROK N teb
o o o o
N N N N
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
C AC_PRESENT AC_PRESENT C

ON/OFF
om om om om ON/OFF

s.c m s .c m s .c m s .c m s.
c
ic c o o o o
PBTN_OUT#
at s. a tic before
can asserts
.cor after RSMRST# ic c
at s.
ic c PBTN_OUT#
at s.
ic c
at cs.
m tic m tic m tic m tic
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN#
i
h me a e a e a e a emat
ch :m ch m h chem
PM_SLP_S5# PM_SLP_S5#

Sch e kSche
tPCH18_Min 90 us
kSche k Schem S
S c ESPI_RST#
o o S o
o kS o Sc ESPI_RST#
okSch
eboo
k
eb o e book e book
ot ot bo ot o ot o
PM_SLP_S4# PM_SLP_S4#

N teb N te N teb N teb

SYSON
o o o SYSON
o
N N N N
+1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC

m m m om
co co co cPM_SLP_S3# c
s. om s. om s. om s. om s.
PM_SLP_S3#

ic c i c c i c c i c c SUSP# ic c
at s. at s. at s. at cs. at cs.
SUSP#

e m tic tCPU04 Min : 100 ns

e m tic e m tic emat
i
emat
i
h m a a a
ch m tCPU10 Min : 1 ms ch m chem chem
+1.0VS_VCCSTG +1.0VS_VCCSTG

Sch e kSche kSche S S

Sc
B +1.0VS_VCCIO
o ko S o
o k S okSch +1.0VS_VCCIO
okSch B

eboo eboo e book e book

ot ot ot o ot o
+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
N teb T4 = Min : 20ms Max : 30ms(EC Control) N teb N teb N teb
EC_VCCST_PG o o o EC_VCCST_PG o
N N N N
VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL
m m m om
SM_PG_CTRL

co co
tCPU18 Max : 35 us
co c+0.675VS_VTT c
c s. om c s. om c s. om c s. o m s.
ic .c
+0.675VS_VTT
i c i
tCPU09 Min : 1 msc i c i c
at cs. at cs. at cs. at cs. +VCC_SA a t s
emat
+VCC_SA
i
emat
i
emat
i
emat
i m tic
h h h chem hema
Schem S c em Sc em S c
kS he
+VCC_CORE +VCC_CORE
k h okSch okSch
Sc +VCC_GT ookSc o k o k
+VCC_GT ookSc
t eboo eboo eboo b
e oo
o ot ot ot
N teb N teb N teb N teb
VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
o o o o
PCH_PWROK
N N N PCH_PWROK
N
H_CPUPWRGD H_CPUPWRGD

SYS_PWROK SYS_PWROK
m m m om
A A

co co co cSUS_STAT# c
s. om s. om s. om s. om s.
SUS_STAT#

i c
t s. c i c c i c c i c c ic c
SOC_PLTRST#a at cs. at cs. at cs. SOC_PLTRST# at cs.
ic i i m ti m ti
h emat h emat h emat hema hema
c
S he m c m c m c c
kS he kS he ok ch
S e kS he
Sc ookSc ookSc CompaloSecret Data S
k Compal Electronics, Inc. ookSc
b b b b
Security Classification

e oo e o e oo e oo Title

ot ot bo ot ot
Issued Date Deciphered Date
HW Reserve
N teb N te N teb N teb
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom v1.0
CKL50
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

o o o o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

N N N N
Date: Thursday, March 09, 2017 Sheet 4 of 59
5 4 3 2 1
 ot o ot o ot o ot o
A B C D E

N teb N teb N teb N teb

o o o o
N N UC1A NSKL-U N
Rev_0.53
21 PCH_DPB_N2 E55 C47
DDI1_TXN[0] EDP_TXN[0] EDP_CPU_LANE_N0_C 20
21 PCH_DPB_P2 F55 C46
DDI1_TXP[0] EDP_TXP[0] EDP_CPU_LANE_P0_C 20
21 PCH_DPB_N1 E58 D46 <eDP>
m m <HDMI> m F58 DDI1_TXN[1] EDP_TXN[1] C45
om
EDP_CPU_LANE_N1_C 20

co co co
21 PCH_DPB_P1 DDI1_TXP[1] EDP_TXP[1] EDP_CPU_LANE_P1_C 20
.c m c
F53 A45
s. om s. om s. om s.
SOC_DP1_CTRL_DATA(Internal Pull Down): 21 PCH_DPB_N0
s
G53 DDI1_TXN[2] EDP_TXN[2] B45
c c c ic .co ic .c
21 PCH_DPB_P0
i c i c i c
DDI1_TXP[2] EDP_TXP[2]

at cs. at cs. at cs. t t

21 PCH_DPB_N3 F56 A47
a cs s
DDI1_TXN[3] EDP_TXN[3]
Display Port B Detected G56 B47
a
m tic
21 PCH_DPB_P3
i i i DDI1_TXP[3] EDP_TXP[3]
i
h emat h emat
0 = Port B is not detected. 22 PCH_DPC_N0
hemat
C50
DDI2_TXN[0] hemF45
EDP_AUXN
m E45 t
a EDP_CPU_AUX#_C 20 hema
1 c m Schem c m C52 c c
DDI EDP
<eDP to CRT> D50
S he kSche kS e kS he
22 PCH_DPC_P0 DDI2_TXP[0] EDP_AUXP EDP_CPU_AUX_C 20 1

Bk ch
22 PCH_DPC_N1
D52 DDI2_TXN[1]
Sc c ookSc
1 = Porto 22 o
ookS
is detected. B52
S S
PCH_DPC_P1
o k o k
A50 DDI2_TXP[1] EDP_DISP_UTIL TP@ T228

eb o eboo B50 DDI2_TXN[2] b

e oo G50
e b o
ot bo ot ot ot22 bo
D51 DDI2_TXP[2] DDI1_AUXN F50

N teb N teb
C51 DDI2_TXN[3] DDI1_AUXP E48
N teSOC_DP2_CTRL_DATA(Internal N t22 e
Pull Down): DDI2_AUX_DN
DDI2_TXP[3] DDI2_AUXN F48 DDI2_AUX_DP DDI2_AUX_DN
o o o DDI2_AUXP G46 o
DDI2_AUX_DP
N Display Port C Detected N N
DISPLAY SIDEBANDS DDI3_AUXN F46 N
PCH_DDPB_CLK L13 DDI3_AUXP
21 PCH_DDPB_CLK PCH_DDPB_DAT GPP_E18/DDPB_CTRLCLK PCH_DDPB_HPD From HDMI
0 = Port C is not detected. HDMI DDC (Port B)
L12 L9 PCH_DDPB_HPD 21
21 PCH_DDPB_DAT GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 DDI2_HPD From eDP to CRT
L7 DDI2_HPD 22
RC200 1 @ 2 2.2K_0402_5% N7 GPP_E14/DDPC_HPD1 L6 NMI_DBG#_CPU
m m m N8 GPP_E20/DDPC_CTRLCLK
m GPP_E15/DDPD_HPD2 N9 EC_SCI#
NMI_DBG#_CPU 10,26

co co co co
1 = Port C is detected. +3VS RC199 1 2 2.2K_0402_5%
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 EC_SCI# 10,26
c
s. om s. om s. om s. om s.
CRT@ L10 EDP_HPD From eDP
GPP_E17/EDP_HPD EDP_HPD 20
N11
i c c i c c i c c
GPP_E22/DDPD_CTRLCLK
i c c ic c
at cs. at cs. at s. EDP_BKLTEN R11 t
s. at cs.
N12 R12 ENBKL
ENBKL 26
GPP_E23/DDPD_CTRLDATA
a ENVDD_CPU
i i ic ic BKL_PWM_CPU 20
m ti
emat emat emat EDP_RCOMP emat
EDP_COMP E52 1 OF 20 EDP_BKLTCTL U13

hema
EDP_VDDEN ENVDD_CPU 20

c h c h h h
S he m
kS he
m Sc em SKL-U_BGA1356
Sc em kS he
c
Sc ookSc ookSch o okSch ookSc
b k k
e oo eboo eboo te oo
b
+1.0V_VCCST

ot ot ot
+1.0VS_VCCIO
o
RC123 1 @ 2 100K_0402_5% ENVDD_CPU
N teb N teb N teb N teb
o o o o

1
RC2
1 2 H_THERMTRIP#
1K_0402_5% N RC3 N UC1D SKL-U N RC124 1 N 2 100K_0402_5% ENBKL
Rev_0.53
1K_0402_5%
D63
2 T248 TP@ H_PECI CATERR# 2
26 H_PECI A54

2
1 2 H_PROCHOT#_R C65 PECI
COMPENSATION PU FOR eDPom m om om
26 PROCHOT# PROCHOT# JTAG
H_THERMTRIP#
oRC4 499_0402_1% C63
.c m .c m .c m .c m c
THERMTRIP#
s.
SOC_OCC# A65 B61 CPU_XDP_TCK0
s s s TP@ T260cs
+1.0VS_VCCIO T25 TP@ SKTOCC# PROC_TCK D60 SOC_XDP_TDI TP@ T259
ic c o ic c o ic c o o ic c
ti s.c
CPU MISC PROC_TDI A61

1
at s. 2 EDP_COMP at s. DS11 at cs. at cs.
XDP_BPM#0 C55 SOC_XDP_TDO
aT262
T270 TP@ XDP_BPM#1 D55 BPM#[0] PROC_TDO C60 SOC_XDP_TMS TP@ T261
mRC1t1ic m tic i ic i
T271 TP@
e e CK0402101V05_0402-2 T250 TP@
e mBPM#[1]
B54
t
PROC_TMS B59 SOC_XDP_TRST#
e mTP@
TP@ t emat
h a a a
BPM#[2] PROC_TRST#
a T263
ch m ch mBPM#[3] chemTP@ T264 chem
24.9_0402_1% T249 TP@ C56

Schem
ESD@ PCH_JTAG_TCK1
CAD note: B56
kSche kSche A6 S S
PCH_JTAG_TCK D59
k ch okSch
Trace width=20 mils,Spacing=25mil,Max length=100mils SCV00001K00 SOC_GPIOE3 SOC_XDP_TDI
c
T30 TP@
o o PCH_JTAG_TDO C59 oSOC_XDP_TMS
2

A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 SOC_XDP_TDO TP@ T265

S S S S
book bo o SOC_XDP_TRST# book
BA5 GPP_E7/CPU_GP1 TP@ T266
o kSOC_GPIOB4 PCH_JTAG_TMSb C61 ok
e e AY5 GPP_B3/CPU_GP2
e e
TP@ T267

ot o ot o t o ot o
T40 TP@ GPP_B4/CPU_GP3 PCH_TRST# TP@ T268
oJTAGX CPU_XDP_TCK0
N teb eb CPU_POPIRCOMP AU16 N teb N teb
A59
TP@ T269
RC5 2
N 11 t49.9_0402_1%
49.9_0402_1% AT16
PROC_POPIRCOMP
o RC6 2
o1 49.9_0402_1%PCH_OPIRCOMP
EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP o o
N RC7 2
RC8 2
N 1 49.9_0402_1%EOPIO_RCOMP H65 OPCE_RCOMP
N N
OPC_RCOMP
4 OF 20
SKL-U_BGA1356
m m m m
co co co co c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at s. at s. at s. at s. at cs.
e m tic e m tic e m tic e m tic emat
i
chem
a
ch m
a
ch m
a
ch m
a XDP CONN chem
S h kSche kSche kSche S
okSch
Sc o o o
3 3
S S S
bo k o k
eboo
o k
eboo book
+1.0VS_VCCIO o
te oo ot ot ot
e o
N teb N teb N teb N teb
o o o o
N
RC11 2 @ 1 51_0402_5% SOC_XDP_TMS N N N
RC13 2 @ 1 51_0402_5% SOC_XDP_TDI

RC15 2 1 51 +-1% 0402 SOC_XDP_TDO SD000008H80

m m m m
co co co co c
s. om s. om s. om s. om s.
RC364 2 @ 1 51_0402_5% CPU_XDP_TCK0

t i c c i c c i c c i c c ic .c
a s . at cs. at cs. at cs. a t s
m tic emat
i
emat
i
emat
i m tic
c hema +1.0V_PRIM
h h h hema
S he Schem Sc em Sc em c
kS he
S c RC14 2 @ okSc
1 51_0402_5%
o
XDP_PREQ#
XDP_PREQ# 11
o okSch o okSch ookSc
eb ok eboo
k
eboo
k b
e oo
RC31o t 2 o ot ot ot
N te
1 @
b 1K_0402_5% XDP_ITP_PMODE XDP_ITP_PMODE 16
N teb N teb N teb
o o o o
N N N N

4 1 51_0402_1% SOC_XDP_TRST# 4
m m m m
RC365 2 @

co co co co c
cs. om c s. om c s. om c s. om s.
ic c
1 51_0402_1% CPU_XDP_TCK0
i i i i
RC35 2 SD000008H80
c c c c
at cs. 1 51_0402_5% PCH_JTAG_TCK1 a
t s. at cs. at cs. at cs.
m tic
RC37 2 @
i i m ti m ti
h emat RC366 1 @ 2 0_0402_5% CFG3 he a CFG3 16 emat
hClassification hema hema
c
S he m Sc em c
Security m Compal Secret Data c Compal Electronics, c
Inc.
okSch he
kScIssued 2014/05/19 Deciphered Date k he
S 2015/12/31 Title kS he
Sc ookS ook Sc ookSc
Date
o k SKL-U(1/12)DDI,MSIC,XDP,EDP
eboo b
e oo b
eCUSTODYo
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
e b o
ot ot otTHIS SHEEToNOR THE INFORMATION IT CONTAINS ot bo
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

N teb N teb N teb OF COMPAL ELECTRONICS, INC.

Custom v1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT CKL50
N t e
o o o Date: Thursday, Marcho
09, 2017 Sheet 5 of 59
A
N B
N C
N D
N E
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o o o o
N N N N

Interleaved Memory
co
m
co
m
co
m
co
m
Interleaved Memory c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. a t s . a t s . a t s . a t s
emat
i m tic m tic m tic m tic
h hem a
<Cocoa_1020> hema hema hema
Schem
D c
kS he PDG#543016, ODT: CPU side k
c
S he c
S he c
kS he
D

Sc ookSc ookSc
no connect, DRAM side connect o took
VDDQ(Memory
Sc
down); FET+R(SO-DIMM) ookSc
b o b b k b
e e oo e o e oo
ot bo ot ot bo ot
N teb N teb
SKL-U
N e e
N tUC1C
ot
UC1B SKL-U
Rev_0.53
o o Rev_0.53
o
17 DDR_A_D[0..15] DDR_A_D0 AL71
N DDR0_CKN[0] AT53 DDR_A_CLK0N
AU53 DDR_A_CLK#0 DDR_A_CLK#0 17 18 DDR_B_D[0..15] DDR_B_D0
NAF65 N
AN45 DDR_B_CLK#0
DDR0_DQ[0] DDR0_CKP[0] DDR_A_CLK0 17 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDR_B_CLK#0 18
DDR_A_D1 AL68 AU55 DDR_A_CLK#1 DDR_B_D1 AF64 AN46 DDR_B_CLK#1
DDR0_DQ[1] DDR0_CKN[1] DDR_A_CLK#1 17 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK#1 18
DDR_A_D2 AN68 AT55 DDR_A_CLK1 DDR_B_D2 AK65 AP45 DDR_B_CLK0
DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 17 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDR_B_CLK0 18
DDR_A_D3 AN69 DDR_B_D3 AK64 AP46 DDR_B_CLK1
DDR0_DQ[3] DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 18
DDR_A_D4 AL70 BA56 DDR_A_CKE0 DDR_B_D4 AF66
m m m mAN56 DDR_B_CKE0
DDR0_DQ[4] DDR0_CKE[0] DDR_A_CKE0 17 DDR1_DQ[4]/DDR0_DQ[20]
DDR_A_D5 AL69 BB56 DDR_A_CKE1 DDR_B_D5 AF67
co co co comAP55
DDR0_DQ[5] DDR_A_CKE1 17
DDR0_CKE[1] DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE0 18
c
DDR_A_D6 AN70 AW56 DDR_B_D6 AK67 DDR_B_CKE1

s. om s. om s. om .DDR1_CKE[1] s.
DDR0_DQ[6] DDR0_CKE[2] TP@ T14 DDR1_DQ[6]/DDR0_DQ[22] DDR_B_CKE1 18
s
DDR_A_D7 AN71 AY56 DDR_B_D7 AK66 AN55
c c c c o
tics.c
DDR0_DQ[7] DDR0_CKE[3] TP@ T15 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] TP@ T17
i i i i
DDR_A_D8 DDR_B_D8
c c c c
AR70 AF70 AP53

at cs. at DDR0_CS#[0]. AU43 DDR_A_CS#1 at cs. at cs.DDR1_CS#[0] BB42 DDR_B_CS#0

DDR_A_D9 DDR0_DQ[8] DDR_A_CS#0 DDR_B_D9 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] TP@ T18

cs a
AR68 AU45 DDR_A_CS#0 17 AF68

ic
DDR_A_D10 DDR0_DQ[9] DDR_B_D10 DDR1_DQ[9]/DDR0_DQ[25]
i iDDR0_CS#[1] i m ti
AU71 AH71

emat emat DDR0_ODT[0] emat emat

DDR_A_D11 DDR0_DQ[10] DDR_A_CS#1 17 DDR1_DQ[10]/DDR0_DQ[26] DDR_B_CS#0 18
AT45 DDR_A_ODT0 DDR_B_D11

hema
AU68 DDR_A_ODT0 17 AH68 AY42 DDR_B_CS#1 DDR_B_CS#1 18
DDR0_DQ[11]
h h h DDR_B_ODT0 18 h
DDR_A_D12 AR71 AT43 DDR_A_ODT1 DDR_B_D12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0
c m c m c m c DDR_B_ODT1 c m
DDR_A_D13 DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 17 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT1
AR69 DDR_B_D13
S he he e kS heDDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AY48 DDR_B_MA5 S he
AF69
kS DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA5 17 S
DDR_A_D14 DDR0_DQ[13] DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] 18
k ch 18 DDR_B_D[16..31] okSc
AU70 BA51 DDR_A_MA5 DDR_B_D14 AH70

Sc17 DDR_A_D[16..31] ookScDDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] ook ookSc

DDR_A_D15 AU69 DDR0_DQ[14] BB54 DDR_A_MA9 DDR_B_D15 DDR1_DQ[14]/DDR0_DQ[30]
AH69
17 S oDDR_B_MA9
DDR_A_D16 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6 DDR_A_MA9 17 DDR1_DQ[15]/DDR0_DQ[31] DDR_B_MA5 18
DDR_B_D16 AP50 DDR_B_MA9
k
BB65 AT66
b
DDR0_DQ[16]/DDR0_DQ[32]
e oo b
DDR_A_MA6
b DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR1_DQ[16]/DDR0_DQ[48]
b 18

oo 17 e oo o
DDR_A_D17 AY52 DDR_A_MA8 DDR_B_D17
eDDR_A_MA7 e oDDR_B_MA8
AW65 DDR_A_MA8 17 AU66 DDR_B_MA6 18

ot ot b t DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7 t

DDR_A_D18 DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_DQ[17]/DDR0_DQ[33] AW52 DDR_A_MA7 DDR_B_D18 DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_DQ[17]/DDR0_DQ[49]
AW63 AP65 BB48 DDR_B_MA8
o o
N teb b b
DDR_A_D19 DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0
DDR0_DQ[18]/DDR0_DQ[34] 17 DDR_B_D19 DDR1_DQ[18]/DDR0_DQ[50] 18
AY63 AN65
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11N
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_MA12
e DDR_A_BG0 N te N e DDR_B_MA7 18

ot DDR_A_MA11 17 DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12 t

DDR_A_D20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR_B_D20 DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_DQ[19]/DDR0_DQ[51] AP52 DDR_B_BG0
DDR_A_MA12 17 AN66 DDR_B_BG0 18
DDR_A_D21 AY65 o
DDR0_DQ[20]/DDR0_DQ[36] DDR_B_D21
o AP66 DDR1_DQ[20]/DDR0_DQ[52]
o
N DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_BG1N N N
DDR_A_D22 DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_ACT#
DDR0_DQ[21]/DDR0_DQ[37] DDR_B_D22 DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11
DDR1_DQ[21]/DDR0_DQ[53] DDR_B_MA12 188/10 Modify for DDR4
BA63 DDR_A_ACT# 17 AT65 DDR_B_MA11 18
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR_B_D23 DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_ACT#
DDR1_DQ[22]/DDR0_DQ[54]
DDR_A_BG1 17 AU65 DDR_B_ACT# 18
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_B_D24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
BA61 AT61 AN52 DDR_B_BG1 DDR_B_BG1 18 8/10 Modify for DDR4
DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13 DDR_B_D25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR_A_MA13 17 AU61
C DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15_CAS# DDR_B_D26 DDR1_DQ[25]/DDR0_DQ[57] DDR_B_MA13 C
DDR_A_MA15_CAS# 17 AP60 BA43 DDR_B_MA13 18
DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14_WE# DDR_B_D27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_B_MA15_CAS#
DDR_A_MA14_WE# 17 AN60 AY43 DDR_B_MA15_CAS# 18

om om om om
DDR_A_D28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16_RAS# DDR_B_D28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] 9/8 Modify
DDR_B_MA14_WE#
DDR_A_MA16_RAS# 17 AN61 AY44
DDR_B_MA14_WE# 18
DDR_A_D29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_B_D29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
.c m .c m .c m .c m c
AY61 AU52 DDR_A_BA0 AP61 AW44 DDR_B_MA16_RAS#

s.
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_BA0 17 DDR1_DQ[29]/DDR0_DQ[61] DDR_B_MA16_RAS# 18
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
s s s s
BA59 AY51 DDR_A_MA2 DDR_B_D30 AT60 BB44 DDR_B_BA0
o o o o
DDR_A_MA2 17 DDR_B_BA0 18
ic c ic c ic c ic c DDR_B_MA2 18 8/10 Modify for DDR4 ic
DDR_A_D31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BA1 DDR_B_D31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_MA2
t s.c
AY59 AU60 AY47

at s. at s. at s. at cs.
17 DDR_A_D[32..47] DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] 18 DDR_B_D[32..47] DDR_A_BA1 17 DDR_B_D32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
AT50 DDR_A_MA10 DDR_B_BA1
a
AY39 DDR_A_MA10 17 AU40 DDR_B_BA1 18 BA44
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
m tic m tic m tic m tic
DDR_A_D33 DDR0_DQ[32]/DDR1_DQ[0] DDR_A_MA1 DDR_B_D33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_MA10
i
AW39 BB50 AT40 AW46

emat
DDR_A_D34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA1 17 DDR_B_D34 DDR1_DQ[33]/DDR1_DQ[17] DDR_B_MA10 18
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR_A_MA0 DDR_B_MA1
e e e DDR_B_MA0 18 he
AY37 AY50 AT37 AY46
h a a
DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
a DDR_A_MA0 17 DDR_B_MA1 18
a
ch m ch m chem
DDR_A_D35 AW37 BA50 DDR_A_MA3 DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
DDR_A_MA3 17

Schem DDR_B_MA3 c m
DDR_A_D36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4 DDR_B_D36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA3

kSche k17Sche e
AR40 BB46
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 17
DDR_B_D37 AP40
k S
DDR1_DQ[36]/DDR1_DQ[20]
h k S
DDR_B_MA4 18
18
DDR1_MA[3]
hBA47 DDR_B_MA4
c o o ookSc o Sc18
DDR_A_D38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0 DDR_B_D38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
DDR_A_DQS#0 AP37
S o kS 17S
book17 oDDR_B_DQS#0
DDR_A_D39 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D39 DDR1_DQ[38]/DDR1_DQ[22]
BB37 AH66 DDR_B_DQS#0
ok
AR37

eb o eboo eboDDR_B_DQS0
DDR_A_D40 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_A_DQS0
DDR_B_D40 DDR1_DQ[39]/DDR1_DQ[23]
DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS0
eDDR_A_DQS#1
AY35 AT33 18

ot bo ot b o t DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_B_DQS1 t

DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D41 DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_B_DQS#1
AU33
o o
DDR_A_DQS1 17 DDR_B_DQS#1 18

N teb DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2 eb

DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#2 DDR_B_D42 DDR1_DQ[41]/DDR1_DQ[25]
N te N te DDR_A_DQS2 17
AU30
N
DDR_A_DQS#2 17 DDR_B_DQS1 18
DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_B_DQS2 t
DDR_A_D43 AW33 DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 DDR_B_D43 DDR1_DQ[42]/DDR1_DQ[26]
AT30 DDR_B_DQS#2 18
DDR_A_D44 BB35 o
DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#3
o DDR_A_DQS#3 17
DDR_B_D44
o AR33 DDR1_DQ[43]/DDR1_DQ[27]
o DDR_B_DQS2 18
DDR_A_D45
DDR_A_D46
BA35
BA33
NDDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQ[45]/DDR1_DQ[13] N
DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3
DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS#4 DDR_A_DQS3 17
DDR_A_DQS#4 17
N
DDR_B_D45
DDR_B_D46
AP33
AR30
DDR1_DQ[44]/DDR1_DQ[28]
DDR1_DQ[45]/DDR1_DQ[29] N
DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#3
DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_B_DQS3
DDR_B_DQS#3 18
DDR_B_DQS3 18
DDR_A_D47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4 DDR_B_D47 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] DDR_B_DQS#4
17 DDR_A_D[48..63] DDR_A_DQS4 17 18 DDR_B_D[48..63] AP30 AT38 DDR_B_DQS#4 18
DDR_A_D48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 DDR_B_D48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS4
DDR_A_DQS#5 17 AU27 AR38 DDR_B_DQS4 18
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5 DDR_B_D49 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS#5
DDR_A_DQS5 17 AT27 AT32 DDR_B_DQS#5 18
DDR_A_D50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 DDR_B_D50 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS5
DDR_A_DQS#6 17 AT25 AR32 DDR_B_DQS5 18
m DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34]
m
DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6
m DDR_B_D51 AU25 DDR1_DQ[50]
m DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6

co co co co
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_A_DQS#7 DDR_A_DQS6 17 DDR_B_D52 DDR_B_DQS#6 18
DDR1_DQ[51] DDR1_DQSN[6] DDR_B_DQS6
BB31 AY26 AP27
c
s. om s. om s. om s. om s.
DDR_A_D53 DDR_A_DQS#7 17 AR27 DDR_B_DQS6 18
BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7 DDR_B_D53 DDR1_DQ[52] DDR1_DQSP[6] DDR_B_DQS#7
DDR_A_DQS7 17 AN27 AR22 DDR_B_DQS#7 18
c c c c tics.c
DDR_A_D54 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[7] DDR_B_DQS7
i c
BA29
i c AW50 DDR_A_ALERT# i c AN25
i .c
AR21 DDR_B_DQS7 18
at s. atDDR0_ALERT#
s. AT52 DDR_A_PAR at s. at csDDR1_ALERT#
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR_B_D55 DDR1_DQ[54] DDR1_DQSP[7]
a
DDR_A_D56 DDR_A_ALERT# 17 AP25

m tic m tic m tic ic

DDR0_DQ[55]/DDR1_DQ[39] DDR_B_D56 DDR1_DQ[55] AN43 DDR_B_ALERT#
i
AY27 AT22
emat emat
DDR_A_D57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PAR 17 DDR_B_D57 DDR_B_ALERT# 18
DDR1_DQ[56] AP43 DDR_B_PAR
e e e
AW27 AU22
a a a
DDR_A_D58 DDR0_DQ[57]/DDR1_DQ[41] DDR_DRAMRST# DDR_B_PAR 18
h ch m DDR0_VREF_DQ ch m chem chem
AY25 AY67 +0.6V_VREFCA DDR_B_D58 DDR1_DQ[57] DDR1_PAR
+0.6V_VREFCA AU21 AT13

Schem
DDR_A_D59 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68 DDR_B_D59 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP0
AW25

kSche kSche S S
DDR_A_D60 AT21 RC38 1 2 121_0402_1%
DDR0_DQ[59]/DDR1_DQ[43] BA67 +0.6V_B_VREFDQ DDR_B_D60 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1

okSch o2 k h
BB27 DDR CH - A
+0.6V_B_VREFDQ AN22 RC39 1 2 80.6_0402_1%

Sc Sc
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ
o o
B
BA27 DDR_B_D61 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP2
DDR CH - B
B
AP22 RC40 1 100_0402_1%
o k S o k S
book book
DDR_A_D62
BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_PG_CTRL DDR_B_D62
AP21 DDR1_DQ[61] DDR_RCOMP[2]

eb o eb o
DDR_A_D63 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 DDR1_DQ[62]
e e
BB25 AN21

ot bo ot bo ot bo ot o
DDR0_DQ[63]/DDR1_DQ[47] 2 OF 20 DDR1_DQ[63]
3 OF 20

N e N e e
N tSKL-U_BGA1356 N teb
ot ot o o
SKL-U_BGA1356

N +1.2V_VDDQ N N N
For VTT power control
+1.2V_VDDQ
+3VS
1
1

RC904 0.1U_0201_10V6K 2 1 CC57

m100K_0402_5% m m m
1

RC905 @ 100K_0402_5%

co @
co UC7
co RC394
co c
c s. om cs. om 1 5
c s. om 100K_0402_5%
c s. om s.
ic .c
2

NC VCC
i c i c i c i c
at cs. at cs. at s. 49 at cs. t
2

DDR_PG_CTRL
a s
2
1

ic m tic
A
i i i
4

emat emat emat emat

Y SM_PG_CTRL +1.2V_VDDQ
2

RC906

hema
3
GND
h 100K_0402_5% @
h h h @ESD@

Schem Sc SM_PG_CTRL
em Sc em c m c
SN74AUP1G07DCKR_SC70-5 DDR_PG_CTRL

kSche CC70 S e
1 2

okS1ch okSch k ch
@ SA00007UR00 100P_0402_50V8J
2

Sc oRC32 ooRequest
DDR_PG_CTRL

1
3
o k o k o k S From ESD Team
k S
eboo eboo eb o470_0402_5% b
e oo
ot ot ot bo ot
N tebUC9 N teb e
NDDR_DRAMRST# N teb
ot

2
SB000008E10
o MMBT3904WH NPN SOT323-3
o 1 @ 2
DDR_DRAMRST#_R
DDR_DRAMRST#_R 17,18 o
N TR DRC5115E0L NPN SOT323-3
SB00000QJ00,S
N N RC33 0_0402_5% N

A A

m m m m
co co co co c
cs. om c s. om c s. om c s. om s.
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at cs. at cs. at cs. at cs. at cs.
i i m ti m ti m ti
h emat h emat hemSecurity
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kS he kS he kS e 2015/12/31 kS Inc. he
Classification Compal Secret Data Compal Electronics,
Date h
Sc ookSc ookSc ookSc INC. AND CONTAINS CONFIDENTIAL ookSc
Issued Date 2014/05/19 Deciphered Title

b b b SKL-U(2/12)DDRIII
b
e oo e oo e FROM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
o
OF COMPAL ELECTRONICS,
e o
ot ot ot INC. NEITHER
oTHIS ot bo
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

N teb N teb MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORb
Custom v1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, SHEET NOR THE INFORMATION IT CONTAINS
N te WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CKL50
N e
5 o 4 o 3 o 2
Date:
o t
Thursday, March 09, 2017 Sheet 6 of 59
1
N N N N
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N teb N teb N teb N te

o o o SML0ALERT# (Internal Pull Down): o
N SKL-U
N N eSPI or LPC N
UC1E 0 = LPC is selected for EC --> For KB9022/9032 Use
Rev_0.53
SPI - FLASH 1 = eSPI is selected for EC --> For KB9032 Only.
SMBUS, SMLINK
PCH_SPI_CLK AV2
m PCH_SPI_SO m AW3 SPI0_CLK SMBCLK mR7 SMB m
SML0ALERT#
co co co co
SPI0_MISO GPP_C0/SMBCLK
PCH_SPI_SI SMBDATA
c
s. om
AV3
s. om s. om s. om s.
R8
PCH_SPI_SIO2 AW2 SPI0_MOSI GPP_C1/SMBDATA
SMBALERT# R10 (Link to XDP, DDR, TP)
i c ic SPI0_IO2
ic
GPP_C2/SMBALERT# TP@ T239
i c ic .c

1
c c
PCH_SPI_SIO3
c c
at cs. at cs. R9 t SML0CLK
. t . t
AU4

cs s s
SPI0_IO3
PCH_SPI_CS0# AU3
a SML0DATA a RC218
a
i i mW1 tiSML0ALERT# m tic m tic
SPI0_CS0# GPP_C3/SML0CLK W2
emat emat
AU2 1K_0402_1%
hema hema hema
AU1 SPI0_CS1# GPP_C4/SML0DATA
h h SPI0_CS2# GPP_C5/SML0ALERT#
D c
S he
m Sc em SPI - TOUCH S c e S hec c
kSche

2
SML1CLK D

okSch M2 ch
kGPP_C7/SML1DATA
W3
ok
SML1
Sc c LAN, Thermal Sensor)
GPP_C6/SML1CLK
ookS ook+3V_PRIM
V3 SML1DATA
toS S
o k
AM7 GPP_B23 1 @ 2 SML1ALERT# o(Link
k
EC,DGPU,

eboo M3 GPP_D1/SPI1_CLK b b b
GPP_B23/SML1ALERT#/PCHHOT#
e oo RC902
e oo RC903 te oo
ot ot ot
J4 GPP_D2/SPI1_MISO
o
0_0201_5%
N teb V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2 N teb TP@ T234 N teb SML1ALERT# 2
N@ t1 eb
o o o o
150K_0402_1%
M1 GPP_D22/SPI1_IO3
N GPP_D0/SPI1_CS# N
LPC
AY13 LPC_AD0 N LPC_AD0 26,28
SML0ALERT# RC3602N@ 1 10K_0402_5%
GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD1 +3VS
C LINK GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 26,28
BB13
GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 26,28
G3 AY12 SMBALERT# 8 1
CL_CLK GPP_A4/LAD3/ESPI_IO3 LPC_FRAME# LPC_AD3 26,28
G2 BA12 7 2
m m CL_DATA GPP_A5/LFRAME#/ESPI_CS#
m SUS_STAT# LPC_FRAME# 26,28
m EC_KBRST#
co
G1
co com co
BA11 TP@ T242 6 3
c
CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET#
s. om s. om s. o s. om s.
5 4

i c c i c c c
AW9 iCLK_PCI0c i c c ic c
at cs. at cs. GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9t CLK_PCI1
. RC53 1 ECt s. at cs.
EC_KBRST# AW13 RC387 1 2 22_0402_5% RPC19 10K_0804_8P4R_5%
26 EC_KBRST#
cs
CLK_PCI_LPC 26
GPP_A10/CLKOUT_LPC1 a
GPP_A0/RCIN# TPM@2 22_0402_5% To a
i ti AW11 iPM_CLKRUN# m tic m ti
CLK_PCI_TPM 28
emat
AY11m
emat
To TPM SERIRQ

h
26,28 SERIRQ
h e GPP_A6/SERIRQ
a GPP_A8/CLKRUN#
h
PM_CLKRUN# 26
e a hema
ch m
5 OF 20
c
S he m LPC Mode c m Sc em c
kS he SKL-U_BGA1356 okSch kSche kS he
Sc ookSc o k
o
o kS ookSc
b
e oo b eb o b
ot te oo
o+3VS ot bo ot
e oo
N teb N teb N te N teb
+3VS

o o o o
to SPI ROM UC2
NSource From
N N N

2
2
RPH11
C PCH_SPI_CS0#_R 1 8 EC_SPI_CS0# RC216 RC215 C
PCH_SPI_CS0#_R PCH_SPI_CS0# EC_SPI_CS0# 26
2 7 10K_0402_5% 10K_0402_5%
om 6 om om om
PCH_SPI_SO_R EC_SPI_SO
3
EC_SPI_SO 26
.c m 5 PCH_SPI_SO .c m .c m .c m c

2
s.
PCH_SPI_SO_R 4 QC1A
s s s s

1
1
o
ic c 15_0804_8P4R_5% o
ic SMBCLK
c c c
i17,18,22 o ic c o ic c
at cs. at s. at s. at cs. at cs.
6 1
PCH_SMBCLK

e ti
m PCH_SPI_HOLD# RPH12
e m tic 2N7002DWH_SOT363-6
e m tic emat
i
emat
i
h a a a +3V_PRIM
ch m ch m chem chem
1 8 PCH_SPI_SIO3 SB00000I700

Schem PCH_SPI_SI_R

5
PCH_SPI_SI_R 2 7 PCH_SPI_SI

c
3
4
6
5
EC_SPI_SI
kSc26he
EC_SPI_SI
o SMBDATA
QC1B
3 4 okSchePCH_SMBDATA 17,18,22 S
okSch SML0CLK RC49 1 2 499_0402_1%
S
okSch
S o kS o kS
15_0804_8P4R_5%
eb o 2N7002DWH_SOT363-6b
e oo e book SML0DATA RC50 1 2 499_0402_1%
e book
ot bo SB00000I700 t
o +3VS b ot o ot o
PCH_SPI_WP# 2 1
N te
PCH_SPI_SIO2
N te N teb N teb
RC388 15_0402_5%
o o o RPC7
o
SPI ROM ( 8MByte Only)
N +3V_SPI N N SML1CLK
SML1DATA
1
2
8
7
N
CC8 SMBDATA 3 6
UC2 1 2 0.1U_0402_16V7K SMBCLK 4 5
PCH_SPI_CS0#_R 1 8 <DB> Un-pop QC2 for new 0x90 thermal sensor
/CS VCC
2

PCH_SPI_SO_R 2 7 PCH_SPI_HOLD# 1K_0804_8P4R_5%

m DO(IO1) /HOLD(IO3) m @ m m
co co co co
PCH_SPI_WP# 3 6 PCH_SPI_CLK_R
/WP(IO2) CLK
c
s. om s. om s. om s. om s.
4 5 PCH_SPI_SI_R SML1CLK 6 1
GND DI(IO0) EC_SMB_CK2 10,26,37 +3V_SPI
ic c i c QC2A
c 2N7002DWH_SOT363-6 @ i c c i c .c@ 2 1K_0402_1% tics.c
at s. PCB Footprint = ACES_91960-0084L_8P-T at s. at cs. at RC390
5
W25Q64FVSSIQ_SO8 SA000039A30
PCH_SPI_SIO2 s a
m tic m tic SML1DATA ic ic
SB00000I700 1
EC_SMB_DA2m10,26,37ti
Use socket footprint
emat RC3911 @ 2 1K_0402_1% emat
3 4
e a e a e a
chem ch m ch m chem chem
QC2B PCH_SPI_SIO3
SPI ROM Part:

k che kSche
2N7002DWH_SOT363-6
S h 2nd: SA00007LA10,64M GD25B64CSIGR(GigaDevice) S
Main:SA000039A30,64M W25Q64FVSSIQ(Winbond )
S S
okSch okSch
SB00000I700

Sc o o
B RC368 3rd: SA000099300,64M N25Q064A13ESEDFF(Micron) B
S S
15_0402_5%
book 26 bo k book book
ePCH_SPI_CLK_R te oo e e
PCH_SPI_CLK 1 PCH_SPI_CLK_R
ot bo ot ot bo
2
o+3V_PRIMb o
N teb
PCH_SPI_CS0#_R 1 @ 2
N 2 ot
e N e +3VALW 1K_0402_5% N e
ot ot
EMI@ RC357
1
CC9 N
o
10P_0402_50V8J
N N N
@EMI@
2

RC81 RC82
10K_0402_5%
m om
10K_0402_5%
m ES@ m
co co o 2 1K_0402_1%
PCH_SPI_SIO3
RC51 1

s. om .c m SB00000I700 s. om .c s.
c
2

s s o ESm
1

i c c i c c o i c c i c cSKL-U
From WW36 MOW for sample
ic .c
at cs. at cs. TP_SMBCLKt27
a cs. t . t
SMBCLK 1 6
a s a s
i i i m tic m tic
QC7A

h emat h emat 2N7002DWH_SOT363-6

h emat hema hema
Schem Sc em Sc em c c
5

okSch okSch TP_SMBDATA 27 kS he kS he

Sc ookSc ookSc
SMBDATA +3VS_PGPPA
o k
4 3
o k
eboo eboo b
e oo b
e oo
ot ot ot ot
QC7B SB00000I700

N teb N teb N teb N teb

2N7002DWH_SOT363-6 PM_CLKRUN# 1 2
RC107 8.2K_0402_5%
o o o o
EON SA000046400 S IC FL 64M N
EN25Q64-104HIP SOP 8P N N SERIRQ 1 2
N
MXIC SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P
WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM RC122 8.2K_0402_5%
Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P
A Follow 543016_SKL_U_Y_PDG_0_9 A
m m m m
co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i i m ti m ti
h emat h emat emat
hClassification hema hema
c
S he m c m c
Security m Compal Secret Data c Compal Electronics, Inc. c
kS he heDate
kScIssued 2014/12/11 Deciphered Date k he
S 2015/12/31 Title kS he
Sc ookSc ookS ook Sc SKL-U(3/12)SPI,ESPI,SMB,LPC ookSc
b
e oo b
e oo b o b
eCUSTODY te oo
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

ot ot otTHIS SHEET oNOR

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

N teb N teb N teb OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THE INFORMATION IT CONTAINS Custom
CKL50 No eb v1.0

o o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT
o Date: Thursday, Marcho t
09, 2017 Sheet 7 of 59
5
N 4
N 3
N 2
N 1
 ot o ot o ot o ot
5 4 3 2 1o

N teb N teb N teb N teb

o o o o
N N N N

m m m m
co co co co c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
emaUC1Gti emRev_0.53
i
emat
i m tic
at
SKL-U
h
c em c h h h+3V_PRIM hema
S h kSche
m AUDIO Sc em Sc em kSche
c
okSch okSch
D D

Sc o oHDA_SYNC
S o o ooUMA S

1
BA22
b k k k k DIS
e ooHDA_SDOUT
HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
ebooSDIO/SDXC eb o e oob
ot BB22 HDA_BLK/I2S0_SCLK
ot ot bo PX@ RC127
ot
N teb HDA_SDIN0 N teb N teb
PROJECT_ID
BA21 HDA_SDO/I2S0_TXD N e 10K_0402_5% 0 1
24 HDA_SDIN0
oT35 TP@ AY21 HDA_SDI0/I2S0_RXD o AB11 o t o
N N VRAMCLK_SEL N N

2
HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 900MHz 1000MHz
J5 AB12 PROJECT_ID
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 PLAT_SEL0
I2S1_SFRM GPP_G3/SD_DATA2 VRAM Clock 0

1
AW20 W11 PLAT_SEL1 1
I2S1_TXD GPP_G4/SD_DATA3 W10 RC128
m SOC_GPIOF1 AK7 m GPP_G5/SD_CD#
m W8 UMA@ m 10K_0402_5% +3V_PRIM
co co co co
T38 TP@ GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
c
s. om s. om s. om s. om s.
SOC_GPIOF0 AK6 W7
T39 TP@ GPP_F0/I2S2_SCLK GPP_G7/SD_WP
i c c i c AK9
c i c c i c c ic .c

2
at cs. at cs. at cBB9 at cs. t
GPP_F2/I2S2_TXD
s.

2
AK10 BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 a s
i ti i i m tic
RC900
emat em emat AB7 SD_RCOMP RC76 2 emat
GPP_A16/SD_1P8_SEL
H5 a hema
X76@ 10K_0402_5%
c h m c h m c h m 1 200_0402_1%
c h m c
S he kS he
D7 GPP_D19/DMIC_CLK0
kS he
SD_RCOMP
kS he S e
okSch

1
GPP_D20/DMIC_DATA0
Sc ookSc D8 ookSc AF13 SOC_GPIOF17 ookSc VRAMCLK_SEL o
k
e b o C8 GPP_D17/DMIC_CLK1
e oob GPP_F23 T235 TP@
b
e oo b
e oo
ot boHDA_SPKR ot ot ot
GPP_D18/DMIC_DATA1

2
10,24 N t
HDA_SPKRe AW5 N teb N teb N teb RC901
o GPP_B14/SPKR
o o o X76@ 10K_0402_5%
N N 7 OF 20 N N

1
C
SKL-U_BGA1356 C

om HDA for AUDIO om om om

s .c m s .c m s .c m s .c m PLAT_SEL1
s.
c
ic . c o RPC9 o
ic c 26 ME_FLASH_EN RC367 1 @ 2 0_0402_5%
ic c o ic c o ic c
at cHDA_SYNC_AUDIO
s 1 8
at s. at s. at s. at cs.
m tic m tic m tic
0 1
i
m t24 7 HDA_SYNC
i
emat
2

h e a 3 6 HDA_RST# e a e a e a
ch m h ch m che
24 HDA_RST_AUDIO# KBL-U
PLAT_SEL0 0 KBL-R

2
Schem 24 HDA_SDOUT_AUDIO Schem m
4 5 HDA_SDOUT +3V_HDA

G
kSche @
3 k kSche S
k ch NA
Sc o o c o o
33_0804_8P4R_5% 1 @ 2 RC380 1 HDA_SDOUT SKL-U
o kS kS
o QC380 o kS book
S
eb o eb oMESS138W-G_SOT323-3 eb o
1K_0402_1%

S
e
ot bo ot bo ot bo ot bo
N te N te N te N te
o 2 EMI@ 1 HDA_BIT_CLK o o o
24 HDA_BITCLK_AUDIO
N RC383 33_0402_5% N N N +3V_PRIM
@EMI@ HDA_SDOUT:
ME Flash Descriptor Security Override
CC143 22P_0402_50V8J Low : Disabled(Default)
om m om m

2
com co

2
.c m
High.c
: Enabled c
srequest
o s. oSKL_ULT s m s. om s.
ic
EMI c i c c UC1I
ic co i c c KBLR@ RC919 SKYL@ RC916
ic c
at s. at cs. at cs. at cs. at cs.
Rev_0.53 10K_0402_5% 10K_0402_5%

e m tic e m tiCSI-2 emat

i
emat
i
emat
i

1
a a PLAT_SEL0
chem ch m A36 chem
C37 chem PLAT_SEL1 chem
S kSche C38
B36 CSI2_DN0 CSI2_CLKN0 S S S
h k chD37
okSch okSch
Sc o ookSC32
CSI2_DP0 CSI2_CLKP0

2
B B
o k S D38 CSI2_DN1 book booKBLU@ k
CSI2_CLKN1
e b o CSI2_DP1 e b o
CSI2_CLKP1
D32
e e
ot o ot o ot o ot 10K_0402_5%
o
C36 C29 KBLU@ RC918 RC917

N teb N tebCSI2_CLKP2 B26 N teb N teb

D36 CSI2_DN2 CSI2_CLKN2 D29 10K_0402_5%
A38 CSI2_DP2
o o o o

1
B38 CSI2_DN3 CSI2_CLKN3
N CSI2_DP3 N CSI2_CLKP3
A26
N N
C31 E13 CSI2_COMP RC80 2 TP@ 1 100_0402_1% SKYL@ KBLR@
D31 CSI2_DN4 CSI2_COMP B7 RC918 RC917
CSI2_DP4 GPP_D4/FLASHTRIG T63
C33
CSI2_DN5
m m D33
m m 10K_0402_5% 10K_0402_5%
co co co co
CSI2_DP5 EMMC
SD028100280
A31 SD028100280
c
s. om s. om s. om s. om s.
B31 CSI2_DN6 AP2
i c c i c c A33 CSI2_DP6 GPP_F13/EMMC_DATA0
i c c i c c ic .c
at cs. at cs.
AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3 at cs. at cs. a t s
emat
i
em
i CSI2_DP7 GPP_F15/EMMC_DATA2
emat
i
emat
i m tic
at
AN3
hema
GPP_F16/EMMC_DATA3
h h A29
h
AN1
h
Schem Sc em B29 CSI2_DN8 c em Sc em c
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5 S
kS he
AN2

okSch okSch okSch

C28 CSI2_DP8 AM4
Sc D28 CSI2_DN9
ookSc
GPP_F19/EMMC_DATA6
o k o k
AM1
o k
eb o b eboo b
A27 CSI2_DP9 GPP_F20/EMMC_DATA7

ot bo
B27 CSI2_DN10
o te oo AM2
ot ot
e oo
N te C27 CSI2_DP10 b
GPP_F21/EMMC_RCLK
e
N GPP_F22/EMMC_CLK AM3
N teb N teb
o D27 CSI2_DN11
CSI2_DP11
t
oGPP_F12/EMMC_CMD AP4
o o
N N
9 OF 20 AT1 EMMC_RCOMP 2 1
N N
EMMC_RCOMP RC89 200_0402_1%
SKL-U_BGA1356
A A
m m m m
co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti m ti m ti
h emat h emat Security Classification
hema
Compal Secret Data
hema Compal Electronics, Inc. chem a
c
S he m c m c c
kS he k che kSche kSche
Issued Date S 2014/05/19 Deciphered Date 2015/12/31 Title

Sc ookSc THIS SHEETo

o S DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND o
oCONTAINS S SKL-U(4/12)HDA,EMMC,SDIO,CSI2 o
o kS
b ebo ok eb
kDIVISION
eb o
OF ENGINEERING CONFIDENTIAL
e oo oo IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT OF R&D Size Document Number Rev
ot ot tTHE ot bo
Custom v1.0
DEPARTMENT
oCOMPAL
EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR INFORMATION
CKL50
N teb N teMAY BEb N te
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF b ELECTRONICS, INC.
N t e
o o o Date:
o
Thursday, March 09, 2017 Sheet 8 o f 59
5
N 4
N 3
N 2
N 1
 ot o ot o ot o ot o
5 4 3 2 1

+RTCVCC N teb N teb N teb N teb

o o o o
RC91 1 2 20K_0402_5%
N
PCH_SRTCRST#
N N N
CC10 1 2 1U_0402_6.3V6K

CLRP1 1 2 SHORT PADS CLR ME UC1J SKL_ULT

om PCH_RTCRST# m m m
Rev_0.53

c20K_0402_5% co co co c
s. 2 o s. om s. om s. om s.
CLOCK SIGNALS
RC93 1
c m c c c
i 2c 1U_0402_6.3V6K i c
CLK_PEG_VGA# D42
i c i c ic .c
at cs. at cs. GPU 3637 CLK_PEG_VGA at cs. t . t
36 CLK_PEG_VGA# CLKOUT_PCIE_N0
s s
CLK_PEG_VGA
a a
CC11 1 C42

m tic m tic
AR10 CLKOUT_PCIE_P0
ti 1 2 SHORT PADS i ti
VGA_CLKREQ#

emaCLRP2 emat em
VGA_CLKREQ# GPP_B5/SRCCLKREQ0#

hema hema
CLR CMOS
h h CLK_PCIE_LAN#
hB42 a
Schem RC941 Sc em LAN
23 CLK_PCIE_LAN# CLK_PCIE_LAN c A42 mCLKOUT_PCIE_N1 F43 c c
D 23 CLK_PCIE_LAN
S e CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43
S he kS he
D

okSch okSchD41 ok
2 1M_0402_5% SM_INTRUDER# LAN_CLKREQ# AT7
23 LAN_CLKREQ#

Sc PCH_RTCRST# 2 @ 1 Sc ookSc
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
o k o
CLK_PCIE_WLAN#
oBA17 SUSCLK
CLR_CMOS# b
ebo ok b k b
32 CLK_PCIE_WLAN# SUSCLK 32
C41 CLKOUT_PCIE_N2 GPD8/SUSCLK
e 26 oo e oo e oo
WLAN 32 CLK_PCIE_WLAN CLK_PCIE_WLAN
0_0402_5% R1088
t
o close o t MINI1_CLKREQ# AT8 CLKOUT_PCIE_P2
otXTAL24_IN
E37 PCH_KBLU24_IN
ot
b to RAM door N teb eb N teb
32 MINI1_CLKREQ# GPP_B7/SRCCLKREQ2#

1
PCH_SRTCRST# 2 @ 1 E35 PCH_KBLU24_OUT
0_0402_5% R1089 NCMOSte
Clear D40 N tXTAL24_OUT
@ o CardReader o C40 CLKOUT_PCIE_N3 oXCLK_BIASREF E42 XCLK_BIASREF RC96 1 2 2.7K_0402_1% o
N N N N
CLKOUT_PCIE_P3 +1.0V_CLK5_F24NS
JCMOS1 CR_CLKREQ# AT10
0_0603_5% GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1
2

B40 RTCX1 AM20 PCH_RTCX2

A40 CLKOUT_PCIE_N4 RTCX2
CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 PCH_SRTCRST#
+3VS GPP_B9/SRCCLKREQ4# SRTCRST# AM16 PCH_RTCRST#
m
oCLKREQ_PCIE#4 m m
E40 RTCRST#
m
co co co
CLKOUT_PCIE_N5
.c210K_0402_5% c
E38

om s. om s. om s. om s.
CLKOUT_PCIE_P5
RC165 s
1 CLKREQ_PCIE#5 AU7 XCLK_BIASREF RC97 1 @ 2 60.4_0402_1%

i c c
From 545659_SKL_PCH_U_Y_EDS_R0_7
i c c i c c
GPP_B10/SRCCLKREQ5#
i c c ic c
at . 10K_0402_5% at cs. at cs. at s. at cs.
CLKREQ_PCIE#5
RC105 s
1 2

ic RPC10 <Cocoa_1027>
i i icU/R Colay m ti
10 OF 20
<DB> Add RX1~4 for KBL
h emat check un-use GPIO for
h em at
termination guidance
h em at Change h ema
XTAL(YC1) tot2016 Type hema
Schem c m Sc em Sche m c
8 1 LAN_CLKREQ# SKL-U_BGA1356
MINI1_CLKREQ#
k S he kS he
okSch okScRX1
7 2

Sc 6
5
3
4
CR_CLKREQ#
ookSc o
PCH_KBLU24_IN
o
2 KBLU@ 1 33_0402_1% PCH_XTAL24U_IN PCH_RTCX2
ookSc
k k
teboo eboo eboo b
e oo
ot 2 0_0402_5% ot2 KBLU@ ot
10K_0804_8P4R_5%
o GPU PCH PLTRST
VGA_CLKREQ#N ebside Buffer N 1 teb N RX2te b 1 33_0402_1% PCH_XTAL24U_OUT 1 N teb
ot
1 @ 2 PD at RC99 PCH_KBLU24_OUT 2 PCH_RTCX1 1 2
+3V_PRIM RC109 10K_0402_5% o o RC92 1M_0402_5%
o RC98 10M_0402_5%
N N +3VS N change form 0 -> 33ohm
<PV> RX1/RX2 KBLU@
N
CC145
@ YC1 YC2
+3VALW_DSW 1 2 24MHZ_18PF_XRCGB24M000F2P51R0 32.768KHZ 9PF 10PPM 9H03200055
C C
1 2

5
@ UC8 3 1
RPC11
m om m om
PLT_RST#_PCH
1 0.1U_0402_16V7K 3 1
SJ10000Q800
1 oPCH_PWROK
PLT_RST# 23,26,28,32,36 o

P
DS12 IN1 PLT_RST# NC NC
.c .c m .c m .c m c
8 4

s.
O
s m
LAN_WAKE# 1 PCH_PWROK
s s 2s

6.8P_0402_50V8C
CC16
CC15
6.8P_0402_50V8C
7 2 2 2 SJ10000UJ00 1 1
i5c c o o
ic c SN74AHC1G08DCKR_SC70-5 ic c o o
ic cKBLU@ tics.c
IN2

G
PCH_RSMRST# 4

CC12
27P_0402_50V8J

27P_0402_50V8J
CC13
6 3

at cs. at s. at s. at cs.
4 SYS_RESET# KBLU@
a

3
CK0402101V05_0402-2

e
i
m t10K_0804_8P4R_5% ESD@
e m tic e m tic emat
i 2 2
emat
ic
h a a a
ch m ch m chem chem
SCV00001K00

Schem kSche kSche S S

S c o
o kS o
o kS okSch okS6.8pch
book <SI> CC15/CC16 o
2 1 SYS_RESET#
CLRP3 SHORT PADS
eb o eb o e e b SI o change
k -> 3.9p
ot bo ot bo ot bo ot bo
1 @ 2 SUSCLK
RC100 1K_0402_5%
2 1 PCH_DPWROK
N te N te N te N te
RC101 100K_0402_5%
o o o o
N N N TP@T254
TP@T255
N
TP@T256
TP@T257
TP@T258
+3VALW_DSW
m m UC1K
m
SKL-U
m
co co co co
Rev_0.53
c
s1 . o2m s. om s. om s. om s.
SYSTEM POWER MANAGEMENT

c
iRC103 .c
PM_BATLOW#
i c c i c c
AT11 PM_SLP_S0#
i c c ic c
at RC104 at s. at s. at cs. at cs.
8.2K_0402_5% GPP_B12/SLP_S0# AP15 PM_SLP_S3#
s1 PLT_RST#_PCH AN10 GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# 12,26,35

m tic
WAKE#
m tic m tic
2 BA16
i i
emat emat
PM_SLP_S4# 12,26,35,49
1K_0402_5% SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5#
e e AY17 e
T296 TP@ AY16 PM_SLP_S5# 26
h a AC_PRESENT_R
a PCH_RSMRST#
a
SYS_RESET# GPD10/SLP_S5#

ch m h RSMRST# chemPM_SLP_SUS# chem

1 @ 2 26 PCH_RSMRST#

Schem cA68 m
RC106 10K_0402_5% AN15 PM_SLP_SUS#

kSche kScB65 he S S
SLP_SUS# AW15 SLP_LAN# 26
RC102 1 @ 2 1K_0402_5% H_CPUPWRGD
SLP_LAN# BB17k
ch okSch
T95 TP@ PROCPWRGD TP@T87

Sc
EC_VCCST_PG SLP_WLAN#
o o o PM_SLP_A#
B B
TP@T88
o k S S kS
bo boo book
Only For Power Sequence Debug VCCST_PWRGD GPD9/SLP_WLAN# AN16

eb o ok
+3V_PRIM SYS_PWROK B6 GPD6/SLP_A#
26 PCH_PWROKte e e
26 SYS_PWROK

ot bo t t
PCH_PWROK BA20 SYS_PWROK
bo o AY15 AC_PRESENT_R
BA15 PBTN_OUT#
o o
PBTN_OUT# 26
ACIN 26,37 o
o
eb AU13 PM_BATLOW# RC108 N teb
PCH_DPWROK_R BB20 PCH_PWROK GPD3/PWRBTN# 2 1
N e N e DSW_PWROK
NGPD1/ACPRESENT
ot ot ot
0_0402_5%
o
RC1151 @ 2 10K_0402_5% SOC_VRALERT# PCH_SUSWARN# AR13 GPD0/BATLOW#
26 PCH_SUSWARN#
N 26 SUSACK# 2
RC110
@ 1
0_0402_5% N
SUSACK#_R AP11 GPP_A13/SUSWARN#/SUSPWRDNACK
GPP_A15/SUSACK# N AU11 EC_PCIE_WAKE#_CPU 2 @ 1 N
EC_PCIE_WAKE# 26,32
WAKE# BB15 GPP_A11/PME# AP16 SM_INTRUDER# RC922 0_0402_5%
+3VALW_DSW 32 WAKE# LAN_WAKE# WAKE# INTRUDER#
AM15
AW17 GPD2/LAN_WAKE# AM10 EXT_PWR_GATE#
GPD11/LANPHYPC TP@T298
T94 TP@ AT15 GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT#

o1m m 11m m
GPD7/RSVD GPP_B2/VRALERT#
OF 20
co co co
ESD@
2 c c
s. om s. om s. om s. om s.
PBTN_OUT# DS13
@ RC111
100K_0402_5% SCV00001K00
SKL-U_BGA1356

t i c c
1
i c
2 H_CPUPWRGD
c i c c i c c ic .c
a s . at s. at cs. at cs. a t s
m tic m tic
CK0402101V05_0402-2
emat
i
emat
i m tic
c hema h
DS14 e@ESD@ a h h hema
Sc m Sc em Sc em c
SCV00001K00
S he 1
he
2 SUSACK#
kS he
Sc o okScCK0402101V05_0402-2 o okSch o okSch ookSc
k k DC3CH751H-40PT_SOD323-2 k
eboo eboo eboo b
SCS00003500
e oo
ot ot PCH_RSMRST# ot ot
N teb N teb N teb N teb
@ESD@ 1 2 PCH_PWROK
DS15
SCV00001K00
o 1 2 SYS_PWROK
o o o
N N 2
DC4
1
SCS00003500 N
SPOK 48
N
CK0402101V05_0402-2 CH751H-40PT_SOD323-2

2 @ 1 PCH_DPWROK_R
26 PCH_DPWROK
A RC112 0_0402_5% A

m m m m
co co co co c
s. om
From EC(open-drain)
c
+1.0V_VCCST
c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti i m ti
emat emat emat
1

h h hemSecurity
a Classification
Compal Secret Data ch m hema
RC113
c
S he m 1K_0402_5% c m c Compal Electronics, Inc. c
he
kSEC_VCCST_PG kS he 2014/05/19 kS Date h
e 2015/12/31 kS he
Sc ookSc ookSc ookScINC. AND CONTAINS CONFIDENTIAL ookSc
Issued Date Title
Deciphered
2

RC1161 2 60.4_0402_1%
26,35 EC_VCCST_PG_R
b b THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTYb
SKL-U(5/12)CLK,GPIO b
e oo e oo eNEITHER oSHEET NOR THE INFORMATION e o
OF COMPAL ELECTRONICS, CONFIDENTIAL

ot ot otINC. WRITTEN
Size

CKL50 ot bo
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED
oTHIS
FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

N teb N teb eb CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INFORMATION IT
IT CONTAINS
CONTAINS Custom v1.0
N tPRIOR NMarcht 09,e
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

o o o o
Date: Thursday, 2017 Sheet 9 of 59
5 4 3 2 1
N N N N
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o o o o
N N N N

UC1F SKL-U +3VS

Rev_0.53
m LPSS
m ISH

om m
co co .c m co c
c s. om AN8
c s. om c s o c s. om s.
i c
AP7 GPP_B15/GSPI0_CS#
i c
P2
i c i c
DGPU_PWR_EN RC3821 @ 2 10K_0402_5%
ic .c
at cs. at cs. at cs. at cs. t
GPP_B16/GSPI0_CLK GPP_D9 TS_GPIO_CPU 20
a s
AP8 P3

m tic
AR7 GPP_B17/GSPI0_MISO GPP_D10 P4
i i i i
GSPI0_MOSI

emat emat emat emat

GPP_B18/GSPI0_MOSI GPP_D11 P1 +3V_PRIM

hema
GPP_D12
c h AM5
h h h
m Sc em Sc em Sc em c
AN7 GPP_B19/GSPI1_CS# M4
S he
D
AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3
k8 che
RPC14 S
D

okSch okSch okSch

SOC_GPIOB21

Sc
AN5 GPP_B21/GSPI1_MISO
2 o
GSPI1_MOSI GPP_D6/ISH_I2C0_SCL 1
o
GPP_B22/GSPI1_MOSI
o
N1 o SOC_GPIOB21
o 7S
AB1 b k k k k
eb o eboo b
GPP_D7/ISH_I2C1_SDA N2

oo
eGPP_C8/UART0_RXD e 4 o 5
TP@T129 UART_0_CRXD_DTXD WL_OFF# 3 6

ot ot bo ot ot bo10K_0804_8P4R_5%
TP@T128 UART_0_CTXD_DRXD AB2 GPP_D8/ISH_I2C1_SCL 5,26 NMI_DBG#_CPU NMI_DBG#_CPU
W4 b
N teb
GPP_C9/UART0_TXD AD11
WL_OFF# N e GPP_C10/UART0_RTS#
N e
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
N te
ot GPP_C11/UART0_CTS# ot
AB3 AD12
o o
32 WL_OFF# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
TP@T133
TP@T132
N AD1
UART_2_CRXD_DTXD
UART_2_CTXD_DRXD AD2 GPP_C20/UART2_RXD
N U1
N N
AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
UART_2_CTXD_DRXD AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS#
1

U4
R5194 GPP_D16/ISH_UART0_CTS#/SML0BALERT#
@ m U7
m AC1
DGPU_PWR_EN 26,38,55,56 m m
co o co co
0_0402_5% GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD
.cGPP_C14/UART1_RTS#/ISH_UART1_RTS# c
U6 AC2

s. om s. om s. om s.
GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 DGPU_HOLD_RST# 36

c
UART_2_CRXD_DTXD
c s o m GPU_PGD c c tics.c
2

i c
U8
i c
AB4
i c i c
at cs. t s. t s. t s.
GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# 56
U9
GPP_C19/I2C1_SCL
a a a a
m tic m tic m tic m tic
AY8
i
emat
GPP_A18/ISH_GP0 BA8

hema hem hema he

AH9
h AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7
a a
c
S he m GPP_F5/I2C2_SCL
c GPP_A20/ISH_GP2 BA7
c c RPC12
c m
+3VS

kSche kSche ODD_DA# 30 kSche S he

GPP_A21/ISH_GP3 AY7 ODD_PWR 30
k
AH11 1 8
GPP_A22/ISH_GP4 AW7

Sc
AH12 GPP_F6/I2C3_SDA
o kSo GPP_A23/ISH_GP5 AP13o
o kS
<Cocoa_1027>
Follow #544669 GPIO o
o S
5,26 EC_SCI#
EC_SCI# 2
o 7
S c
4o
GPP_F7/I2C3_SCL SOC_GPIOA12 ODD_PWR 3 6
AF11 b
I/O k
setting k
eb o eb o eb o
GPP_A12/BM_BUSY#/ISH_GP6 T122 TP@

oo
ODD_DA# 5
eGPP_F8/I2C4_SDA
ot b ot bo ot bo ot bo
AF12
GPP_F9/I2C4_SCL 6 OF 20 <Cocoa_1127> remove EC_LID_OUT# function 10K_0804_8P4R_5%
N te N te N te N te
o SKL-U_BGA1356 o o o
N N N N
C C
CPU THERMAL SENSOR
Functional Strap.c om om om om
s
Definitions
m
Strap Pin
s .c m s .c mAddress : 0x48 s .c m s.
c
ic c o ic c o ic c o o
at cs.
+3VS
at s. at s.
UC3
tic .c ic c
at cs.
EC_SMB_DA2a7,26,37 s
m tic m tic m tic
1 5
SPKR m i Down): i
emat
7,26,37 EC_SMB_CK2 SMBCLK SMBDATA
(InternaltPull
hema e a e a e a
+3VS
RC117 h
ch m ch m chem
2

Sch c1 e m
@ 2 100K_0402_5% HDA_SPKR GND
eSwap Override
TOP
kS
HDA_SPKR 8,24
kSche kS1 che S

.1U_0402_16V7K
3 4
h ALERT# +Vs
okSch
Sc o c o o

CC127
0 = Disable TOP Swap mode.---> AAX05 Use o kS RC118 1 @ 2 4.7K_0402_5% GSPI0_MOSI
o kS o kS book
eboo RC201 1 @ 2 150K_0402_1% GSPI1_MOSI eb o eb o
G753T11U_SOT23-5
t e
ot bo ot bo ot o
SA00008CH00
o
N teb N teb
2
1 = Enable TOP Swap Mode.
N te N te
o o o o
N N <DB> Change N Thermal Sensor IC N
GSPI0_MOSI (Internal Pull Down):

No Reboot
m m m m
co--> AAX05 Use
0 = Disable No Reboot mode. co co co c
c s. om c s. om c s. om c s. om s.
1 = Enable No t i c (PCH will disable the TCO i c i c i c ic c
s. feature). This function is useful at s. at s. at s. at cs.
Reboot Mode.
a c
e mrunningti ITP/XDP.
Timer system reboot
e m tic e m tic e m tic emat
i
h
when a a a a
Schem ch m ch m ch m chem
kSche kSche kSche S
okSch
Sc GSPI1_MOSI (Internal Pull Down): o o o
B B

o k S o k S o k S
eboo eboo eboo e book
Boot BIOS Strap Bit ot ot ot ot o
N teb N teb N teb N teb
0 = SPI Mode --> AAX05 Use o o o o
N N N N
1 = LPC Mode

m m m m
co co co co c
c s. om cs. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
emat
i
emat
i
emat
i m tic
h h h h hema
Schem Sc em Sc em Sc em c
kS he
Sc o okSch o okSch o okSch ookSc
k k k
eboo eboo eboo b
e oo
ot ot ot ot
N teb N teb N teb N teb
o o o o
N N N N

A A

m m m m
co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti i m ti
h emat h emat hem a emat hema
c m c m c Security Classification Compal Secret Data ch m Compal Electronics, Inc. c
S he kS he kS he 2014/05/19 kS Date h
e 2015/12/31 Title kS he
Sc ookSc ookSc ookScINC. AND CONTAINS CONFIDENTIAL ookSc
Issued Date Deciphered
SKL-U(6/12)GPIO
b
e oo b
e oo b
e oTHIS oSHEET NOR THE INFORMATION
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,
Size Document Number
e b o Rev

ot ot ot CKL50 ot bo
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom v1.0

N teb N teb N teb

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER INFORMATION IT
IT CONTAINS
CONTAINS

NMarcht 09,e
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, 2017 Sheet 10 of 59
5 o 4 o 3 o 2 1 o
N N N N
 ot o ot o ot o ot
5 4 3 2 1o

N teb N teb N teb N teb

o o o o
N N UC1H SKL-U
N N
Rev_0.53

SSIC / USB3
PCIE/USB3/SATA
m m m H8 31m
co o co co
USB3_1_RXN USB3_RX1_N

s. om 36 .c
0.22uF for Gen3
s om PEG_PRX_C_DTX_N0 H13 s. om USB3_1_RXP
G8
C13 s. o31m
USB3_RX1_P
31 USB2.0/USB3.0
s.
c
i c c
PEG_PRX_C_DTX_N0
ic .c
PCIE1_RXN/USB3_5_RXN ic c USB3_1_TXN i c c 31
USB3_TX1_N
ic .c
at cs. at at s. at cs. t
PEG_PRX_C_DTX_P0 G13 D13
0402 2 s 1 PX@ PEG_PTX_DRX_N0 B17 PCIE1_RXP/USB3_5_RXP a s
36 PEG_PRX_C_DTX_P0 USB3_1_TXP USB3_TX1_P
ic2 A17 PCIE1_TXN/USB3_5_TXN m tic m tic
CC119 0.22U 6.3V K X5R
i i
emat em ematUSB3_RX2_N 31
36 PEG_PTX_C_DRX_N0
K X5Rt
h
36 PEG_PTX_C_DRX_P0
CC146 0.22U 6.3V
h a
0402 1 PX@ PEG_PTX_DRX_P0
h e
PCIE1_TXP/USB3_5_TXP a
J6
USB3_2_RXN/SSIC_1_RXN H6
h hema
c em Schem Sc em
USB3_2_RXP/SSIC_1_RXP B13 c m USB3_RX2_P 31 c
S kSche kS he
PEG_PRX_C_DTX_N1 G11 USB2.0/USB3.0
h ok okSch
D 36 PEG_PRX_C_DTX_N1 USB3_TX2_N 31 D
PEG_PRX_C_DTX_P1 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
Sc c 0.22U 6.3V K X5R 0402 2 USB3_2_TXP/SSIC_1_TXPo
ookSc
36 PEG_PRX_C_DTX_P1
o S
CC128
k o
1 PX@ PEG_PTX_DRX_N1 D16 PCIE2_RXP/USB3_6_RXP o S USB3_TX2_P 31

eboo CC93 0.22U 6.3V K X5R 0402 2 ok

1 PX@ PEG_PTX_DRX_P1 C16bPCIE2_TXN/USB3_6_TXN b k b
36 PEG_PTX_C_DRX_N1
e PCIE2_TXP/USB3_6_TXP e oo H10 J10
e oo
ot ot H16bo t ot
36 PEG_PTX_C_DRX_P1 USB3_3_RXN/SSIC_2_RXN
o
N teb e N teb N teb
USB3_3_RXP/SSIC_2_RXP
N
PEG_PRX_C_DTX_N2 B15
ot G16
PEG 36 PEG_PRX_C_DTX_N2 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN
36 o
PEG_PRX_C_DTX_P2
PEG_PRX_C_DTX_P2 o A15 o
36 N
PEG_PTX_C_DRX_N2
CC124 0.22U 6.3V K X5R 0402 2 N
1 PX@ PEG_PTX_DRX_N2 D17 PCIE3_RXP
PCIE3_TXN N
USB3_3_TXP/SSIC_2_TXP
N
CC92 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_P2 C17 E10
36 PEG_PTX_C_DRX_P2 PCIE3_TXP USB3_4_RXN F10
PEG_PRX_C_DTX_N3 G15 USB3_4_RXP C15
36 PEG_PRX_C_DTX_N3 PCIE4_RXN USB3_4_TXN
PEG_PRX_C_DTX_P3 F15 D15
m 36 PEG_PRX_C_DTX_P3
m PEG_PTX_DRX_N3 B19 PCIE4_RXP
m USB3_4_TXP
m
co
CC129 0.22U 6.3V K X5R 0402 2
co
1 PX@
co c31om
36 PEG_PTX_C_DRX_N3 PCIE4_TXN
c
s. om s. om s. om s. 31 s.
CC118 0.22U 6.3V K X5R 0402 2 1 PX@ PEG_PTX_DRX_P3 A19 AB9
36 PEG_PTX_C_DRX_P3 PCIE4_TXP USB2N_1 USB20_N1
ic c i c c i c c
AB10
i c c o USB20_P1 USB2.0/USB3.0 ic c
t . at cs.
PCIE_PRX_DTX_N5 F16
at cs.
USB2P_1
atUSB20_N2
s. 31 at cs.
LANa ics
23 PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5 E16 PCIE5_RXN
i i AD6
ic m ti
emat e11 m at emat ematUSB20_P2 31
23 PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5 C19 PCIE5_RXP USB2N_2 AD7
hema
CC18 2 0.1U_0402_16V7K USB2.0/USB3.0
c h 23 PCIE_PTX_C_DRX_N5
c h PCIE_PTX_DRX_P5 D19 PCIE5_TXN
c h USB2P_2 h
m m m AH3Sc m c
23 PCIE_PTX_C_DRX_P5 CC17 2 0.1U_0402_16V7K
S he kS he kS he
PCIE5_TXP
k
USB2N_3 AJ3 he USB20_N3 33 S he
kboard
Sc ookSc ookSc USB2P_3o Sc
ookSc
PCIE_PRX_DTX_N6 G18 USB2.0 ( on small )
32 PCIE_PRX_DTX_N6
b
32 PCIE_PRX_DTX_P6
PCIE_PRX_DTX_P6 F18 PCIE6_RXN
b b o k
USB20_P3 33
b
e oo CC19 2 e oo oo AD10 e oo
PCIE6_RXP
WLAN CC20 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N6 D20 eUSB2N_4 AD9
ot PCIE_PTX_DRX_P6t C20 PCIE6_TXN
ot USB2P_4 t
32 PCIE_PTX_C_DRX_N6 USB20_N4 32
o o
N teb N tebPCIE6_TXP N teb N teb
32 PCIE_PTX_C_DRX_P6 1 0.1U_0402_16V7K USB20_P4 32 WLAN
o o F20 PCIE7_RXN/SATA0_RXN o AJ1 o
30 N N N N
30 SATA_PRX_DTX_N0 USB2N_5 AJ2 USB20_N5 20
SATA_PRX_DTX_P0 E20 Camera
PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 20
HDD 30 SATA_PTX_DRX_N0
B21
PCIE7_TXN/SATA0_TXN
USB2
A21 AF6
30 SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 20
C
USB2P_6
AF7 USB20_P6 20 Touch Screen C
G21
om om om om
30 SATA_PRX_DTX_N1 PCIE8_RXN/SATA1A_RXN F21 AH1
.c m .c m .c m .c m c
30 SATA_PRX_DTX_P1 USB20_N7 33
s.
PCIE8_RXP/SATA1A_RXP USB2N_7
ODD s 30 SATA_PTX_DRX_N1 s
D21
s
AH2
s USB20_P7 33 Card Reader
ic c o ic c o PCIE8_TXN/SATA1A_TXN
ic c
C21 o USB2P_7
ic c o ic c
at s. at s. at s. at s. at cs.
30 SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8
m tic m tic m tic m tic
USB2N_8 AF9
i
emat
E22

h e a e a E23 PCIE9_RXN e a
USB2P_8
e a
Schem ch m B23 PCIE9_RXP ch m USB2N_9 AG2Sc
AG1 h m chem
c o kSche o k che
A23 PCIE9_TXN S
PCIE9_TXP USB2P_9 k
o c he S
okSch
S o kS S AH7S
eb o e
F25
book
E25 PCIE10_RXN
book
eUSB2N_10 e book
ot bo ot D23bPCIE10_RXP
o ot USB2P_10
b o AH8 ot o
N te N te C23 PCIE10_TXN N te AB6 USB2_COMP RC119 1 2 N teb
113_0402_1%
o o PCIE10_TXP o USB2_COMP AG3 USB2_ID o
N RC120 1 2 100_0402_1% PCIE_RCOMPNN F5 N USB2_ID AG4 USB2_VBUSSENSE N
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
T291 TP@ XDP_PREQ# PROC_PRDY# GPP_E10/USB2_OC1# USB_OC2#
m 5 XDP_PREQ# m D61
m D9
om
co co com
SOC_GPIOA7 BB11 PROC_PREQ# GPP_E11/USB2_OC2#
B9 USB_OC3# USB2_ID RC20 1 @ 2 0_0402_5%
s. om
TP@ T154
s. om
GPP_A7/PIRQA#
.
s o
GPP_E12/USB2_OC3#
s .c m s.
c
c c c c o
i i i i tics.c
DEVSLP0
c c E28
c J1
c
at s. at s. t . t .
T241 TP@
E27 PCIE11_RXN/SATA1B_RXN s
GPP_E4/DEVSLP0 J2
s
a DEVSLP1
a USB2_VBUSSENSE 1 @ 2
a
m tic m tic ic ic ic
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1
emat emat emat
D24 J3 RC21 0_0402_5%
e a e a C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 DEVSLP2 19

chem ch m chem
E30 PCIE11_TXP/SATA1B_TXP H2 chem
SATA_GP0 chem
S kSche S
19 SATA_PRX_DTX_N2
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 S S
h k h ok h okSch
Sc ookSc Sc
19 SATA_PRX_DTX_P2 ODD_PLUG# 30
B
SSD o
o k S A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 SATA_GP2 B

book book
19 SATA_PTX_DRX_N2 G4
B25bPCIE12_TXN/SATA2_TXN
eboo
GPP_E2/SATAXPCIE2/SATAGP2
19 SATA_PTX_DRX_P2
e o
PCIE12_TXP/SATA2_TXP e e
ot ot o ot o ot o
H1 SATA_LED# 33
N teb N teb N teb N teb
GPP_E8/SATALED#
8 OF 20 +3VS
o o o o
N N SKL-U_BGA1356 N DEVSLP1 N 1 2
SOC_GPIOA7 RC362 1 2 10K_0402_5%
GPIO DEVICE CONTROL RC361 10K_0402_5%

m om
When PCIE8/SATA1A is used USB_OC0# m
om
RPC13
co co
USB2 Port 1 and Port 2 SATA_LED# 1 8
s. om s .c mas SATA Port 1 (ODD), then
s. om s .c m
SATA_GP0 2 7
s.
c
i c c i c o PCIE11/SATA1B (M.2 SSD)
c cannot be used as SATA i c c
USB_OC1# USB2 Port 3 ic .co SATA_GP2 3 6 ic .c
at cs. at cs. at cs. a t s ODD_PLUG# 4 5 a t s
emat
i
emat
i Port 1. i
emat USB_OC2# NA m tic m tic
h h h hema 10K_0804_8P4R_5%
hema
Schem Sc em Sc em USB_OC3# NA c
kS he
c
he
kS +3V_PRIM
Sc o okSch o okSch NA ookSc ookSc
b o k b o k DEVSLP0
b b
e e e oo 1e
RPC20
o
ot bo ot bo oBt ot bo7
USB_OC1# 8
N teb
DEVSLP1 NGFF SSD KEY USB_OC3#
N te N te USB_OC0# N t3 e
2
o o o o 6
N N DEVSLP2 NA N USB_OC2#
N 4 5

SATA_GP0 NA 10K_0804_8P4R_5%

A NA A
m m SATA_GP1 m m
co co co co c
cs. om c s. om c s. om c s. om s.
ic c
SATA_GP2 ODD_PLUG#
i c i c i c i c
at cs. at cs. at cs. at cs. at cs.
i i m ti m ti i
h emat h emat Security Classification
hema Compal Secret Data
hema Compal Electronics, Inc. chemat
m
c
S he m c m c c
kS he Issued Date S e S e kS he
2014/05/19 2015/12/31 Title
okSch okSch
Deciphered Date
Sc ookSc THIS SHEETo
k oCONTAINS
k
SKL-U(7/12)PCIE,USB,SATA ookSc
b
e oo b OF ENGINEERING
b
DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND
o AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
CONFIDENTIAL
b
e oEXCEPT oo IT CONTAINS
e INFORMATION e o
Size Document Number Rev
ot ot ot THEb ot bo
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom v1.0
N teb N t eb
DEPARTMENT
MAY BE
N COMPAL
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
e ELECTRONICS, INC. CKL50 N e
o o o t Date:
o
Thursday, March 09, 2017 t Sheet 11 of 59
5
N 4
N 3
N 2
N 1
 ot o ot o ot o ot
5 4 3 2 1o

N teb N teb N teb N teb

o o o o
N +1.0V_PRIM TO N
+1.0V_VCCSTU N N
+1.2V_VDDQ +1.0VS_VCCIO
UC1N SKL-U
m om om
Rev_0.53
m
co com
CPU POWER 3 OF 4
.c m .c m c
+5VALW +1.0V_PRIM +1.0VS_VCCIO +1.0V_VCCSTU

c s. om c s o c s o AU23
c s. AK28o s.
i c i c i I c VDDQ_AU23
i VCCIO
c ic .c
at cs. at cs. at cs. at VCCIO
s. AL30 t
(Max) : 4.5 A AU28 AK30
AU35 VDDQ_AU28 a s
m tic m tic
R5188 1 @ 2 0_0603_5% I (Max) : 3.4 A
i i ti
emat e1matI (Max) : 0.04 A(+1.0V_VCCSTU) em AU42 VDDQ_AU35 VCCIO AL42

1U_0402_6.3V6K
1U_0402_6.3V6K
h
1
h h a VDDQ_AU42
h e a VCCIO AM28
hema

CC97

0.1U_0402_25V6
CC98
BB23
c em Sche m Sc em
1
c
BB32 VDDQ_BB23 m VCCIO AM30 c
S kSche kS he

0.1U_0402_25V6

CC96
1@ RON(Max) : 25 mohm
h ok okSch
D D
BB41 VDDQ_BB32 VCCIO AM42
Sc c @2 ookSc

CC151
o 2
S
V drop : 0.001 V
o o
BB47 o S
VDDQ_BB41 VCCIO
b k b k b k
VDDQ_BB47 b
e2 oo e oo oo
2
t t t e oo
BB51 AK23 +VCC_SA e
ot
VDDQ_BB51 VCCSA AK25
o o o
N teb b b N teb
VCCSA G23
UC5 N t e N e
ot AM40 VDDQC
VCCSA G25
1N
o 2 0_0402_5% 1
VOUT1 13o
14 +1.2V_VDDQ o
VOUT1 N N N
RC142 2 VIN1 VCCSA G27
26,35,49 SYSON VIN1 VCCSA A18 G28
+1.0V_VCCST VCCST VCCSA
RC144 1 @ 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 J22
9,26,35,49 PM_SLP_S4# ON1 CT1 VCCSA
CC95 +1.0VS_VCCIO A22
VCCSTG_A22 VCCSA
J23 I (Max) : 5 A
RC168 1 2 0_0402_5% 4 11 10P_0402_50V8J J27
13,26,35,49 m SUSP# m GND m AL23 VBIAS
m VCCSA K23
co RC194 5 co com co
+1.2V_VCCSFR_OC VCCPLL_OC
c VCCSA
s. om . ON2 m CT2 10 s. +1.0V_VCCSFR s. om s.
1 @ 2 0_0402_5% EN_1.8VS 1 2 K25
9,26,35 PM_SLP_S3#
c c s o c o c
VCCSA
tics.c
@ CC94 K20 K27
i c i c i c i c
at cs. at cs7. VIN2 t s. t s.
6 9 1000P_0402_50V7K K21 VCCPLL_K20 VCCSA K28
VOUT2 8 a VCCPLL_K21 a a VCCSA
m tic m tic m tic
+1.8V_PRIM
i m ti
K30
emat
VIN2 VOUT2 VCCSA
hema hema hema hema
+1.8VS

c h m c 15
c c AM23 VCCIO_SENSE T124 TP@ c
S he kS he
GPAD
kSche kS he
VCCIO_SENSE AM22 VSSIO_SENSE
VSSIO_SENSE T125 TP@
kS he
Sc ook1 Sc oo ookSc ookSc
EM5209VF_DFN14_2X3 <Cocoa_1113>
1 kS 1
1U_0402_6.3V6K
SA00007PM00 @ESD@ H21 VSSSA_SENSE
b
e oo b Per b bVSSSA_SENSE 52
te oo o o
VSSSA_SENSE H20
e e VCCSA_SENSE
CC156 CC99 VCCSA_SENSE
ot ot bo ot bo
CC100 543977_SKL_PDDG_Rev0_91, 52
o0.1U_0402_25V6 14 OF 20 VCCSA_SENSE
N teb b
I (Max) : 0.536 A(+1.8VS)
@ RON(Max) : 25 N
mohm t e 0.1U_0402_25V6 change CC95 N
value t
frome N t e
o 2
o 2 2
1000pf to 10pf for o o
N V drop : 0.013 VN
<= 65us timing for
N meet SKL-U_BGA1356
N
+1.0V_VCCSTU power rail.
C C

om om m
o+1.0V_VCCSTU om
s.c m s .c m s .c m +1.0V_VCCST
s .c m s.
c
ic c o ic c o ic c o ic c o ic c
at s. at s. at s. at cs. at cs.
em tic e m tic e m tic RC140 1 2 0_0402_5%
e m ti emat
i
h a h a a PSC a
Side
Schem Schem
+1.0V_PRIM TOk+1.0VS_VCCSTG / +1.0VS_VCCIO ch m ch m chem
c o c okSche o kSch1 e S
okSch

1U_0402_6.3V6K
S o kS o kS o kS
eb o eb o +1.0VS_VCCIO eb o e book
ot bo ot bo ot bo ot

CC48
o
N teb
+5VALW +1.0V_PRIM I (Max) : 3 A(+1.0VS_VCCIO)
N te RON(Max) : 6.2 mohm N te near pin A22 N te 2
o o o o
N V drop : 0.019 V N @ N N
1U_0402_6.3V6K
0.1U_0402_25V6

1 1 Imax : 2.77 A CC89 1 2 0.1U_0402_25V6

CC117
CC88

UC6 RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0

+1.0VS_VCCIO
m2 @ om m1
VIN1 m
co co co
2 2
s. om .c m s. om
VIN2 +1.0V_VCCSFR
s. om s.
c
+1.0VS_VCCIO
6 s +1.0VS_VCCSTG_IO
RC189
ic c 7
VOUTi c c o 1 2 0_0805_5% CC90 1
i c
2 0.1U_0402_25V6
c i c c ic c
at s. at s. at s. at s. at cs.
VIN thermal PSC Side BSC Side
e m tic 3
e m tic Imax : 3 A
e m tic RC143 1 2 0_0402_5%
e m tic emat
i
a VBIAS
a a a
chem SUSP# RC186 1
ONc
h m ch m ch m chem

1U_0402_6.3V6K
2 0_0402_5% 4 5
S kSche kSche kSch1 e S
GND 1
h okSch

1U_0402_6.3V6K
Sc 26 EC_S0IX_EN o o o
B B
S S S

CC56
RC187 1 2 0_0402_5%
o k TPS22961DNYR_WSON8 o k o k book
eb o eb o eboo

CC55
@
e
ot bo ot bo ot ot
2
o
N teb N teb
2
N e Part Number = SA00007XR00 N e
ot ot
For Verify S0IX <Cocoa_1027>
o o
connect to EC, checkN/w EC N N N
RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53

+1.2V_VDDQ
m
+1.0VS_VCCIO
m om
+1.2V_VDDQ
m
co BSC Side
co PSC Side
c co
PSC Side BSC Side
c
c s. om c s. om s.Side
BSC
o m s. om s.
i c i c ic c i c c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
emat
i m t i
emat
i m tic
h h he a h hema
Schem 1 Sc em Schem 1c e1m c

10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0201_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0402_6.3V6M

1U_0402_6.3V6K
1U_0201_6.3V6K

10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0201_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

10U_0603_6.3V6M
10U_0402_6.3V6M

kS he

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 S 1 1 1 1 1 1

Sc okSch ookS
k c okSch ookSc

CC42
CC36
CC30

CC33

CC43

CC46
CC28

o o
CC34

CC47 Follow 543016_SKL_U_Y_PDG_0_9

CC31

CC37
CC35
CC32

CC39

CC40
CC47

CC38
CC27

CC41

CC44

CC45
CC29

b o k b b 2 ok 2 b
e e oo 2 e e2 oo2
ot o2 ot ot o ot
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

N teb N teb N teb N teb

o o o o
N N N N
+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6
A 1UF/6.3V/0402 * 4 A
m m m m
co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti m ti m ti
h emat h emat Security Classification
hema
Compal Secret Data
hema Compal Electronics, Inc.chem a
c
S he m c m c c
kS he k che kSche kSche
Issued Date S 2014/12/11 Deciphered Date 2015/12/31 Title

Sc ookSc THIS SHEETo

o S DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND o
oCONTAINS S SKL-U(8/12)Power o
o kS
b ebo ok b kDIVISION
eb o
OF ENGINEERING CONFIDENTIAL
e oo oo IT CONTAINS
Size Document Number Rev
te
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT OF R&D
ot ot ot bo
Custom v1.0
DEPARTMENT
oCOMPAL
EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION
CKL50
N teb N teMAY BEb N te
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF b ELECTRONICS, INC.
N t e
o o o Date:
o
Thursday, March 09, 2017 Sheet 12 of 59
5
N 4
N 3
N 2
N 1
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb +1.0V_PRIM N teb

o o +1.0V_PRIM o o
+1.0V_PRIM +1.0V_APLL
N +3V_PRIM +3V_HDA
N N N

1U_0201_6.3V6K
1
UC1O SKL-U

22U_0603_6.3V6M

22U_0603_6.3V6M

1U_0402_6.3V6K

CC91
0.69A Rev_0.53 1209_follow G group GPIO
CPU POWER 4 OF 4
RC148 1 @ 2 0_0603_5% RC150 1 @ 2 0_0402_5% powe rail to +3V_PRIM
m m om m
1 1 1 2

CC147

CC61
22U_0603_6.3V6M

CC148
22U_0603_6.3V6M
@ @ AB19
co com co VCCPGPPA
VCCPRIM_1P0
.c m c
AB20 AK15
s. o s.1 CC63 s. om s.
1 1 +3V_PGPPA
m@
VCCPRIM_1P0
2 s

CC134
CC142

1U_0402_6.3V6K
@ near pin K15,L15 P18 AG15
o o
1
c c c c ic .c
2 2 VCCPGPPB Y16
VCCPRIM_1P0 +3V_PGPPB

t i c 2 i c i c i c
. at cs.2 1U_0201_6.3V6K at cs. t . t
VCCPGPPC Y15 +3V_PGPPC

CC72
a cs a s a s
+1.0V_PRIM AF18 +3V_1.8V_PGPPD
m tic m tic
2 VCCPRIM_CORE VCCPGPPD
i i i 2.574A AF19 T16

emat emat emat

+3V_PGPPE
2 +1.0VO_DSW V20 VCCPRIM_CORE VCCPGPPE AF16

hema hSDeCARD a
+1.8V_PRIM
h h h V21 VCCPRIM_CORE VCCPGPPF AD15

Schem Sc em c em +1.0V_PRIM c c m
VCCPRIM_CORE VCCPGPPG +3V_PRIM For
D
S e
S DCPDSW_1P0 +3V_PRIM S e D

okSch k h kAL1 ch ok ch
V19

Sc Follow 543016_SKL_U_Y_PDG_1_0 ookSc ookS

VCCPRIM_3P3_V19
o +1.0V_DTS S
o

1U_0402_6.3V6K
k k
K17 T1

eb o eboo b b
1 +1.0V_MPHYAON
L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1
e oo o
e +1.8V_PRIM
ot bo t ot b ot bo
+3V_PGPPA VCCMPHYAON_1P0

CC85
1U_0402_6.3V6K
+1.0V_CLK5_F24NS AA1
+3V_PRIM o b N15 VCCATS_1P8
N e N te N+1.0V_PRIM e 1.87A VCCRTCPRIM_3P3 N te
ot ot
2 N16 VCCMPHYGT_1P0_N15

CC68
1 AK17 +3V_PRIM_RTC
RC152 1 @ 2 0_0603_5% o N17 VCCMPHYGT_1P0_N16 o
N 22U_0603_6.3V6M
N near pin N18 N P15 VCCMPHYGT_1P0_N17
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 N
AK19 +RTCVCC
22U_0603_6.3V6M

BB14
2 VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1
CC130
CC135

@ @ +1.0V_PRIM K15 BB10 CC71 1 2 0.1U_0402_10V7K

RC197 1 @ 2 0_0402_5% L15 VCCAMPHYPLL_1P0 DCPRTC
VCCAMPHYPLL_1P0 A14 +1.0V_CLK6_24TBT
m 2 2
m +3V_SPI
m V15 m VCCCLK1

co co co co
+1.0V_APLL VCCAPLL_1P0
K19
c
s. om s. om s. om s. omVCCCLK3 L21 s.
VCCCLK2
1U_0402_6.3V6K
1 +1.0V_PRIM AB17

ic c i
@
c c i c c i cY18
c
VCCPRIM_1P0_AB17
tics.c
at cs. at cs. t s. t s.
CC67 VCCPRIM_1P0_Y18 +1.0V_APLL
RC154 1 @ 2 0_0402_5%
a+1.0V_PRIM a a
i i ic m tic m tic
AD17 N20

emat emat emat

+3VALW_DSW VCCCLK4 +1.0V_CLK4_F100OC
2 AD18 VCCDSW_3P3_AD17

c h m +1.0V_CLK4_F100OC
c h m +3V_PGPPB
c h m c hema
AJ17 VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17 VCCCLK5
L19 +1.0V_CLK5_F24NS he
c m
a
S he kSche kSche +3V_HDA
he
kScVCCHDA
AJ19 A10
kSche
+1.0V_CLK6_24TBT
c
VCCCLK6

ook ookS o o

1U_0201_6.3V6K
1
S S o kAJ16S VCCSPI STP@
bo k
RC190 1 @ 2 0_0603_5% near pin AF20, AN11 PRIMCORE_VID0
b b eboo AF20 VCCSRAM_1P0
+3V_SPI GPP_B0/CORE_VID0 AN13 PRIMCORE_VID1 T130

CC141
e o RC161 1 @ 2 0_0402_5% e oo AF21,T19, T20 te oo
T131 TP@

ot bo t ot b
GPP_B1/CORE_VID1
22U_0603_6.3V6M
22U_0603_6.3V6M

o o
+1.0V_PRIM

N teb b
2

1U_0402_6.3V6K
0.64A AF21
N te N te N te
1 1 1 VCCSRAM_1P0
CC137
CC136

@ @ T19
o o o T20 VCCSRAM_1P0 o

CC102
2 2 N 2 N N+3V_PRIM AJ21
VCCSRAM_1P0
N
VCCPRIM_3P3_AJ21
+1.0V_PRIM +1.0V_PRIM AK20
C VCCPRIM_1P0_AK20 C

+1.0V_PRIM N18

om om om om
+3V_PGPPC VCCAPLLEBB 15 OF 20
+RTCBATT

s .c m +1.0V_PRIM s .c m s .c m s .c m s.
c
o o o o
SKL-U_BGA1356
icImaxc: 2.57A 2 0_0402_5% ic c ic .c ic .c JRTC1
tics.c
at s. at s. t t
RC163 1 @ near pin N15, N16,
a s a s a
m tic m tic1 i@c ic ic

22U_0603_6.3V6M

22U_0603_6.3V6M
1U_0402_6.3V6K
N17,P15,P16 1 20mils
emat emat RTC Battery emat
1U_0402_6.3V6K 1 1
e e
2 1
h a a - +

ch m chem chem chem

CC81

CC82
CC80
1U_0402_6.3V6K

Schem
CC73
near pin AF18,
kSche S S S
2 2 2
CC76

okSch k h okSch
AF19,V20,V21
c ookSc
2

S o S
MAX. 8000mil

book book booCONN@

2 Per 543016_SKL_U_Y_PDG_0_9

VCCRTC does not exceed 3.2 V b

o k
e e e From PDG
e
ot o ot o ot bo ot SP07000H700
o
LOTES_AAA-BAT-054-K01

N teb +1.8V_PRIM eb b
CC7 Close UC1.AK19.
N t N e
Power Rail t Voltage +RTCBATT_R N e+RTCBATT
ot
+3V_1.8V_PGPPD
o o o
N
+1.0V_MPHYAON
N N +RTCVCC
N
1K_0402_5%
RC1721 @ 2 0_0402_5% RC2061 @ 2 0_0402_5% +CHGRTC 3.383V(MAX) RC19
DC1 15mils 15mils
1U_0402_6.3V6K

RC175 1 @ 2 0_0402_5% 1 15mils 2 2 1

@ BAT54C(VF) 240 mV 1
m m m m
CC103

3 +3VL
co co co
1
co
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c
1 CC7

s. om s. om s. om s.SC600000B00 s.
2

c c c
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c
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3P C/C_SOT-323

ic c
CC87

i c i c i c i c
at s. at cs. at s. at cs. at cs.
2
2
m tic m tic
Result : Pass
m t i i i
h e a e a +3V_PGPPE e a emat emat
Schem ch m ch m chem chem
kSche kSche S
okSch okSch
S
Sc o o
B B

S
o k 1 @ 2 0_0402_5% o k S
book booS3.
+1.0V_CLK6_24TBT

eb o
RC167

eboo e Kabylake No Support Deep

e
k
ot bo ot ot o ot bo
1U_0402_6.3V6K

N teb N teb
RC169 1 @ 2 0_0603_5%
N te N e
CC74

o1 o o +3VALW TO +3V_PRIM ot
N N N N
2
1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M
22U_0603_6.3V6M

1 1 1
@ @ @ @ I (Max) : 0.46 A(+3V_PRIM)
CC86

I (Max) : 0.1 A
CC75

CC139
CC138

+1.2V_VDDQ +5VALW
RDS(Typ) : 65 mohm
2 2 2 2 V drop : 0.03 V

1
1
+3V_PRIM_RTC

m m m RC910 m
co co co co
@
c
RC914 @

s. om s. om s. om s. om s.
100K_0402_5% 100K_0402_5%

i c c i c c
RC171 1 @ 2 0_0402_5%
i c c i c c ic .c
at cs. at c1 s. 1 t t t

2
. .
2
+1.0V_DTS
0.1U_0201_10V6K

a cs a s a s
1U_0402_6.3V6K

ema ti emat
i i
emat 2 @ D QC382 m tic m tic

1
1
CC78

hePCH_PWR_EN
a hema

1
1 @ D
CC77

RC911
h h h
Schem Sc em c c c
RC162 1 @ 2 0_0402_5% 12,26,35,49 SUSP# m 1K_0402_5% @RC912 26,35,51 m 2 QC3 1K_0402_5% @

kS he S e kS he
2 2 G G 2N7002K_SOT23
2N7002K_SOT23
c okSch ookSc okSch ookSc
S @ CC167 S @ CC165

2
3
2
3

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2 1
o+1.2V_VCCSFR_OC
k
2 1

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2
ot ot bo @ t

2
0.047U_0402_16V7K 0.047U_0402_16V7K
o o
N teb b b

G
N te +1.2V_VDDQ N 3 te 1 +3VALW N te 3 1

Follow 543016_SKL_U_Y_PDG_0_9 o o o o

0.1U_0201_10V6K

D
N N N QC381 N

0.1U_0402_25V6
1 1 1 1
1U_0402_6.3V6K
CC150

CC49

CC51
QC4

CC50
1U_0402_6.3V6K
S TR LP2301ALT1G 1P SOT-23-3 S TR LP2301ALT1G 1P SOT-23-3
+1.0V_PRIM +3V_PRIM +1.8V_PRIM
2 2 2 2
+3VS +3VS_PGPPA 2 1
A 1 2 A

o1m m om om
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

RC393 0_0805_5%
22U_0603_6.3V6M

RC141 0_0402_5%

@ c @ com .c m .c m c
1 1 1 1 1

s. om 2 0_0402_5% s. s.
CC112

CC114

CC115
CC111

@
CC113

@ @
CC116

s s
@

i c c
RC178 1 @
i c c o ic co ic co ic c
2
at2 cs.2 2 2 2
at cs+3VALW_DSW
. at cs. at cs. at cs.
i i m ti i m ti
emat emat emat
+3VALW

h h hemSecurity
a Classification Compal Secret Data ch m hema
Schem S c em c
kS he kS e 2015/12/31 Compal Electronics, Inc.
kS he
c
okSch Date h
2014/12/11 Title

Sc ookSc ookScINC. AND CONTAINS CONFIDENTIAL ookSc

RC173 1 @ 2 0_0603_5% Issued Date Deciphered

b o k b THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTYb

SKL-U(9/12)Power
b
e oo e oo e oTHIS oSHEET NOR THE INFORMATION IT CONTAINS e o
OF COMPAL ELECTRONICS, CONFIDENTIAL
Follow 543016_SKL_U_Y_PDG_0_9 Size Document Number Rev

ot ot ot CKL50ot bo
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
OF R&D
R&D

N teb N teb N teb

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER Custom v1.0

NMarcht 09,e
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, 2017 Sheet 13 of 59
5 o 4 o 3 o o 2 1
N N N N
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o o o o
N N N N
+VCC_GT_VR +VCC_GT
JU42A @
+VCC_CORE +VCC_CORE +VCC_CORE 1 2 +VCC_GT
1 2 UC1M SKL-U

m om m m
UC1L SKL-U Rev_0.53
JUMP_43X39_0805

co com co
Rev_0.53 CPU POWER 2 OF 4

.c m c
CPU POWER 1 OF 4

s. om A48.
s. om s.
JU22 @ N70
VCC_G32 G33 s s VCCGT
o o
A30 G32 1 2 N71
i c c A34 VCC_A30
i c .c
+VCC_GT 1 2
ic A53 VCCGT
A58.c
VCCGT
i c c ic .c
at cs. atG35 at cs at cs. t
R63
VCC_A34 VCC_G33 VCCGT VCCGT
G37 s a s
A39 R64

i A44 VCC_A39 VCC_G35

VCC_G37 i c JUMP_43X39_0805
i A62
VCCGT VCCGT
i m tic
emat em emat AA63 emat
R65
VCC_G38t G40
AK33 VCC_A44 A66 VCCGT VCCGT

hema
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h AK35 VCC_AK33
h a h
VCCGT VCCGT
h R67

Schem c m cKBLR m Sc em c
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68

kSche VCC_J30 e kS he
D
AK38 VCC_AK37 VCC_G42 J30 JU42A/JU42B for S AA66 VCCGT VCCGT D

k h okSch
R69

Sc o kSc ookSc
AK40 VCC_AK38 JU221 foro KBLU AA67 VCCGT VCCGT
AL33 VCC_AK40 o
J33 R70
o S o
VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37
AL40 e
b ok
VCC_AL33
VCC_AL37
VCC_J37 J40
VCC_J40 K33 b
e oo
AA70 VCCGT
AA71 VCCGT eboo
k
VCCGT
VCCGT
T62
b
e oo
t t ot ot
bo
U65
o o
VCC_AL40 VCC_K33 AC64 VCCGT VCCGT
AM32
N AM33 e
VCC_AM32
K35
VCC_K35 K37
N te b AC65 VCCGT
N teb
VCCGT
U68
N teb
t
U71
VCC_AM33 VCC_K37 AC66 VCCGT VCCGT
o o o o
AM35 K38 W63
AM37 VCC_AM35 VCC_K38 K40 AC67 VCCGT VCCGT
N N N N
W64
AM38 VCC_AM37 VCC_K40 K42 AC68 VCCGT VCCGT W65
VCC_AM38
G30 VCC_K42 K43 VCCGT VCCGT
VCC_G30 VCC_K43
Trace Length < 25 mils AC69
VCCGT VCCGT
W66
AC70 W67
K32 E32 AC71 VCCGT VCCGT W68
T123 TP@ RSVD_K32 VCC_SENSE VCCCORE_SENSE 52 VCCGT VCCGT
E33 J43 W69
VSS_SENSE VSSCORE_SENSE 52 VCCGT VCCGT
AK32 J45 W70
m om m m
T121 TP@ RSVD_AK32 VCCGT VCCGT
SOC_SVID_ALERT# B63 J46 W71 +VCC_GTX_VR

co co co
VIDALERT# VCCGT VCCGT
.c m c
AB62 A63 J48 Y62

s. om s. om s. om s.
VCCOPC_AB62 VIDSCK VR_SVID_CLK 52 VCCGT VCCGT
s
P62 VR_SVID_DATA D64 J50

i c c
V62 VCCOPC_P62
i c c o VIDSOUT
i c c
J52 VCCGT
i c JU42B @
c ic c
at cs. VCCSTG_G20t
a cs. at cs. at c+VCC_CORE
s. at cs.
VCCOPC_V62 +1.0VS_VCCIO VCCGT
For CPU2+3e SKU G20 J53
VCCGT
AK42
1 2
1 2
H63 J55 VCCGTX_AK42 AK43
i i i i m ti
emat emat emat emat
VCC_OPC_1P8_H63 J56 VCCGT VCCGTX_AK43 AK45

hema
VCCGT VCCGTX_AK45 JUMP_43X39_0805
h h h h
G61 J58 AK46
VCC_OPC_1P8_G61 VCCGT VCCGTX_AK46
c
S he m c m c m J60
Sc em
AK48
c
AE63 VCCOPC_SENSE kS he kSc1 h@e2 kS he
AC63 K48 VCCGT VCCGTX_AK48 AK50

okSch
VCCGT VCCGTX_AK50

Sc ookSc ookSc
K50 AK52

ookSRC920
VSSOPC_SENSE VCCGT VCCGTX_AK52
o
K52 AK53

ok
VCCGT VCCGTX_AK53
AE62
b
VCCEOPIO o
b o
0_0402_5% K53
VCCGTX_AK55 b
AK55
b
e oo
te e e
AG62 VCCEOPIO K55 VCCGT AK56

bo ot bo ot bo ot
VCCGT VCCGTX_AK56
o
K56 AK58

N teb
VCCGT VCCGTX_AK58
N AJ62 eVCCEOPIO_SENSE N te N e For CPU2+3e SKU
AL63 K58 AK60

ot VSSEOPIO_SENSE 12 OF 20 t
K60 VCCGT VCCGTX_AK60 AK70
o L62 VCCGT
o
VCCGTX_AK70 AL43 o
N N L63
L64
VCCGT
VCCGT NVCCGTX_AL43
VCCGTX_AL46
AL46
AL50
N
SKL-U_BGA1356 VCCGT VCCGTX_AL50
L65 AL53
L66 VCCGT VCCGTX_AL53 AL56
C L67 VCCGT VCCGTX_AL56 AL60 C
L68 VCCGT VCCGTX_AL60 AM48

om om om om
L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
.c m .c m .c m .c m s.
c
L71 VCCGT VCCGTX_AM52 AM53
s o s o s o
VCCGT VCCGTX_AM53
s o
ic c ic c ic c ic c ic c
M62 AM56
VCCGT VCCGTX_AM56

at s. at s. at s. at s. at cs.
N63 AM58
N64 VCCGT VCCGTX_AM58 AU58

m tic m tic m tic m tic i

VCCGT VCCGTX_AU58

emat
N66 AU63
e e e e
VCCGT VCCGTX_AU63

h a a a N67 BB57
a
ch m chem chem chem
VCCGT VCCGTX_BB57
SVID ALERT N69

Schem
BB66
VCCGT VCCGTX_BB66
+1.0V_VCCST
Place thekPUS he kSchVCCGT_SENSE kSchT219 S
okSch
J70 AK62VCCGTX_SENSE T155 TP@
c c
52 VCCGT_SENSE

S o
o kS
resistors close to CPU
o o S
VSSGT_SENSE J69 VCCGT_SENSE
o
VCCGTX_SENSE AL61 VSSGTX_SENSE
S
TP@

book book
52 VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
k
eboo e bTrace o e e
13 OF 20
t t t ot
1

oRC179 b o o Length < 25 mils

o o o
N teb N teb N teb
SKL-U_BGA1356

N t e
o 56_0402_5% o o o
N N N N
2

Intel 568813_KBL_R_U42_PDG_Addendum_Rev0p9
SOC_SVID_ALERT# 1 2 (To VR)
VR_ALERT# 52
RC180 220_0402_5%

m om m m
co .c m co co c
c s. om c s o c s. om c s. om s.
i c i c i c i c ic c
at cs. at s. at s. at s. at cs.
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m tic m tic m tic

Place the PU
ti i
SVID
mDATA
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Schem ch m ch m ch m chem
1

kSche kSche kSche S

okSch
Sc o o o
RC181
B B
o k S o k S o k S
book
100_0402_1%

eboo eboo eboo e

2

ot ot ot ot o
N teb N teb N teb N teb
o VR_SVID_DATA 52 (To VR)
o o o
N N N N

m m m m
co co co co c
c s. om cs. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
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h h h h hema
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kS he
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k k k
eboo eboo eboo b
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ot ot ot ot
N teb N teb N teb N teb
o o o o
N N N N

m m m m
A A

co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti m ti m ti
h emat h emat hema hema hema
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S he m c m c c c
kS he kS he Security Classification Compal Secret Data kS he Compal Electronics, Inc.okSche
Sc ookSc ookSc Issued Date 2014/05/19
oo
Deciphered Date S
k
c 2015/12/31 Title
o kS
b
e oo e b o THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OFe
b o INC. AND CONTAINS CONFIDENTIAL SKL-U(10/12)Power,SVIDeb o
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N teb INC. NEITHERb
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

N te e CONSENT OF COMPAL ELECTRONICS, INC.

NPRIOR WRITTEN C
CKL50 N te v1.0

ot
THIS SHEET NOR THE INFORMATION IT CONTAINS

o o Thursday, March 09, 2017o

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

N N N
Date:
N
Sheet 14 of 59
5 4 3 2 1
 ot o ot o ot o ot
5 4 3 2 1o

N teb N teb N teb N teb

o o o o
N N N N

m m m m
co co co co c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. a t s . a t s
emat
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c em h h hema hema
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GND 1 OF 3 GND 2 OF 3

ot o t ot o L18bo
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BA49
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NVSSte
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L20
AA2 AM21 AU10 BA6 G43 L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 VSS VSS
G45 L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 VSS VSS
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c
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VSS VSS VSS VSS VSS VSS
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BB30
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ot ot ot ot
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VSS VSS VSS VSS VSS VSS
N teb N teb N teb N teb
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AE64 VSS VSS AN32 VSS VSS VSS VSS
AW23 C1 J25 T17
AE65 o
VSS VSS AN33 o AW26 VSS VSS C25 o J28 VSS
o VSS T18
AE66 N
VSS
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VSS
VSS
AN35 N AW28 VSS
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C5 N J32 VSS
VSS
N VSS
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AE67 AN37 AW30 D10 J35 T21
AE68 VSS VSS AN38 VSS VSS VSS VSS
AW32 D11 J38 T4
AE69 VSS VSS AN40 VSS VSS VSS VSS
C AW34 D14 J42 U10 C
AF1 VSS VSS AN42 VSS VSS VSS VSS
AW36 D18 J8 U63
om om om om
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AW38 D22 K16 U64
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AF2 VSS VSS AP18 VSS VSS VSS VSS
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m tic m tic m tic m tic
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AG71 N te
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VSS VSS AP68 o AW64 VSS VSS D62 o VSS o VSS
AH6 N
VSS VSS AP70 N AW66 VSS VSS D66 N L16
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AW8 D69
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AY66 E11
AH67 VSS VSS AR16 VSS VSS
B10 E15 18 OF 20
AJ15 VSS VSS AR20 VSS VSS
m VSS VSS m B14
m E18
m
co co co co
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c
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AJ20 VSS VSS AR28 VSS VSS SKL-U_BGA1356
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ic c
AJ4 VSS VSS
i c
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c i c
B30
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AK11 VSS VSS AR42 VSS VSS
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m tic m tic m tic m tic
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i
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e
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h AK22 AR48 B53 E71
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ot ot ot ot
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N teb N teb N teb N teb
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AR53 B71 F22
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AR55 BA1
o
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o o
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AL28 N
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m AL4 AT23
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m F37 m
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VSS F68 F40
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F42
i VSS
i i i
emat emat emat emat
AL58 VSS AT56 VSS VSS BA41
hema
VSS VSS VSS
h AL64
h
AT58
h h
Schem Sc em Sc em17 OF 20 Sc em c
VSS VSS
16 OF 20
okSch okSch okSch kS he
Sc o k o k o k ookSc
eboo
SKL-U_BGA1356 eboo eboo b
e oo
ot ot ot ot
SKL-U_BGA1356

N teb N teb N teb N teb

o o o o
N N N N

A A
m m m m
co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti m ti m ti
h emat h emat Security Classification
he 2014/05/19a Compal Secret Data
hema Compal Electronics, Inc. chem a
c
S he m c m Issued Date Sc em c
kS he kSche kSche
Deciphered Date 2015/12/31 Title
k ch
Sc ookSc THIS SHEETo
o S DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND o
oCONTAINS S SKL-U(11/12)GND o
o kS
b ok
b SECRET eb
kDIVISION
eb o
OF ENGINEERING CONFIDENTIAL
e oo oo IT CONTAINS
Size Document Number Rev
te USED
AND TRADE INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT OF R&D
ot oBY tTHE ot bo
Custom v1.0
oDEPARTMENT oCOMPAL
EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR INFORMATION
CKL50
N teb N teMAY BEb N te
OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF b ELECTRONICS, INC.
N 2017 te
o o o Date: Thursday, March 09,
o Sheet 15 of 59
5
N 4
N 3
N 2
N 1
 ot o ot o ot o ot
5 4 3 2 1o

N teb N teb N teb N teb

o o o o
N N N N

m m m m
co co co co c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
emat
i
emat
i
emat
i m tic
h
c em h h h hema
S h Sc em Sc em Sc em c
kS he
okSch okSch okSch
D D

Sc o k o k o k ookSc
eboo UC1S SKL-U
eboo eboo b
e oo
ot ot ot ot
N teb N teb N teb N teb
Rev_0.53
RESERVED SIGNALS-1
o o o o
N T272 TP@ E68
CFG[0] N RSVD_TP_BB68
BB68 T156 TP@ N N
T273 TP@ B67 BB69 T157 TP@
D65 CFG[1] RSVD_TP_BB69
T274 TP@ CFG[2]
D67 AK13 T158 TP@
5 CFG3 CFG[3] RSVD_TP_AK13
CFG4 E70 AK12 T159 TP@
m m CFG[4] RSVD_TP_AK12
m m
co
C68
co co co
T275 TP@ CFG[5]
c
s. om s. om s. om s. om s.
T276 TP@ D68 BB2
CFG[6] RSVD_BB2
i c c T277
i c
TP@
c
C67
i c c
BA3
i c c ic c
at cs. at cs. at s. at cs. at cs.
F71 CFG[7] RSVD_BA3
T278 TP@ CFG[8]
i i m tic T162 TP@ m ti m ti
G69
emat emat
T279 TP@ CFG[9]
TP5eAT5 a hema hema
F70 AU5
c h c h T281 TP@ CFG[10] h
m m ScTP6em c c
T280 TP@ G68 T163 TP@
S he kS he
H70 CFG[11]
kS he kS he
okSch D5
T283 TP@ CFG[12]
Sc ookSc ookSc <DB> Add ball E3/C7 for KBL U/R Colay oo Sc
T282 TP@ G71
b
H69 CFG[13]
o k RSVD_D5 D4 k
eboo b b
T284 TP@
e oo e oo o
CFG[14]
G70 e
ot ot ot ot bo
T285 TP@ CFG[15] RSVD_D4 B2
N teb N teb N teb
UC1T SKL-U
T166 TP@
RSVD_B2 C2
N e
ot
T286 TP@ E63 T167 TP@
o o o
Rev_0.53
F63 CFG[16] RSVD_C2
SPARE
N T287 TP@ CFG[17] N RSVD_B3
B3 T170 TP@ N N
E66 A3 T252 TP@ AW69 F6
T288 TP@ CFG[18] RSVD_A3 RSVD_AW69 RSVD_F6
F66 AW68 E3 PCH_KBLR24_IN
T289 TP@ CFG[19] RSVD_AW68 RSVD_E3
C AW1 T174 TP@ AU56 C11 C
CFG_RCOMP E60 RSVD_AW1 AW48 RSVD_AU56 RSVD_C11 B11
om om m om
CFG_RCOMP RSVD_AW48 RSVD_B11
E1 T179oTP@ PCH_KBLR24_OUT C7 A11
.c m .c m c TP@ .c m c
RSVD_E1 E2 RSVD_C7 RSVD_A11
s 5 XDP_ITP_PMODE
XDP_ITP_PMODE E8
s s .T183 m s
U12
RSVD_U12 s.
RSVD_D12
D12
ic c o ic .c o
ITP_PMODE RSVD_E2
o o
tics.c tics.c tics.c
U11 C12
at s. at
RSVD_U11 RSVD_C12
AY2
s RSVD_BA4 BB4 a
BA4
a H11 T227 TP@ a F52
m tic ic RSVD_AY1 ic ic ic
RSVD_AY2 RSVD_H11 RSVD_F52
e
T192 TP@
e m tAY1 RSVD_BB4
emat emat emat
h a h a 20 OF 20

Schem T194 c
S TP@TP@
em
D1
D3 RSVD_D1 S cheA4
RSVD_A4 m T195 TP@
S chem S chem
okSch okS ch okSch okSch
T196 C4 T197 TP@ SKL-U_BGA1356

S c o
RSVD_D3 RSVD_C4

e b o kT198 TP@ K46

RSVD_K46
e book TP4
BB5
e book e book
ot o ot o ot o ot o
T200 TP@ K45
RSVD_K45
N teb N teb N teb N teb
A69 T201 TP@
AL25 RSVD_A69 B69
T203 TP@
o AL27 RSVD_AL25 o RSVD_B69 o PCH_KBLR24_IN o 1 0_0402_5% PCH_XTAL24R_IN
RX3 2 KBLR@
N RSVD_AL27 N AY3 RC182 1 N
2 0_0402_5% N
C71 RSVD_AY3
T205 TP@ RSVD_C71
T206 TP@ B70 D71 T207 TP@
RSVD_B70 RSVD_D71 C70
RSVD_C70 T208 TP@
F60
m T209 TP@ m RSVD_F60 m PCH_KBLR24_OUT RX4 2 KBLR@ 1 0_0402_5% m
co co T210o
co
C54 PCH_XTAL24R_OUT 1 KBLR@ 2
c TP@
TP@
c
s. om s. om s.T301o s. om s.
RSVD_C54
c
T211 TP@ A52
c c
D54
m c
RC915 1M_0402_5%

tics.c
RSVD_A52 RSVD_D54
i c ti s .c ti s.c ti s.c
at s. aBA70 TP1 BB3 a
AY4
a KBLR@
a
m tic tic RSVD_TP_BA68 ic ic ic
T213 TP@ RSVD_TP_BA70
e T300 TP@
e m BA68 emat emat
YC3
emat
a a TP2 24MHZ_18PF_XRCGB24M000F2P51R0
chem T217 c
h m J71 cheAY71
mPM_ZVM# 1 RC183 2 0_0402_5% chem chem
S S TP@ he J68 RSVD_J71 S S S
VSS_AY71
h kT218 okScZVM# h AR56 T225 TP@
ch Solution
k 2+3e 3
ok
1
h
Sc o c o Sc
B TP@ RSVD_J68 3 1 B
S
o kT220 TP@ ForS
booRSVD_TP_AW71
k boo k book
NC NC
e b o
F65
VSS_F65 e
AW71 T333 TP@
e PM_ZVM# e
ot o ot o RSVD_TP_AW70 ot bo PM_MSM# ot 4 o
T222 TP@ G65 AW70 T223 TP@ SJ10000UJ00

N teb N teb N teb

VSS_G65 2

CC168
27P_0402_50V8J

CC169
27P_0402_50V8J
F61 AP56 PM_MSM# e
N t+1.0V_VCCST KBLR@ KBLR@
o T224 TP@
E61 RSVD_F61 o MSM# C64 SKL_CNL# T230 TP@
o o
N T226 TP@ RSVD_E61 N PROC_SELECT# N N
19 OF 20 1 @ 2
RC184 100K_0402_5%
SKL-U_BGA1356
m m om
Follow
544669_SKL_U_DDR3L_RVP7_schematic_rev1.0 m
co co .c m co c
c s. om cs. om c s o c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
emat
i
emat
i
emat
i m tic
h h h h hema
Schem Sc em Sc em Sc em c
kS he
Sc CFG_RCOMP 1 2
o okSch o okSch o okSch ookSc
b k k k
te oo eboo eboo b
e oo
RC185 49.9_0402_1%

2 o b ot ot ot
N teb N teb N teb
CFG4 1
N e
RC193
ot
1K_0402_1%
o o o
N N N N

A A
m m m m
co Strap
Display Port Presence co co co c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at 1c:s.Disabled; No Physical Display Port at cs. at cs. at cs. at cs.
e m tiattached
CFG4 emat
i m ti m ti m ti
a he a hema Compal Electronics, Inc. chem a
to Embedded Display Port Security Classification Compal Secret Data
c h c h
S he m e m Issued Date Sc em c
kS kSche kSche
2014/05/19 Deciphered Date 2015/12/31 Title

Sc
0 : Enabled; An external Display chdevice is
Port
ookSPort THIS SHEETo
o k ch
S DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND o
oCONTAINSS SKL-U(12/12)RSVD o
o kS
ok kDIVISION
connected to the EmbeddedbDisplay b SECRET eb eb o
OF ENGINEERING CONFIDENTIAL
e oo oo IT CONTAINS
Size Document Number Rev
te oEXCEPT
AND TRADE INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT OF R&D
ot tTHE ot bo
Custom v1.0
oDEPARTMENT oCOMPAL
AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR INFORMATION
CKL50
N teb N teMAY BEb N te
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF bELECTRONICS, INC.
N 2017 te
o o o Date: Thursday, March 09,
o Sheet 16 of 59
5
N 4
N 3
N 2
N 1
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o o o o
REVERSE TYPE (5.2 mm)
CHANNEL-A N N

6
N

DDR_A_CLK0
DDR_A_CLK0
DDR_A_CLK#0
137
139
JDIMM1A
CK0(T)
STD
DQ0
8
7
N

DDR_A_D0
DDR_A_D4
m m m 6 DDR_A_CLK#0 CK0#(C)
mDDR_A_D3 DQ1

Interleaved Memory
DDR_A_CLK1 138 20
co co co co DDR_A_D7
6 DDR_A_CLK1 CK1(T) DQ2
DDR_A_CLK#1 140 21
c
s. om s. om s. om s. omDDR_A_D1 s.
6 DDR_A_CLK#1 CK1#(C) DQ3 4
ic
t s.c ic c ic c
DDR_A_CKE0 109
i c c
DDR_A_D5 DQ4 3
ic .c
Non-ECC DIMM mattics. 6 DDR_A_D[0..15] at cs. t . t
6 DDR_A_CKE0 CKE0 DQ5
a cs s
DDR_A_CKE1 DDR_A_D2
aJDIMM1 a
110 16
TOP: ic CONN i
6 DDR_A_CKE1 CKE1

ti
DDR_A_D6 DQ6 17
m tic
emat emat 149m DQ7
e he hema
DDR_A_CS#0 DDR_A_DQS0 13
h h a h
6 DDR_A_CS#0 DDR_A_CS#1 157 S0#a DQS0(T)
DDR_A_DQS#0 DDR_A_DQS0 6
11
c
S he m Sc em
6 DDR_A_D[16..31]
Sc em
6 DDR_A_CS#1
c m S1# DDR_A_DQS#0 6
DQS0#(C)
c
kSche kS he
D
162 D
+3VS +3VS +3VS S2#/C0

okSch okSch
165 28 DDR_A_D8

Sc ookSc
6 DDR_A_D[32..47]

oo
S3#/C1 DQ8 29 DDR_A_D12
o o S
DDR_A_ODT0 DQ9 41 DDR_A_D14
b ok k k
155

eb o b b
6 DDR_A_D[48..63] 6 DDR_A_ODT0
161 ODT0 DQ10 42
1

1
te e oo o
DDR_A_D10
e
DDR_A_ODT1

oSTDt bo ot ot bo
6 DDR_A_ODT1
o
RD1 ODT1 DQ11 24 DDR_A_D9
RD4 RD2
@ 0_0402_5% o
N teb N teb DDR_A_BG1
@ 0_0402_5% JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
e e
@ 0_0402_5%
N 6 DDR_A_BG0 DDR_A_D11N
ot VDD11 141 t
113 BG0 DQ13 38
o o o
6 DDR_A_BG1
111 DDR_A_BA0 150 BG1 DQ14 37 DDR_A_D15
+1.2V_VDDQ +1.2V_VDDQ
N 112 N N N
6 DDR_A_BA0
2

145 BA0 DQ15 34

2

VDD1

2
SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 142 DDR_A_BA1 DDR_A_DQS1
6 DDR_A_BA1 BA1 DQS1(T) 32 DDR_A_DQS1 6
117 VDD2 VDD12 147 DDR_A_DQS#1
DDR_A_DQS#1 6
118 VDD3 VDD13 148 DDR_A_MA0 144 DQS1#(C)
6 DDR_A_MA0 A0
1

1
VDD4 VDD14
1

123 153 DDR_A_MA1 133 50 DDR_A_D21

VDD5 VDD15 6 DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D17
RD3 RD5 RD6 124 154 132 49
VDD6 VDD16 6 DDR_A_MA2 DDR_A_MA3 A2 DQ17 DDR_A_D23
0_0402_5% 0_0402_5% 0_0402_5% 129 159 131 62
m m m m
VDD7 VDD17 6 DDR_A_MA3 DDR_A_MA4 A3 DQ18 DDR_A_D18
130 160 128 63

co co co co
VDD8 VDD18 6 DDR_A_MA4 A4 DQ19
c
135 163 DDR_A_MA5 126 46 DDR_A_D16

s. om s. om s. om s. om s.
6 DDR_A_MA5 A5 DQ20
2

+3V_PRIM_DA 2 VDD9 VDD19

2

136 DDR_A_MA6 127 45 DDR_A_D20

c c c c tics.c
VDD10 6 DDR_A_MA6 A6 DQ21
i i i i
DDR_A_MA7 DDR_A_D19
c c c c
122 58

at cs. at cs. at s. at cs.

6 DDR_A_MA7 DDR_A_MA8 A7 DQ22 DDR_A_D22
a
255 258 125 59
+0.6V_0.6VS 6 DDR_A_MA8
m tic m tic
VDDSPD VTT DDR_A_MA9 A8 DQ23 DDR_A_DQS2
ti THE BELOW RESISTORS CLOSE TO SODIMM em i m ti
121 55

emaALL
6 DDR_A_MA9 DDR_A_DQS2 6
a2 t+0.6V_DDR_VREFCA
DDR_A_MA10 A9 DQS2(T) DDR_A_DQS#2
e+2.5V hema hema

0.1U_0402_10V6K
PLACE 164 257 146 53

2.2U_0402_6.3V6M
h h
VREFCA VPP1 259
h a 6 DDR_A_MA10 DDR_A_MA11 120 A10_AP DDR_A_DQS#2 6
DQS2#(C)
c m c m c m c c
2 VPP2 6 DDR_A_MA11 A11
DDR_A_MA12 119 70 DDR_A_D25
S he kS he 1 kSche
6 DDR_A_MA12
kS he
DDR_A_MA13 A12
DQ24 71 DDR_A_D28
kS he

CD1

CD2
1 99 6 DDR_A_MA13 158

Sc SPD ADDRESS FOR CHANNEL A : ookSc ookSc ookSc

A13
VSS 103o
2 VSS VSS 102 DDR_A_MA14_WE# 151 DQ25 83 DDR_A_D30

VSS o S
1 VSS 6 DDR_A_MA14_WE# DDR_A_MA15_CAS# A14_WE#
DQ26 84 DDR_A_D31
9/8 Modify 156

ok
5
b
e oo
VSS
b 106 6
b
DDR_A_MA15_CAS#
e oo
DDR_A_MA16_RAS# A15_CAS#
DQ27 66 DDR_A_D24 b
e oo
teVSS
6 6 DDR_A_MA16_RAS# 152

WRITE ADDRESS: 0XA0 o t 9 VSS

VSS o
107
ot
A16_RAS#
DQ28 67 DDR_A_D29
ot
b VSS o b N teb DDR_A_PAR N teb
VSS DDR_A_ACT# 114 DQ29 79 DDR_A_D27
10 167

READ ADDRESS: 0XA1 Note N te VSS 168

PLACE NEAR TO PIN 14 VSS 6 DDR_A_ACT# ACT# DQ30 80 DDR_A_D26

VSS o o o
VSS 143 DQ31 76 DDR_A_DQS3
15 171
N N N N
VSS 172 6 DDR_A_PAR DDR_A_ALERT# PARITY DQS3(T) DDR_A_DQS#3 DDR_A_DQS3 6
18 116 74
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS 175
VSS
RD7 2 +1.2V_VDDQ
240_0402_1%
6 DDR_A_ALERT#
1 DIMM1_CHA_EVENT# 134 ALERT#
DDR_DRAMRST#_R
DQS3#(C)
108 EVENT#
DDR_A_DQS#3 6
174 DDR_A_D32
176
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181
6,18 DDR_DRAMRST#_R RESET# DQ32
DQ33
173
187
DDR_A_D37
DDR_A_D34 C

STRETCH GOAL IS 2133 MT/S 27 VSS VSS 184 PCH_SMBDATA 254 DQ34 186 DDR_A_D39

om om om om
VSS VSS 7,18,22 PCH_SMBDATA PCH_SMBCLK SDA DQ35 DDR_A_D36
30 185 7,18,22 PCH_SMBCLK 253 170
VSS VSS SCL DQ36 DDR_A_D33
.c m .c m .c m .c m c
31 188 169

s.
VSS VSS DQ37 DDR_A_D35
s s s s
35 189 SA2_CHA_DIM1 166 183
o
ic JDIMM1.257,259 ic c o ic c o ic .c o
tics.c
Layout Note: Layout Note: VSS VSS SA1_CHA_DIM1 260 SA2 DQ38 182 DDR_A_D38
.c
36 192

at s at s. at s. SA0at
VSS VSS SA0_CHA_DIM1 256 SA1 DQ39 DDR_A_DQS4
s
179
a
Place near Place near JDIMM1.258 39 193 DDR_A_DQS4 6
DQS4(T)
m tic m tic m tic ic ic
40 VSS VSS 196 177 DDR_A_DQS#4

e92m emat
DDR_A_DQS#4 6

at
VSS VSS DQS4#(C)
e
h m a e a
43
e a
197

chem
VSS
ch m che chem
44 VSS 201 195 DDR_A_D44

Sche m
47 VSS VSS 91 CB0_NC DQ40 194 DDR_A_D45

kSche
202
+0.6V_0.6VS kS S S
VSS VSS 101 CB1_NC DQ41 207 DDR_A_D42

c +2.5V 10uF*2
o c h
10uF*2
48
51
o
VSS VSS
205
206
okSch 105
CB2_NC DQ42 208 DDR_A_D43
okSch
S S1uF*1 o kS
book book book
1uF*2 52 VSS VSS 209 88 CB3_NC DQ43 191 DDR_A_D41

eb o
VSS VSS 87 CB4_NC DQ44 190 DDR_A_D40
e e e
56 210
For ECC DIMM
ot ot bo ot t
100 CB5_NC
o 1 o
DQ45 203

bo
57 VSS VSS 213 DDR_A_D46

DDR_A_DQS5 o
N teb N teb
VSS VSS 104 CB6_NC DQ46 204 DDR_A_D47
10U_0603_6.3V6M

1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

10U_0603_6.3V6M
0.1U_0402_25V6
1U_0402_6.3V6K

60 214
N te N teDDR_A_DQS5
1 1 1 1 1 1 1
@ESD@ 61 VSS VSS 217 97 CB7_NC DQ47 200
6
o o VSS
o 95 DQS8(T) DQS5(T) 198 DDR_A_DQS#5
o DDR_A_DQS#5 6
CD4

VSS
CD9
CD3

CD8
CD6

CD7
CC159
CD5

64 218
N N N N
VSS VSS DQS8#(C) DQS5#(C)
65 222
2 2 2 2 2 2 2 2 VSS VSS 216 DDR_A_D53
68 223
VSS VSS 12 DQ48 215 DDR_A_D48
69 226 +1.2V_VDDQ DM0#/DBI0#
VSS VSS 33 DQ49 228 DDR_A_D54
72 227 DM1#/DBI1#
VSS VSS 54 DQ50 229 DDR_A_D50
73 230 DM2#/DBI2#
VSS VSS 75 DQ51 211 DDR_A_D52
77 231
m m m m
VSS VSS 178 DM3#/DBI3# DQ52 DDR_A_D49
78 234 212

co co co co
VSS VSS DM4#/DBI4# DQ53 DDR_A_D55
c
81 235 199 224

s. om s. om s. om s. om s.
VSS VSS 220 DM5#/DBI5# DQ54 DDR_A_D51
82 238 225
c c c c ic c
VSS VSS DDR_DRAMRST#_R DM6#/DBI6# DQ55 DDR_A_DQS6
i i i i
241 221
c c c c
85 239 DDR_A_DQS6 6
at cs. at s. at cs. at cs. at cs.
VSS VSS 96 DM7#/DBI7# DQS6(T) DDR_A_DQS#6
86 243 DDR_A_DQS#6 6 219
DM8#/DBI8# DQS6#(C)
m tic
VSS VSS
tiCAP near JDIMM1. i i i
89 244

e m Note:
Layout
e 90 VSS
emat 2 VSS 247
emat emat
h a a
ch
VSS
chem chem chem
PLACE THE 164 93 VSS
CD10 248

Schem m VSS VSS

0.1U_0402_10V6K 237 DDR_A_D60
94

kSche
251
+3V_PRIM +3V_PRIM_DA VSS
S VSS
@ESD@ S DQ56 236 DDR_A_D57
S
okSch
9/8 Modify base on ESDk
o Sch okSch
98 1 252

Sc
Request DQ57 249 DDR_A_D59
o
B VSS VSS B

oRD32k S GND o
book book
1 2 DQ58 250 DDR_A_D62
b ok
262 261

eb o
GND DQ59 232 DDR_A_D56
e e e
0_0402_5%

ot bo ot ot bo ot
DQ60 233
o o
DDR_A_D61

N teb N teb
+0.6V_DDR_VREFCA 2.2uF*1 DQ61 245 DDR_A_D58
FOX_AS0A827-H2RB-7H
0.1uF*1 N te PLACE N NEAR tTOe SODIMM DQ62 246 DDR_A_D63

o o o DQ63 242
DDR_A_DQS#7 o
DDR_A_DQS7
DDR_A_DQS7 6
N N N N
CONN@ DQS7(T) 240
2 2 DQS7#(C) DDR_A_DQS#7 6

CD11 CD12
0.1U_0402_10V6K 1 2.2U_0402_6.3V6M Part Number:LTCX0069GA0 FOX_AS0A827-H2RB-7H
1
Part Value:S SOCKET FOX AS0A827-H2RB-7H 260P DDR4
+1.2V_VDDQ
m m m m
co co co co
CONN@
c
c s. om cs. om c s. om c s. om s.
i c i c i c DIMM Side CPU Side
i c ic .c
at cs. at cs. a t s . t
a cs . a t s
em ti Note: emat
i m tic m ti m tic

2
a hema 2 hema hema
Layout +0.6V_DDR_VREFCA +0.6V_VREFCA
h h
RD8

Schem Sc em c c c
Place near JDIMM1 1K_0402_1%

kS he kS he kSche
@

Sc okSch ookSc
CD13
ookSc ook
1
o k 20Smils
eboo b b b
0.1U_0402_10V6K
VREF traces should be at least
o o 1 RD9 2 oo
1

10uF*6 ot
e e te to
b ot bo ot bo 2_0402_1% wide with 20 mils spacing
o b other
1uF*8N e N te N te 2 N te
330uF*1 ot
+1.2V_VDDQ +1.2V_VDDQ 1 signals
o o o
2

N N +1.2V_VDDQ RD10 N CD14

CD15 N
0.022U_0402_25V7K
1K_0402_1% 0.1U_0402_10V6K 2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

2
1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1
1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1
1

1 1 1 1 1 1 1
CD95
CD21
CD93

CD22

A RD11 A
CD18

CD20
CD19
CD17
CD16

1
CD23

m m om m
CD31

CD94
CD30
CD25

CD26

CD29
CD96

CD24

24.9_0402_1%
CD27

CD28

co c2 o 2 co
C174 +
2
s. om
2 2 2 2 2 2 2
s. om
2
2 2 2 2 2
2
2 2 2
s .c m SF000006S00
s. om s.
c

1
i c c i c c
330U_2.5V_M
i c c o i c c ic c
at cs. at cs. at cs. at cs. at cs.
2

m ti emat
i
emat
i
emat
i m ti
c hema c h m c h mSecurity Classification Compal Secret Data c h m Compal Electronics, c hema
Inc.
S he kS he kS he kS e 2015/12/31 kSche
Date h
Sc ookSc ookSc ookScINC. AND CONTAINS CONFIDENTIAL
2015/08/03
ook
Issued Date Title
Title
Deciphered
P18-DDRIV_CHA: S
DIMM0
b
e oo b
e oo b
eNEITHER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
oSHEET
OF COMPAL ELECTRONICS,
e b o
ot ot otINC. b ot bo
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED
oTHIS
FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

N teb N teb
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, NOR THE INFORMATION IT CONTAINS v1.0
N tPRIOR
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT
eWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CKL50NMarcht09,e
5 o 4 o 3 o Date:
2
Thursday,
o 1
2017 Sheet 17 of 59

N N N N
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o o o o
CHANNEL-B N N N
STD (5.2 mm) N

TOP: JDIMM2 om
.c CONN
ms
Non-ECC DIMM co
m
s. om 6 DDR_B_D[0..15]
co
s. om
m Interleaved Memory 6 DDR_B_CLK0
6 DDR_B_CLK#0
CK0(T) m
DDR_B_CLK0

co
DDR_B_CLK#0

s.CK1#(C)
CK1(T) m
CK0#(C)
DDR_B_CLK1
DQ0 7
137
139
DQ1 20
138
JDIMM2A

DDR_B_D10
DDR_B_D11
STD 8

s.
DDR_B_D15

c
ic co c c c o ic .c
6 DDR_B_CLK1 DQ2 21
i c i c i DDR_B_CLK#1
c
140 DDR_B_D12

at cs. at cs. at cs. t . t

6 DDR_B_CLK#1 DQ3 4
s s
DDR_B_D14
6 DDR_B_D[16..31]
a a
m tic110 CKE0 m tic
+3VS +3VS +3VS DQ4
m ti i i
DDR_B_CKE0 109 3 DDR_B_D9

emat emat
6 DDR_B_CKE0 DQ5 16

he he hem
DDR_B_CKE1 DDR_B_D8
a h
6 DDR_B_D[32..47]
h
6 DDR_B_CKE1
a CKE1 DQ6 17 DDR_B_D13 a
Schem Sc em Schem c m c
DQ7 13

1
1

1
DDR_B_CS#0 149 DDR_B_DQS1
6 DDR_B_CS#1 kS he kS he 6
D 6 DDR_B_D[48..63] 6 DDR_B_CS#0 S0# DQS0(T) DDR_B_DQS1 6 D

@ 0_0402_5%k
o Sch ok
RD19 RD20 RD21 DDR_B_CS#1 157 11 DDR_B_DQS#1
c c ookSc ookSc
DDR_B_DQS#1
0_0402_5% 0_0402_5% JDIMM2B 162 S1# DQS0#(C)
S @
o k o S
k VDD11 141
STD 165 S2#/C0 28 DDR_B_D0

ebSA2_CHB_DIM2 b b b
S3#/C1 DQ8 29
t o +1.2V_VDDQ
t e 111
o +1.2V_VDDQ e oo e
DDR_B_D5
o
o o ot6 DDR_B_ODT0 t
DDR_B_D6 o
2

112 VDD1 DQ9 41

2
SA0_CHB_DIM2 2
SA1_CHB_DIM2 142 DDR_B_ODT0 155 DDR_B_D7
o o DQ11 24 o DDR_B_D4
N teb N teb b eb
117 VDD2 VDD12 147 DDR_B_ODT1 161 ODT0 DQ10 42
118 VDD3 VDD13 148
N t6eDDR_B_ODT1 ODT1
DQ12 N25 ot
o o 123 VDD4 VDD14 153
o 6 DDR_B_BG0
1

1
DDR_B_BG0 115 DDR_B_D1
RD23 N N N DQ14 N
RD22 RD24 124 VDD5 VDD15 154 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D3
6 DDR_B_BG1
0_0402_5% @ 0_0402_5% 129 VDD6
0_0402_5%
VDD16 159 DDR_B_BA0 150 BG1 37 DDR_B_D2
VDD7 VDD17 6 DDR_B_BA0 DDR_B_BA1 BA0 DQ15 DDR_B_DQS0
130 160 145 34
VDD8 VDD18 6 DDR_B_BA1 BA1 DQS1(T) DDR_B_DQS#0 DDR_B_DQS0 6
135 163 32 DDR_B_DQS#0 6
2

VDD9 VDD19 DQS1#(C)

2

2
+3V_PRIM_DB 136 DDR_B_MA0 144
VDD10 6 DDR_B_MA0 DDR_B_MA1 A0 DDR_B_D20
133 50
m m om m
6 DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D17
255 258 132 49

co co +0.6V_DDRB_VREFCA co
VDDSPD VTT +0.6V_0.6VS 6 DDR_B_MA2 A2 DQ17
.c m c
DDR_B_MA3 131 62 DDR_B_D19

s. om s.2 om s. om s.
6 DDR_B_MA3 A3 DQ18
s+2.5V
DDR_B_MA4 DDR_B_D22

0.1U_0402_10V6K
164 128 63

2.2U_0402_6.3V6M
257
c c c o c ic c
VREFCA VPP1 259 6 DDR_B_MA4 A4 DQ19
i i i i
DDR_B_MA5 DDR_B_D21
c c c c
126 46
PLACE ALLat at cs. at cs. at cs. at cs.
2
THE s .
BELOW RESISTORS CLOSE TO SODIMM VPP2 6
6
DDR_B_MA5
DDR_B_MA6
DDR_B_MA6 127 A5 DQ20 45 DDR_B_D16

ic
A6 DQ21 DDR_B_D18

CD61
DDR_B_MA7
i i i m ti

CD60
1 99 122 58

emat emat emat emat

6 DDR_B_MA7 A7 DQ22
2 VSS VSS 102 DDR_B_MA8 DDR_B_D23

hem
125 59
h h 1 1 5 VSS
h
VSS 103 6 DDR_B_MA8
h DDR_B_MA9 121 A8 DQ23 55 DDR_B_DQS2 a
c m c m c 106 m c m c
6 DDR_B_MA9 DDR_B_DQS2 6
SPD
S he ADDRESS FOR CHANNEL B : 6 VSS VSS DDR_B_MA10 146 A9 DQS2(T) 53 DDR_B_DQS#2

kS he he
S VSS kS he kSche
VSS VSS 6 DDR_B_MA10 A10_AP DQS2#(C) DDR_B_DQS#2 6
10 VSS k
9 107 DDR_B_MA11 120
6 DDR_B_MA11

Sc ookSc o ScVSS ookSc

A11
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN 14oVSS
167 6 DDR_B_MA12
DDR_B_MA12
DDR_B_MA13
119
158 A12
70
DQ24 71
DDR_B_D25
DDR_B_D24 o
o kS
15 VSS k
168
READ ADDRESS: 0XA3 b
e oo b o
VSS 171 6
b DDR_B_MA13 A13 DQ25 83
eb o
oo
DDR_B_MA14_WE# DDR_B_D31
e 18oVSS Modify te6 DDR_B_MA14_WE# 151
t t VSS VSS 172 9/8 DDR_B_MA15_CAS# 156 A14_WE# DQ26 84
t
DDR_B_D28o
DDR_B_D27
SA0 = 0; SA1 = 1; SA2N=o0. b o b o
N teb DQ28 67 o DDR_B_D29
b
VSS 6 DDR_B_MA15_CAS# DDR_B_MA16_RAS# A15_CAS# DQ27 66
19 175 152
e N te 22 6 DDR_B_MA16_RAS# A16_RAS#
DQ29 N
e
ot 1867 MT/S t
VSS VSS 176
DDR4 POR OPERATING SPEED: o 23 VSS VSS 180
o 6 DDR_B_ACT# DDR_B_ACT# 114
DQ30 80 o DDR_B_D26
79 DDR_B_D30
N N 26 VSS
27 VSS
VSS 181
VSS 184 N DDR_B_PAR 143
ACT#
DQ31 N DDR_B_DQS3
STRETCH GOAL IS 2133 MT/S 30 VSS
VSS
VSS
VSS
185
6 DDR_B_PAR
6 DDR_B_ALERT#
DDR_B_ALERT#
DIMM2_CHB_EVENT#
116 PARITY
ALERT#
DQS3(T)
DQS3#(C)
76
74 DDR_B_DQS#3 DDR_B_DQS3
DDR_B_DQS#3
6
6
31 188 RD25 2 1 134
C VSS VSS +1.2V_VDDQ 240_0402_1% DDR_DRAMRST#_R EVENT# DDR_B_D37 C
35 189 6,17 DDR_DRAMRST#_R 108 174
VSS VSS RESET# DQ32 DDR_B_D33
Layout Note: Layout Note: 36 192 173
m
Place near JDIMM2.257,259
om
Place near JDIMM2.258 39 VSS
om
VSS 193 m DQ33 187 DDR_B_D35

com com DQ35

VSS VSS PCH_SMBDATA DQ34 DDR_B_D38
.c m .c m c
40 196 254 186

s. 253 .SDA
s.
VSS VSS 7,17,22 PCH_SMBDATA PCH_SMBCLK DDR_B_D32
s 43
s 197
s 170

ic . c o o o o
7,17,22 PCH_SMBCLK
ic c ic c SA2_CHB_DIM2 ic166 c
tics.c
VSS VSS SCL DQ36 169 DDR_B_D36
44 201
t
a cs at s. at s.
47 VSS VSS 202
a t s . SA2 DQ37
DQ38
183
a
DDR_B_D34

m tic m tic SA0_CHB_DIM2 ic256 SA1 ic

VSS VSS SA1_CHB_DIM2 DDR_B_D39
i
48 205 260 182
+2.5Vm
at emat DDR_B_DQS4 m
e 66 at
10uF*2 +0.6V_0.6VS 10uF*2 VSS VSS DQ39 DDR_B_DQS4
e e e 51 206 179
h 1uF*1h a a VSS SA0 DQS4(T)
ch m chem chem
52 VSS 177 DDR_B_DQS#4
1uF*2 209

Schem Sc em
VSS VSS DQS4#(C) DDR_B_DQS#4
56

kSche
210
VSS VSS
S DDR_B_D44 S
1 k 1 ch
okSch okSch
57 213 92 195
c 91 CB0_NC DQ40 194
o o
VSS VSS DDR_B_D45
10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M

1 1 1 1 60 214
S o kS o kS book DDR_B_D47o
1 VSS VSS 101 CB1_NC DQ41 207 DDR_B_D42
b ok
61 217

eb eb o
VSS VSS 105 CB2_NC DQ42 208
CD63

CD64

CD66

CD67
CD65

o
CD68

e e
CD62

64 218

ot b ot bo ot For t
88 CB3_NC DQ43 191
2 o 2 o ECC DIMM DDR_B_D41o
65 VSS VSS 222 DDR_B_D40

DQ45 203 o DDR_B_D43

N teb eb
2 2 2 2 2 68 VSS VSS 223 87 CB4_NC DQ44 190
N te N te 69 VSS VSS 226 100 CB5_NC
DQ46 N t
o o 72 VSS VSS 227 o 104 CB6_NC
DQ47 200o DDR_B_DQS5
204 DDR_B_D46
N N 73
77
VSS
VSS
VSS
VSS
230
231
N 97 CB7_NC
95 DQS8(T) DQS5(T) N
198 DDR_B_DQS#5 DDR_B_DQS5 6
DDR_B_DQS#5 6
VSS VSS DQS8#(C) DQS5#(C)
78 234
81 VSS VSS 235 216 DDR_B_D48
VSS VSS 12 DQ48 215 DDR_B_D53
82 238 +1.2V_VDDQ DM0#/DBI0#
VSS VSS 33 DQ49 228 DDR_B_D54
85 239
m m m m
VSS VSS 54 DM1#/DBI1# DQ50 DDR_B_D51
86 243 229

co co co co
VSS VSS DM2#/DBI2# DQ51 DDR_B_D52
c
89 244 75 211

s. om s. om s. om DDR_DRAMRST#_R s. om s.
VSS VSS 178 DM3#/DBI3# DQ52 DDR_B_D49
90 247 212
c c c c ic c
VSS VSS DM4#/DBI4# DQ53 DDR_B_D55
i i i i
199 224
c c c c
93 248

atCAP s. at s. at s. at s. at cs.
Layout Note: VSS VSS 220 DM5#/DBI5# DQ54 DDR_B_D50
94 251 225
DM6#/DBI6# DQ55
ic WITHIN 200 MILS m tic m tic m tic
VSS VSS 241 DDR_B_DQS6
PLACE THE 221
i
98 252
m emat
DM7#/DBI7# DDR_B_DQS6 6
THE t
VSS VSS 96 DQS6(T) DDR_B_DQS#6
e e e e
2 219
FROM
a JDIMM2
a a a DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 6
h ch m
262
h m 261 CD92
ch m chem
Schem c
GND GND 0.1U_0402_10V6K

kSche kSche kSche S

@ESD@

Sc okSch
1 DDR_B_D60
o o o
B B
FOX_AS0A827-H2SB-7H 237
o k S o k S o k S DQ56 236
DDR_B_D58o
DDR_B_D57
+0.6V_DDRB_VREFCA 2.2uF*1
eboo eb CONN@o eboo
DQ57 249
e b ok
ot ot bo ot t
DQ58 250
DDR_B_D56o
DDR_B_D62
0.1uF*1
DQ60 233 o DDR_B_D61
N teb N teb eb
DQ59 232
2 2
Part e
N tNumber:LTCX0069FA0 PLACE NEAR TO SODIMM DQ61 N tDDR_B_D59
o o Value:S SOCKET FOX AS0A827-H2SB-7H 260P DDR4 o
Part DQ62 246o DDR_B_D63
245
CD69
0.1U_0402_10V6K
CD70
2.2U_0402_6.3V6M
N N N DQ63 N
242 DDR_B_DQS7
DDR_B_DQS7 6
1 1 +1.2V_VDDQ DQS7(T) 240 DDR_B_DQS#7
+3V_PRIM +3V_PRIM_DB DQS7#(C) DDR_B_DQS#7 6

1 2
m m RD33 0_0402_5%
m om
FOX_AS0A827-H2SB-7H

co co co .c m c
c s. om cs. om c s. om c sCONN@o s.
i c i c i c i c ic .c
at cNote:
s. at cs. at cCD71
s. DIMM Side t
a cs . a t s
2
Layout
emat
i near JDIMM2
Place
emat
i i
ema@t 1 0.1U_0402_10V6K mCPU
ti Side m tic

2
h h h RD26
hema +0.6V_B_VREFDQ hema
Schem Sc em Sc em 1K_0402_1% +0.6V_DDRB_VREFCA
kS he
c c
kS he
Sc o okSch o okSch ookSc ookSc
1
b k k
eboo b b
10uF*6
+1.2V_VDDQ 1uF*8
330uF*1o
te oo +1.2V_VDDQ
ot ot
e oo1 RD27 2 e oo
bet atbleast
VREF traces should o
N teb N teb N teb
2_0402_1% 20 mils
o o o
wide with 20 mils
o te
N spacing to other
2

N N N N
2
2 1 signals
10U_0603_6.3V6M
10U_0603_6.3V6M

RD28
10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

CD72
1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1 CD81 1K_0402_1%
1U_0402_6.3V6K

1 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 0.1U_0402_10V6K CD82
CD79
CD73

CD75

1
CD74

CD80
CD76

CD78
CD77

0.1U_0402_10V6K 0.022U_0402_25V7K
CD86
CD85

CD90

1
CD83

CD84

2
CD88

CD89
CD87

A A
2 2

2
2

om om m m
2 2 2 2 2 2 2 2 2 2 2
2 2

co co
RD29

s .c m s.c m s. om
24.9_0402_1%
s. om s.
c
ic co ic co c c ic c
@
@
i c i c
at s. at s. at cs. at cs. at cs.

1
e m tic e m tic emat
i
emat
i m ti
h a
ch m
a h h hema
Schem c mSecurity Classification Compal Secret Data c m Compal Electronics, cInc.
c kSche kS he kS Date h
e 2015/12/31 kSche
ookSc ookScINC. AND CONTAINS CONFIDENTIAL
2015/08/03
o ook
Issued Date Title
Title
Deciphered
S o kS P19-DDRIV_CHB: S
DIMM0
eb o b
e oo b
eNEITHER oSHEET e b o
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,

ot bo ot otINC. b ot bo
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED
oTHIS
FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

N teb
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, NOR THE INFORMATION IT CONTAINS v1.0
N te N tPRIOR
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT
eWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CKL50NMarcht09,e
5 o 4 o 3 o 2
Date: Thursday,
o 2017
1
Sheet 18 of 59

N N N N
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o o o o
N N N N
5,6,7,9,10,11,13,17,18,20,21,22,23,24,26,28,32,33,34,35,36,37,38,52,56 +3VS +3VS

m m m m
co co co co c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
emat
i
emat
i
emat
i m tic
D h h h h hema D

Schem +3VS +3VS_SSD Sc em Sc em Sc em c

S he
Sc
@
o okSch o okSch o okSch k
ookS c
k k k
eboo eboo eboo eb o
JSSD33

ot b ot ot ot bo
1 2
N teb N teb
1 2
N e 1 1 N te
ot

10U_0603_6.3V6M

CS29

.1U_0402_16V7K

CS30
JUMP_43X79 CONN@
o o o
N N JSSD N N
2 SSD@ 2 SSD@
1 2 +3VS_SSD
3 1_CONFIG_3 3.3V_2 4
m m 3_GND m 3.3V_4 m
co co co NA_6 co
5 6
5_NA c
s. om s. om s. om s. om s.
7 8
i c c i c c 9
i c
7_NA
c
NA_8 10
i c
T350@
c ic c
at cs. at cs. at cs. at cs. at cs.
11 9_NA DAS# _10
i i i
11_NA
i m ti
h emat h emat e
h ma
m t
12 hemat hema
c
S he m c m 13 c NA_20 c m c
kS he k15Sc he kS he kS he
14
21_CONFIG_0 NA_22
Sc ookSc ookSc ookSc
16
oo S
17 23_NA NA_24 18
b b k 25_NA NA_26 b b
e oo e oo 21 27_GND
19 20 e oo e oo
ot t ot ot
NA_28
o
N teb N teb N teb N teb
22
23 29_NA NA_30 24
C
o o 25 31_NA NA_32 26 o o C
N N 27 33_GND NA_34 28 N N
29 35_NA NA_36 30 DEVSLP2_R RSD1 1 SSD@ 2 0_0402_5% DEVSLP2 11
31 37_NA DEVSLP_38 32
SSD@ CS25 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P2 33 39_GND NA_40 34
11 SATA_PRX_DTX_P2
35 41_SATA-B+/PETn0 NA_42
om m m om

1
SSD@ CS26 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N2 36
co o
11 SATA_PRX_DTX_N2
37 43_SATA-B-/PETp0 NA_44
s.c m s. om 39 45_GND s .c NA_46
m
38
s .c m s.
c
ic c o 11 SATA_PTX_DRX_N2
2c
2 0.01U_0402_16V7K
i c
SSD@ CS27 1 SATA_PTX_C_DRX_N2
41 47_SATA-A-/PERn0ti
o
c .c NA_48 40 @ R2
ic c o ic c
at s. t
a cs. at s. at cs.
0.01U_0402_16V7K SSD@ CS28 1 SATA_PTX_C_DRX_P2 42 10K_0402_5%
11 SATA_PTX_DRX_P2 a s
m tic m tic
43 49_SATA-A+/PERp0
m tic
NA_50
i i
emat emat
44
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2
a 45 51_GND a
NA_52 46 a
h h h m
53_NA NA_54
ch m chem
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S S 55_NAe MFG1_56
kSche S
okSch k49 h okSch
50
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57_GND
o k53S 59_Notch M
MFG2 _58 o
o kS
book book
52
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Notch M_60 54
e e
ot o ot bo ot bo ot o
Notch M_62 56
N teb N teb
63_Notch M Notch M_64
N te 57
65_Notch M Notch M_66
58 N te
o o 59 60 o o
N N 61 67_NA SUSCLK _68 62 N N
63 69_CONFIG_1 3.3V_70 64
65 71_GND 3.3V_72 66
67 73_GND 3.3V_74
75_CONFIG_2
m m m 68
m
co co o co
GND 69
B
c m c
s. om s. om s. oNC_70 s. om s.
B
GND 70
ic c i c c i c c NC_71 i c c ic .c
at s. at s. at s. at s. t
71
a cs
e m tic e m tic emat
ic
FOX_AS0BC56-S00PB-7H
e m tic emat
i
h a a a
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kSche S
okSch kSche S
okSch
Sc o
o k S o S
eboo e book o k
eboo e book
ot ot o ot ot o
N teb N teb N teb N teb
o o o o
N N N N

m m m m
co co co co c
c s. om cs. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. a t s . a t s . a t s
emat
i
emat
i m tic m tic m tic
h
c em h hema hema hema
S h Sc em c
kS he
c
kS he
c
kS he
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A A
o k
eboo b
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b
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ot Securityo ot ot
N teb b
N Classification
te N teb
Compal Secret Data N teb Inc.
Compal Electronics,
o o 2013/3/1 o 2015/3/1 Title o
N NIssued Date DecipheredN
Date
M.2 SSD N
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
CKL50
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS v1.0
m m m
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. m
co com co Date: co Thursday, March 09, 2017 Sheet 19 of 59
c
s. o5 m 4 s.
o s. om s. m s.
c c c ic co ic c
3 2 1
i c i c i c
at cs. at cs. at cs. at cs. at cs.
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h emat h emat h emat hema hema
c
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kS he kS he kS he kS he
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b
e oo b
e oo b
e oo b
e oo
ot ot ot ot
N teb N teb N teb N teb
o o o o
N N N N
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o eDP Power o o +3VS o
N N N N
+3VS 5,6,7,9,10,11,13,17,18,19,21,22,23,24,26,28,32,33,34,35,36,37,38,52,56 +3VS
UG1 +19VB
38,47,48,49,50,53,55,56 +19VB
1 +LCDVDD
5 VOUT
VIN W=60mils 7,13,23,26,27,32,35,48,49,51 +3VALW +3VALW
INVPWR_B+ +19VB

0.1U_0402_16V7K
4.7U_0402_6.3V6M
2 SM010014520 3000ma W=60mils
GND
m m m m

0.1U_0402_16V7K
1U_0402_6.3V4Z 1 @ 2 4 1 1 220ohm@100mhz
0_0402_5% EN
co co co com
1 1 R172 DCR 0.04
c
s. om s. om s. om s. oDISPOFF# s.
3 CG2 L1 1
CG3 2 0_0805_5%
CG4 CG1 /OC SD002000080
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ic c i c c ic .c
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s. t
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<EC> 26 EC_BKOFF#
s
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a
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1
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h h10K_0402_5%

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2 2
5 ENVDD_CPU
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R259 0_0402_5%

1
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Camera

2
m m m m
co co co coEDP_HPD_PANEL c
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ic 2 D7 m tic ic m tic
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1 2

c h m c 1
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EDP_CPU_AUX
o o o 5 EDP_CPU_AUX_C
o
N
LA1/LA2 closed to Aduio codec 1 @ 2
N N 5 EDP_CPU_AUX#_C
CT101 1 2 .1U_0402_16V7K N
EDP_CPU_AUX#

R5196 0_0603_5%
SM01000DX00 SD013000080 CT98 1 2 .1U_0402_16V7K EDP_CPU_LANE_P0
D_MIC_CLK D_MIC_L_CLK 5 EDP_CPU_LANE_P0_C
C 1 2
24 D_MIC_CLK
LA1 EMI@ FBMA-L10-160808-301LMT_2P
<CPU> CT97 1 2 .1U_0402_16V7K EDP_CPU_LANE_N0
C

5 EDP_CPU_LANE_N0_C

om om om om
FG3 +3VS_CAMERA
D_MIC_DATA 1 @ 2 D_MIC_L_DATA
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c
24 D_MIC_DATA 3
R175 0_0402_5% CT103 1 2 .1U_0402_16V7K
s o s o
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5 EDP_CPU_LANE_P1_C
s o
ic . c ic c 1 IN tics.c CT100 1 ic
tics.c
1 1
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a cs C5221 C5222
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emat
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m tic
4.7U_0402_6.3V6M
m tic m tic
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GND 2 2 SE00000SO00
h chem
Schem S S c e S c e S c e
SA000080300
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okSch okSch k h okSch
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C594 2 1 220P_0402_50V7KDISPOFF#
N 12 t 1 e
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o o o EDP_CPU_LANE_N1
o3 2
N N N EDP_CPU_LANE_P0 N 4 34
EDP_CPU_LANE_N0 5

Touch Screen
6 5
EDP_CPU_AUX 7 6
EDP_CPU_AUX# 8 7
1 @ 2
8
m om m m
R5175 0_0402_5% +LCDVDD 9
9

co co co
10

.c m10 c
EDP_HPD_PANEL 10

s. om s. om s. om s.
L13 11
s
USB20_P6_R 1 @ 2 TS_GPIO 12 11
1 @ 2
i c c
11 USB20_P6
i
1
c o 2 TS_GPIO_CPU
i c i c 12
ic c
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@ESD@ R260 0_0402_5% Touch screen USB20_P6_R 13

at s. a3 t s at s. at s. at cs.
USB20_N6_R 14 13
D6
2 ic m3 tic m tic m tic
USB20_N6_R DISPOFF# 14
i
4 15
m t emat
11 USB20_N6 26 TS_GPIO_EC 1 @ 2
USB20_P6_R 4 INVTPWM 15
e e e e
R5187 0_0402_5% 16
a
hUSB20_N6_R 3 h m a a a 16

ch m chem chem
1 WCM-2012-900T_4P TS_GPIO 17

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kSR173he kSche kSINVPWR_B+ S

1 @ 2 19 18
h okSch
19

Sc ookSc o o c
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B PESD5V0U2BT_SOT23-3 B
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20

b o k book +5VS_TOUCH
21
book
eboo
SCA00000U10 +3VALW 22 21

e o e e 22

ot o ot ot o ot GND
b36o
+3VS_TOUCH 23
23

N teb N teb N teb

24
1

N te 25 24
+3VS_CAMERA 25
Touch Screen Power USB20_N5_R
o o@ RTS5 o o GND
26 35
+3VS_TOUCH USB20_P5_R GND 34 26
Camera
N N N N
27
28 33 27
100K_0402_5%
RTS7 1 @ 2 0_0402_5% D_MIC_L_CLK GND 32
29 28
2

D_MIC_L_DATA 30 29 GND 31
30 GND
1

ACES_50203-03001-002
1

D SP010023710
@ RTS4 @

om m m m
FG4 @ 2 QTS4

co@ CTS8 co co
TOUCH_ON 26 1K_0402_5%

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c o +3VS_TOUCH_IN ic c c ic .c
2

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i c c
2
i c i c
at s. at s. 0.047U_0402_16V7K 20mil at cs. at cs. t
@ 1 +3VS_TOUCH_IN
a s
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IN
4.7U_0402_6.3V6Mic 20mil ic @ m tic
CTS3
i i
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1
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S TR LP2301ALT1G 1P SOT-23-3
o k o k o k
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eb o eboo b
e oo
ot ot RTS3bo ot ot
1

RTS6 1 @ 2 0_0402_5%
+5VS_TOUCH
N teb N @te N teb N teb
2N
o o 100K_0402_5% o o
RTS8 1 @ 0_0402_5% N N N
2
1

TS@ RTS1 @D
FG2 @ TOUCH_ON
1K_0402_5% QTS1 2

om o@m m m
A G A
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co co
3 CTS2
.c m .c 1m2 c
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s. om s. om s.
2

1
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c s o
1 +5VS_TOUCH_IN +5VS_TOUCH_IN
c s o c c
i i i i tics.c
IN
c c c c
2

at c at cs t s. t s.
CTS6
4.7U_0402_6.3V6M
2 s
. 2 20mil @.
0.047U_0402_16V7K
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a a a
G

m tic m tic m tic

GND
m ti em ti
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hema 1 a hema hema hema

D

c
SA000080300
c hTS@CTS1m c c c
S he he kS he Security Classification Compal Secret Data kS he kS he
G5250Q1T73U SOT-23 3P POWER SWITCH
kS
QTS2
0.1U_0402_16V4Z S TR LP2301ALT1G 1P SOT-23-3
Compal Electronics, Inc.
Sc ookSc 2
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k
c 2015/07/08 Title
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b b b b
Deciphered
e oo e oo o INC. AND CONTAINS CONFIDENTIAL e oo
RTS2 1 TS@ 2 0_0402_5%
e LVDS Connector
ot ot otFROMTHIS THEo ot
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,

N teb N teb DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHERb

LA-C707PN teb
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
NPRIOR t e CONSENTSHEET NOR THE INFORMATION IT CONTAINS v1.0

o o o Thursday, March 09, 2017o

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT WRITTEN OF COMPAL ELECTRONICS, INC.

N N N N
Date: Sheet 20 of 59
5 4 3 2 1
 ot o ot o ot o ot
5 4 3 2 1o

N teb N teb N teb N teb

o o o o
N N N +3VS N
PCH_DPB_P0 0.1U_0402_16V7K 1 2 CG27 PCH_DPB_P0_C +HDMI_CRT_5V
5 PCH_DPB_P0 22 +HDMI_CRT_5V
PCH_DPB_N0 0.1U_0402_16V7K 1 2 CG28 PCH_DPB_N0_C
5 PCH_DPB_N0
5,6,7,9,10,11,13,17,18,19,20,22,23,24,26,28,32,33,34,35,36,37,38,52,56 +3VS +3VS
m PCH_DPB_P1 0.1U_0402_16V7K 1 2 CG29 m PCH_DPB_P1_C m m
co co co co +5VS
5 PCH_DPB_P1
PCH_DPB_N1 0.1U_0402_16V7K 1 PCH_DPB_N1_C
c
s. om s. om s. om s. om s.
<CPU> 2 CG30 +5VS
5 PCH_DPB_N1 20,24,26,27,30,34,35,52,53,56

1
RG47
ic .c ic c i c c i c c ic .c
a55t PCH_DPB_P2 at s. at cs. t . t
PCH_DPB_P2 0.1U_0402_16V7K 1 2 CG31 PCH_DPB_P2_C
cs
iPCH_DPB_N2
PCH_DPB_N2 0.1U_0402_16V7K 1 2
m tic
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i
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m tic
s a
m tic
s
h emat 2he
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2
PCH_DPB_P3 0.1U_0402_16V7K 1 PCH_DPB_P3_C
c em 55 PCH_DPB_P3 Sc2 e m Sc em c c

2
S kS6 he kS he
PCH_DPB_N3 0.1U_0402_16V7K 1 CG34 PCH_DPB_N3_C
h okSch okSch
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20K_0402_5%
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1

5
6
7
8
5
6
7
8
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N teb N teb N tebSB00000I700 e

1
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220P_0402_50V7K ot
o oQG1B SB00000I700 o 5V Level RG56
N N N 2
N
2N7002KDW_SOT363-6

4
3
2
1
4
3
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1
3 4

2
RP3 RP4
470_0804_8P4R_5% 470_0804_8P4R_5%
m m m m
co co co co c

5
c s. om c s. om +3VS
c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
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b
e oo e b oD21 b
e oo b
e oo
ot ot bo1 1 ot ot
N teb N teb N teb
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PCH_DPB_P3_C N RG59 1 EMI@ 2 8.2_0402_1% HDMI_R_CK+ N N N
HDMI_R_D0+ 4 4 7 7 HDMI_R_D0+
2
C HDMI_R_D0- 5 5 6 6 HDMI_R_D0- C

5
EMI@ CG71
om om
0.82P_0402_50V8 3 3
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1

s.
PCH_DDPB_CLK 4 3 HDMI_SCLK
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ic c ic c ic c ic c ic c
PCH_DPB_N3_C RG60 1 EMI@ 2 8.2_0402_1% HDMI_R_CK- 8

at s. at s. at s. at s. QG2B SB00000I700
at cs.
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Schem
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1

PCH_DDPB_DAT 1 6 HDMI_SDATA
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HDMI_R_D1- 1 1 0 9 HDMI_R_D1-
5
o
PCH_DDPB_DAT
o
N N N N QG2A SB00000I700
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PCH_DPB_P1_C RG65 1 EMI@ 2 8.2_0402_1% HDMI_R_D1+
HDMI_R_D2- 4 4 7 7 HDMI_R_D2-
m m m m
co co co co
2

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c
c s. om EMI@
c s. om
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c s. om c s. om s.
i c i c ti s.c ti s.c tics.c
3 3
at cs. at cs.
0.82P_0402_50V8
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+3VS
a a a
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8.2_0402_1%m HDMI_R_D1- ic m tic ic
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chem PCH_DPB_P2_C chem HDMI_R_D2+ chem ch chem
1

S
2
e m
7 HDMI_SDATA
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RG70 1 EMI@ k h S
k ch S S
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Sc o c o
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5 PCH_DDPB_DAT
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book book boo2.2K_0804_8P4R_5% book
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e e e e
ot ot ot HDMI Conn.ot bo
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o o o
N teb N teb N teb
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@ESD@ DG1
PCH_DPB_N2_C N RG66 1 EMI@ 2 8.2_0402_1% HDMI_R_D2- N
HP_DETECT 1 1 0 9 HP_DETECT
N CONN@ N
JHDMI1
HDMI_SDATA 2 2 9 8 HDMI_SDATA HP_DETECT 19
18 HP_DET
+HDMI_CRT_5V +5V
m m HDMI_SCLK 4 4 7 7
mHDMI_SCLK
m 17
co co co co SDA
DDC/CEC_GNDHDMI_SDATA
c
16

c s. om cs. om 5 5 6 6
c s. om c s. omSCL HDMI_SCLK
s. 15
i c i c i c i c ic .c
at cs. at cs. at cs. t t 14
3 3 a cs . Reserved
a s 13

emat
i
emat
i
emat
i m i CEC
m tic
at
HDMI_R_CK- 20 12
hem hema
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h h 8
h @ @ 11
Schem Sc em Sc em c c
CK_shield GND 22

10P_0402_50V8J
HDMI_R_CK+
kS he HDMI_R_D0- kS he
W=40mils

10P_0402_50V8J
1 1 10

okSch +HDMI_CRT_5V okSch

IP4292CZ10-TB CM27 CK+ GND 23 9
CM26
Sc ookSc ookSc
FG1 D0- GND
o k o k
8
eb o 3 eboo b b
HDMI_R_D0+ D0_shield
e oo o 7
e
ot bo ot ot ot bo
2 2 HDMI_R_D1- D0+ 6
N teb N teb
OUT D1-
N te HDMI_R_D1+ D1_shield N te
5
+5VS 1
oIN o o D1+ o 4
N 2
1 N N HDMI_R_D2-
D2- N 3
2
GND HDMI_R_D2+ 1 D2_shield
CG46 D2+
A 0.1U_0402_16V7K 2 YUQIU_HD074-F19M1BR-A A
m AP2330W-7_SC59-3
m m m
co SA00004ZA00
co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti m ti
h emat h emat Security Classification
hema Compal Secret Data
hema Compal Electronics, Inc.hemati
c
S he m c m c c Sc em
kS he Issued Date S e S e
2011/06/29 2011/06/29 Title
okSch okSch okSch
Deciphered Date
Sc ookSc THIS SHEETo o HDMI Conn/Leveloshift
b ok
b SECRET b kDIVISION OF R&D
eb o
k
OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
e oo eTRADE e oo IT CONTAINS
Size Document Number Rev
ot ot otTHEb ot bo
AND INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT
oEXCEPT CKL50 v1.0
N teb eb
DEPARTMENT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR INFORMATION
N t MAY BE
N COMPAL
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
t e ELECTRONICS, INC. N t e
o o o Date:
o
Thursday, March 09, 2017 Sheet 21 of 59
5
N 4
N 3
N 2
N 1
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o o o o
N N N N
DP to CRT converter +HDMI_CRT_5V

+3VS +3VS_CRT
m m m m
co co co co c

0.1U_0201_10V6K
1 .
c s@ o m
2 0_0603_5%
R33
c s. om c s. om c s. om s.
i i i i ic .c

4.7U_0402_6.3V6M
c c c c
at cs. at cs. at cs. at cs. t
1 1
s

C3008
a
CRT@ CRT@

m tic
+3VS_CRT_DVDD

C3009
i i i i
h emat h emat 2 2
hemat h emat hema
c
S he m R34 1 @ 2 0_0603_5%
Sc em Sc em Sc em c
kS he
D D

Sc o okSch o okSch o okSch ookSc

k k k
eboo eboo eboo b
e oo
ot ot ot ot
N teb N teb N teb N teb
o o o o
N N N N

Note: C3001,C3008,C3009,
m om m m
co C3010,C3011,C3012,C3013
.c m co VGA_VSYNC co c
s. om s. om s. om s.
+3VS_CRT_DVDD
sto R3012 1 CRT@ 2 47_0402_5% VGA_VSYNC_R

i c c need to place
i c c o
Chip i c c i c c ic c
at cs. a cs. t at s. at cs. at cs.
+3VS_CRT C3010 VGA_HSYNC
CRT@ 1 R3013 1 CRT@ 2 47_0402_5%
2 0.1U_0402_16V4Z VGA_HSYNC_R

m tic

2P_0402_50V8C
2P_0402_50V8C
CRT@
i i i m ti
emat emat C3011 CRT@ 1 e e1m1at hema
UCT1
h h h a h

C3015
C3014
1 20 2 2.2U_0402_6.3V6M
c
S he m C3001 CRT@1 2 0.1U_0201_10V6K +1.2VO_VCCK
c 4
e m
AVC33 VDD_DAC_33
c
CRT@ 1 e
m c
CRT@ m CRT@ c
kS hVCC_33 kS he2 2 kS he
AVCC_12 +1.2VO_VCCK C3012 S
k ch
+3VS 14 25 2 0.1U_0402_16V4Z
c ookSc23 AUX_P ookSc ookSc
VCCK_12

S 5 DDI2_AUX_DP C3002 CRT@1 2 0.1U_0201_10V6K SOC_DP1_AUXP_R1_C

b PVCC_33
26 +3VS
b oo
C3013 S
k
CRT@ 1 2 0.1U_0402_16V4Z
b CRT Connector
b
oo te oo e oo e oo
CRT@1 2 0.1U_0201_10V6K SOC_DP1_AUXN_R1_C
e SOC_DP1_P0_C1
5 DDI2_AUX_DN C3003

ot bSOC_DP1_N0_C1 ot ot
AUX_N

HVSYNC_PWR 18 o b N teb N teb 6 JCRT1

C3004 CRT@1 2 0.1U_0201_10V6K 5 17 CONN@
N te SOC_DP1_P1_C1 76 LANE1_P VSYNC N te
5 PCH_DPC_P0 LANE0_P +HDMI_CRT_5V
C3005 CRT@1 2 0.1U_0201_10V6K VGA_VSYNC
5 PCH_DPC_N0
o RTD2166 o o o
LANE0_N 19 VGA_HSYNC
5 PCH_DPC_P1 C3006 CRT@1 2 0.1U_0201_10V6K
N N N N
C3007 CRT@1 2 0.1U_0201_10V6K SOC_DP1_N1_C1 8 HSYNC L7 CRTEMI@ 11
5 PCH_DPC_N1 LANE1_N VGA_R VGA_R_2
1 2 1
R3001 2 CRT@ 1 4.7K_0402_5% POL1_SDA 10 23 BLM15BA220SN1D_0402 SM01000LU00 7
R3002 2 CRT@ 1 4.7K_0402_5% POL2 9 POL1/SPI_CEB RED_P L8 CRTEMI@ VGA_SDA 12
C +3VS_CRT POL2 C
22 VGA_G 1 2 VGA_G_2 2
R5116 2 @ 1 4.7K_0402_5% GPI1_SCL 11 GREEN_P BLM15BA220SN1D_0402 SM01000LU00 8
m om BLUE_P VGA_B om om
12 GPI1/SPI_CLK 21 L9 CRTEMI@ VGA_HSYNC_R 13

com
+HDMI_CRT_5V GPI2/SPI_SI VGA_B_2
.c m .c m .c m c
13 1 2 3

s .R3003 GPI3/SPI_SO
s s s
+HDMI_CRT_5V BLM15BA220SN1D_0402 SM01000LU00 9
s.
ic R3004 o ic c o ic c o c c o
tics.c
VGA_SCL VGA_VSYNC_R
iW=40mils
2 CRT@ 1 2.2K_0402_5% 15 14
c
at s. at s. at s. at s.
2 CRT@ 1 2.2K_0402_5% VGA_SDA 16 VGA_SCL 4
VGA_SDA
a

2 R5114 1

2 R5115 1

2 R5113 1
m tic m tic

75_0402_1%
m tic 1 m 1 tic ic

2P_0402_50V8C

2P_0402_50V8C
2P_0402_50V8C
75_0402_1%

75_0402_1%

2P_0402_50V8C
2P_0402_50V8C

2P_0402_50V8C
27 1 10 G 16

emat
RTD2166_SMB_SCL 30 LDO_RSTB 28 @ VGA_SCL 15 17
e a e
29 SMB_SCL a EXT_CLK_IN 31
e a
1 1 1 1
e a
G

C3017

C3020
C3019
h h h h chem
RTD2166_SMB_SDA

C3018

C3022
0.1U_0201_10V6K
C3016

C3021
5

Schem Sc em Sc em c em
SMB_SDA EXT1.2V_CTRL
32 24 S 2
S
C-H_13-12201560CP

okSch okSch okSch okSch

5 DDI2_HPD HPD GND 33 2 2 2
c
2 2 2 DC060006E00
S o o o book
EPAD_GND
2

k k k
ebooR5110 eboo eboo
RTD2166-CG_QFN32_4X4
e
ot ot ot ot o
N teb N teb CRTEMI@ eb N teb
100K_0402_5%
CRTEMI@ CRTEMI@N
t
CRTEMI@ CRTEMI@ CRTEMI@
o o o o
1

N N N N
CRT@ CRT@ CRT@

m m m m
co co co co c
s. om s. om s. om s. om s.
R3006 0_0402_5% 2 @ 1 RTD2166_SMB_SCL
PCH_SMBCLK7,17,18
ic c 7,17,18
PCH_SMBDATA R3007 0_0402_5% 2
i c@
c
1 RTD2166_SMB_SDA
i c c c
ti s.c tics.c
at s. at s. at s.
@ESD@
D4
a a
m tic m tic m tic c I/O2 3 ic
SC300001G00
I/O4 ti
ema emat
VGA_HSYNC_R 6 VGA_VSYNC_R

h e a e a e a
ch m ch m
+HDMI_CRT_5V h
Schem c em chem
kSche kSche okSch
S S
okSch
Sc o o
B 5 2 B

S S
VDD GND
o k o k book book
eboo eboo e e
ot ot ot o ot o
N teb N teb N teb N teb
VGA_SCL 4 1 VGA_SDA
I/O3 I/O1

o o o AZC099-04S.R7G_SOT23-6 o
N N N N
@ESD@
D5
SC300001G00
VGA_R_2 6 3 VGA_G_2
I/O4 I/O2
m m m om
co co co
+HDMI_CRT_5V

s. om s. om s. om s .c m s.
c
i c c i c c i c c
5
i c c
2
o ic .c
at cs. at cs. at cs. at cs. t
VDD GND
a s
emat
i
emat
i
emat
i
em ti I/O1 1 m tic
a hema
VGA_B_2
h h h chem
4
I/O3

Schem Sc em Sc em S c
kS he
okSch okSch k h AZC099-04S.R7G_SOT23-6

Sc o k o k ookSc ookSc
eboo eboo eboo b
e oo
ot ot o t ot
N teb N teb N teb N teb
o o o o
N N N N

A A

m m m m
co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti i m ti
h emat h emat hemSecurity
a Classification emat hema
c m c m c Compal Secret Data ch m Compal Electronics, c
Inc.
S he kS he kS he 2016/03/07 kS Date h
e 2017/09/01 Title kS he
Sc ookSc ookSc ookScINC. AND CONTAINS CONFIDENTIAL ookSc
Issued Date Deciphered
DP to CRT RTD2166
b
e oo b
e oo b
e oTHIS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
oSHEET NOR THE INFORMATION IT CONTAINS
OF COMPAL ELECTRONICS,
Size Document Number
e b o Rev

ot ot ot ot bo
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5

N teb N teb N teb

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER
LA-D701PR05
NMarcht09,e
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, 2017 Sheet 22 of 59
5 o 4 o o 3 o 2 1
N N N N
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o@ +LAN_VDD_3V3 Rising time o o o
N JL33 N N N
1
1 2
2 need>0.5mS and <100mS
+3VALW @ JUMP_43X79

m UL2
m m CL8, CL23 close LL2. m
co co co co
1 +LAN_VDD_1V0
CL26 close UL1 Pin 3.
c
VOUT +LAN_VDD_3V3

s. om s. om s. om s. om s.
5
VIN CL12 close UL1 Pin 8.
<DB> Delete LL1, CL21
1
i c c
t 26 LAN_PWR_EN i c c i c c i c c ic .c
s. at cs. at cs. LL2 t . t
@ 2 CL13 ~ CL15 close UL1 Pin 22.
GND
1500P_0402_50V7K a
CL28 4
a s a s
ic m tic m tic
EN CL11, CL27 close UL1 Pin 30.
i i
emat emat emat
2

hema1 hema
3 +LAN_REGOUT 1 2
h h h
/OC

1U_0402_6.3V6K
0.1U_0402_16V7K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
2.2UH +-5% NLC252018T-2R2J-N

Schem Sc em c em c c
G524B1T11U_SOT23-5 giga8111@
S kS e CL14 kS he
D 1 1 1 1 1 1 1 1 D

okSch k h CL13 h

CL8

CL23
SA00006Y800 @ @

Sc ookSc oo2kSc2 ookSc

CL11 CL12 CL15 CL26 CL27
o k
giga8111@

eboo eboo b b
2 2 2 2 2 2 2

ot o t te oo ot
e oo
giga8111@o
N teb N teb giga8111@
N teb N teb
o o o o 2
N N N N1K_0402_5%
EC_LAN_ISOLATEB#_R 1 +3VS
RM6
8111HSH/8166EH Co-Lay

2
+LAN_VDD_3V3 +LAN_VDD_3V3
UL1 RM11
4.7U_0603_6.3V6K

giga8111@
4.7U_0603_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

4.7U_0603_6.3V6K

giga8111@ RTL8151GH +LAN_VDD_3V3=40mil 15K_0402_5%

m1 0.1U_0402_16V7K
m m m
com co co +LAN_VDD_1V0 L +VDDREG=40mil co
1 1 1 1 1 100_8166@ SA000084T00

1
c
CL10

CL16
@ @ UL1
CL20
2 ic
s.2 oCL5 CL19 CL9
c s. om c s. om c s. om s.
i i i tics.c
+LAN_REGOUT=60mil
c c c c
at s. at cs. t s . 8 t s.
2 2 2 2 LAN_MDIP0 1 3
2 MDIP0 a AVDD10
a a
m tic icAVDD10 m tic m tic
LAN_MDIN0
i
emat emat DVDD10
@8151@ LAN_MDIP1 4 MDIN0 30 +LAN_VDD_3V3 XTLI

h e a h
LAN_MDIN1 5 MDIP1
6 MDIN1 h
AVDD10 22 +LAN_VDD_3V3
hema hema
Schem c m c m c c
LAN_MDIP2 2 1 XTLO

kSche S e kSRL15 e kS he
LAN_MDIN2 7 MDIP2 11 1M_0402_5% RL7
k9 MDIN2 h AVDD33 32
ch

1
LAN_MDIP3
c c ookSc
+LAN_VDD_3V3

oo ookS ookS10K_0402_5%
10 MDIP3 AVDD33
S CL9, CL20 close to UL1 Pin 11 23S
LAN_MDIN3
CL10& CL16 close b
to UL1: Pink b
MDIN3 23
b YL1
b
e o e oo 12
VDDREG(VDD33) 24 +LAN_REGOUT
e oo e o
ot bo tLAN_CLKREQ#_R ot ot3 bo
LAN_CLKREQ# 2 REGOUT
0_0201_5%o
CL5 & CL19 close to UL1: Pin 32 @ 1 1 3

N teb N teb
9 LAN_CLKREQ# RTL8111G

2
19 CLKREQB 1
N te te 2
PLT_RST# EC_PME#
N
9,26,28,32,36 PLT_RST# RL6 21 EC_PME# 26
PERSTB LANWAKEB 20 EC_LAN_ISOLATEB#_R NC NC
o CLK_PCIE_LAN o 15 ISOLATEB
o o
N N N N
9 CLK_PCIE_LAN 2
16 REFCLK_P 2 4

10P_0402_50V8J
CL25
CLK_PCIE_LAN# LAN_ACT#

CL24
10P_0402_50V8J
9 CLK_PCIE_LAN# 27
REFCLK_N LED0 26 LED1/GPO TH1
PCIE_PTX_C_DRX_P5 13 LED1/GPO 25 LAN_LINK#
11 PCIE_PTX_C_DRX_P5 PCIE_PTX_C_DRX_N5 HSIP LED2(LED1) 1 SJ10000UP00 1
11 PCIE_PTX_C_DRX_N5 14
C PCIE_PRX_DTX_P5 CR11 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P5 17 HSIN 28 XTLI 25MHZ_10PF XRCGB25M000F2P34R0 C
11 PCIE_PRX_DTX_P5 HSOP CKXTAL1
PCIE_PRX_DTX_N5 CR13 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N5 18 29 XTLO
11 PCIE_PRX_DTX_N5

om om 33 m om
HSON CKXTAL2

GND o
RSET 31

s.c m s .c m RSET
s .c m s .c m s.
c

2
ic c o SP050005L00 Footprint
ic c o ic .c o ic c o ic c
at s. at cs. at 10/100 at cs. at cs.
RL11
TSL1 100_8166@ 2.49K_0402_1% SA000063500
s
em tic 25
LANGND 24
XGND
m@ t2 i0_0805_5%
RL55 1
e
(SA000063500)
e m ticGiga
8166EH
emat
i
emat
i
a a a
+V_DAC 1
(SA000084T00) 8111HSH
h ch m MCT1 h chem chem

1
LAN_MDIP3 2 TCT1 MCT1 23 RJ45_TX3+ RP5

Schem Sc em
3 TD1+ MX1+ 22

kSche S S
LAN_MDIN3 RJ45_TX3- 1 8
TD1- MX1-

okSch okSch okSch

MCT2 2 7

S c 4
5 TCT2 o o2021
SRJ45_TX2-
MCT3 3 6
o book book
LAN_MDIP2 MCT2 RJ45_TX2+ MCT4
k k
4 5
LAN_MDIN2
e b MX2-o
6 TD2+ MX2+ 19
eb o e e
t o ot bo ot o ot o
TD2- 75_0804_8P4R_1%
o b MCT3 17 RJ45_RX1+ N teb N teb
7 18 SD300002E80
N t89eTCT3 e
2
CL2N
SE167100J80 t
LAN_MDIP1 +LAN_VDD_3V3
o TD3- MX3- 16 RJ45_RX1- o o o
LAN_MDIN1 TD3+ MX3+
CONN@
N 10 TCT4 MCT4 15 1 N
10P_1808_3KV
N 10
JLAN1
A2_AmberLED+
N
LAN_MDIP0 11 14 RJ45_TX0+
LAN_MDIN0 TD4+ MX4+ 1 LAN_ACT# LAN_ACT#_R
12 13 RJ45_TX0- CL3 EMI@ 2 1 9
TD4- MX4- A1_AmberLED-
3

120P_0402_50V8J RL31 510_0402_5%

RJ45_TX3-
YSLC05CH_SOT23-3

ESD@ LANGND 8
2 TX3-
m m m m
DL1

co @EMI@ co co co
2 CAP_LAN-8700GS SCA00000U10 RJ45_TX3+ 7
1
c
TX3+

s. omCL4 s. om s. om s. o6m s.
SP050008V00
CL1 TSL1 RJ45_RX1-

1i c c (SP050008V00) 10/100
X'FORM_ LAN-8100G 1G ti
giga8111@ c c i c c c
i RJ45_TX2-
RX1-
c 5 TX2- ic c
at s. at s. t at cs.
0.01U_0402_16V7K

s. .
0.1U_0402_16V7K
2
(SP050008Y00) Giga SSP050008Y00 a s
a cRJ45_TX2+
m tic m tic m tic i
emat RJ45_RX1+ 4 TX2+ emat
i
1

h e a e a e a
Schem ch m ch m chem 3
chem
kSche kSche S S
RX1+

Sc okSch okSch
RJ45_TX0-
B
o k o S o S
2 B

bo book book
@ESD@ TX0- 13
@ESD@

ebo ok
RJ45_TX0+ 1 GND1 14
o
DM13
e e e
DM12 TX0+ GND2

ot ot3 o ot o ot o
LAN_MDIP0 4 3 LAN_MDIN0 LAN_MDIP2 4 3 LAN_MDIN2

N teb N teb N teb LAN_LINK# N teb

4 3 4 11
B2_WhiteLED+
LAN_LINK#_R
o o o o
2 1 12
B1_WhiteLED-
N N N N
RL30 2K_0402_5%
SANTA_130456-701
LANGND DC23400C300
powe rail need to check powe rail need to check

5 2 +LAN_VDD_3V3 5 2
+LAN_VDD_3V3 Vbus GND Vbus GND
m m m m
co co co co c
c s. om cs. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at s. at cs. at cs. a t s
emat
i
LAN_MDIN1 e
m tic LAN_MDIP3 6 emat
i
emat
i m tic
h LAN_MDIP1 6 1
h a 1 LAN_MDIN3
h h hema
Schem Sc em Sc em Sc em c
6 1 6 1

c
YSUSB2.0-5_SOT-23-6-6
okSch
YSUSB2.0-5_SOT-23-6-6
okSch okSch kS he
S ookSc
SC300001400
o o o
SC300001400
k k k
eboo eboo eboo b
e oo
ot ot ot ot
N teb N teb N teb N teb
o o o o
N N N N

m m m m
A A

co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti m ti m ti
h emat h emat hema hema hema
c
S he m c m c c c
kS he kS he Security Classification Compal Secret DatakS he Compal Electronics, o kS he
Inc.
Sc ookSc ookSc Issued Date 2013/02/26 oo Date S
k
c 2015/07/08 Title
o kSc
b b b b
Deciphered
e oo e oo e o INC. AND CONTAINS CONFIDENTIAL LAN 8151/8166_ e oo
CR RTS5238
ot ot otFROMTHIS THEo ot
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,

N teb N teb DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHERb

N teb
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
NPRIOR t e CONSENTSHEET NOR THE INFORMATION IT CONTAINS
CKL50 v1.0

o o o Thursday, March 09, 2017o

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT WRITTEN OF COMPAL ELECTRONICS, INC.

N N N N
Date: Sheet 23 of 59
5 4 3 2 1
 ot o ot o ot o ot o
5 4 3 2 1

N teb N teb N teb N teb

o +3VS o o o
N N N N
5,6,7,9,10,11,13,17,18,19,20,21,22,23,26,28,32,33,34,35,36,37,38,52,56 +3VS +3VS +DVDD +DVDD_IO +3VS
12 +1.8VS +1.8VS
RA21 @ 2 0_0603_5% 1 @ 2
+5VS LA7 0_0402_5%
20,21,26,27,30,34,35,52,53,56 +5VS

10U_0603_6.3V6M
CA6

.1U_0402_16V7K
CA7
.1U_0402_16V7K
CA5

10U_0603_6.3V6M
CA8
L Layout notes 1 1 1 1
m om mCA6 close Pin1
CA5 m
co .c m coCA7 co c
s. om s. om s. om s.
UA1 CA8 close Pin9
c c s o c CA9 CA10 close Pin26 2 2 2 2
c
i c i c i c CA12 CA13 close Pin40 i c ic .c
at cs. at cs19. MIC1_L at cs. at cs. t
20 1 +DVDD
MIC1_R DVDD 9
a s
m tic
DVDD_IO +DVDD_IO
i i i i
h emat INT_MIC RA3 1 2 1K_0402_5%
CA1 1
CA4 1
h em
2 4.7U_0402_6.3V6M
2 4.7U_0402_6.3V6M at
INT_MICR_C
INT_MICL_C
18
17 MIC2_R
26
AVDD1 40 +5VS_AVDD
+1.8VS_AVDD h
emat h emat hema
Schem Schem Sc em Sc e+5VS m c
MIC2_L AVDD2

kS he
D D

okS okSch okSch

31 41 +5VS_PVDD
c c 30 MIC1_VREFO_L
ookSc
PVDD1 46 +5VS_AVDD
S
26 MUTE_LED_IN
o 29 MIC1_VREFO_R
o o
PVDD2 +1.8VS_AVDD +1.8VS
b k k LA4 k
eboo eboo b
+MIC2_VREFO MIC2_VREFO

1
oo e oo
1 @ 2 0_0603_5%
e 10K_0402_5%
ot b
SPK_OUT_R+ 44 tSPK_R- t ot
23 45 SPK_R+ 1 @ 2
SPK_OUT_R- o o
24 LINE2_R
N teb N t1eb2 N teb

4.7U_0402_6.3V6M
CA10
.1U_0402_16V7K
CA9
LA5 0_0402_5%
N te
LINE2_L

4.7U_0402_6.3V6M
CA13
.1U_0402_16V7K
CA12
RA30

o o Internal Speaker o 1 2
o

2
N N 42 N N
16 SPK_L+
MONO_OUT SPK_OUT_L+ 43 SPK_L- change 30 ohm from vendor suggest
PC_BEEP 12 SPK_OUT_L- 2 1
PCBEEP
20141120
2 1
+3VS HPOUT_R RA4 2 30_0402_1% HP_OUTR
8 HDA_SYNC_AUDIO 10
SYNC HPOUT_R
33
HPOUT_L RA5
1 Headphone
32 1 2 30_0402_1% HP_OUTL
HDA_RST_AUDIO# 11 HPOUT_L
m 8 HDA_RST_AUDIO#
om
RESET#
om om
co +3VS .c m SDATA_OUT .c m .c m c
4.7U_0402_6.3V6M
CA17

CPVDD 5 GNDA

s. om s.
2 1 @ 2 HDA_SDOUT_AUDIO 8
s sHDA_SDIN0 sGNDA
RA6 8 SDATA_IN RA7 1 2 22_0402_5%
c c o c o c o ic c
SDATA_IN 8
i i i i
ALDO_CAP
c c c c
4.7K_0402_5% CA11 1 2 10U_0603_6.3V6M 7

at cs. at s34. at cs.HDA_BITCLK_AUDIO at cs. at cs.

LDO3-CAP 6 +5VS_PVDD +5VS
BCLK 8
CPVDD ic 36 CPVEE
1 CA14 1 2 2.2U_0402_6.3V6M ACPVEE LA6 SM01000NS00
i i i m ti
emat mCBN t m t emat
22 1 2

he a hema hema
35 CPVDD LINE1_L 21
h h
TAI-TECH HCB2012VF-601T20 0805
c Schem S1c20K_0402_1% c c
LINE1_R 48
m 37 CBN
m

.1U_0402_16V7K
CA21
MIC_JD

.1U_0402_16V7K
CA20

10U_0603_6.3V6M
CA23
CBP

10U_0603_6.3V6M
CA22
CA15 1 2 2.2U_0402_6.3V6M
S he e kSche kS he
CBP SPDIFO/GPIO2
k 2 k h
1 1 2 2
15 JDREF RA9

Sc ookSc oo c oo ookSc
JDREF 28 AVREF CA16 2
2 S S
2 1 .1U_0402_16V7K
20 D_MIC_DATA
1 k 1 k1
3 GPIO0/DMIC_DATA VREF 27

eboo eb b b
CA18 1 10U_0603_6.3V6M
o o e oo
20 D_MIC_CLK
e
GPIO1/DMIC_CLK LDO1_CAP 39 CA19 2 10U_0603_6.3V6M 2 2

o t LDO2_CAP
o t o ot bo ot
N teb N 38teb N te N teb
PLUG_IN# RA10 1 2 39.2K_0402_1% SENSEA 13 25 2 RA29 1 100K_0402_5%
14 SENSE_A AVSS1
o SENSE_B AVSS2
o4 o o
N 47
NDVSS 49 add 100k from vendor suggest
GNDA N N
+1.8VS +DVDD PDB Thermal Pad 20141120
1

C ALC3227-CG_MQFN48P_6X6 AVREF CA24 1 2 2.2U_0402_6.3V6M C

1

om om m om
RA25

.c m
2.2K_0402_5% 1K_0402_5%

.c m com
.GNDA .c m
Internal SPK <DB> change foorprint
c
s.
RA26 GNDA
s s s s
2 2

ic c o ic c o o
ic c SPK_R- ic .c o ic c
CONN@
2

at s. at s. at s. at sSPK_R-_CONN at cs.
B

SB000008E10 JSPK1
RA13 1 @ 2 0_0603_5% 1

m tic m tic m tic m tic SPK_L-_CONN m ti

1
E

HDA_RST_AUDIO# 3 1 PD# SPK_R+ RA14 1 @ 2 0_0603_5% SPK_R+_CONN 2

e e e e hema
2
a a a a
C

SPK_L- RA15 1 @ 2 0_0603_5% 5 3

h QA1
h h SPK_L+ RA16 1 @ 2 0_0603_5%
h SPK_L+_CONN 3 GND

Schem c em c em Schem c
6 4
4 GND
1

MMBT3904WH_SOT323-3
S S S e
okSch
Power down (PD#) power stage for save power k
o Sch k okSch
E-T_3703K-F04N-03R

Sc ookS c
10K_0402_5% SP02000H310
1 2
26 EC_MUTE#

book
RA11 0V: Power down power stage
book
wide 40 MIL book

220P_0402_50V7K
220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
DA3

eboo
3.3V: Power up power stage
e
CH751H-40PT_SOD323-2
e e
ot o ot o t ot 1 o
2

SCS00003500
o
1 1

N teb N teb b
1

N teb

@EMI@ C125
@EMI@ C123

@EMI@ C124

@EMI@ C126
N te
o o o o
N N N N
2 2 2 2

Reserve for ESD request.

m m INT_MIC_R m m
co com com co
HP_OUTR_R HP_OUTL_R
GNDA
c
s. om s o. .
s o s. om s.

3
ic PC Beep i c i c i c ic c

3
c c c DA4
c
at s. at s. at s. at s. at cs.
YSLC05CH_SOT23-3 DA6

m tic m tic m tic m tic emat

i
SCA00002900 YSLC05CH_SOT23-3

h e a e a e a ESD@ SCA00000U10
e a
Schem
EC Beep chCA311m2 PC_BEEP_R ch m @ESD@
ch m chem
kSche kSche kSche S
26 EC_BEEP#

okSch
+MIC2_VREFO

Sc o o o
B .1U_0402_16V7K RA19 Jack detect B
S S S

1
SB Beep b o k 47K_0402_5%
book book Combo Mic = High book

1
1 2 1 2 PC_BEEP
o
8,10 HDA_SPKR 1 2
e e e e

1
ot o .1U_0402_16V7Kt
bo ot bo ot o
CA34
CA33 Normal HP = Low
o
N teb N tebRA17
1

.1U_0402_16V7K
N t e N t e
o o o o
RA20 2.2K_0402_5%

N L Layout notes N
10K_0402_5%
N N

2
MIC_JD 1 2 INT_MIC
2

RA18
Close chip Pin12

10U_0603_6.3V6M
CA32
22K_0402_5%
2

m m m m
co co co co
1
c
c s. om cs. om c s. om c s. om s.
ic .c
GNDA
i c i c i c i c
at cs. at cs. at cs. COMBO AUDIO JACK at cs. a t s
emat
i
emat
i
emat
i
emat
i m tic
h h h h hema
SchRA27
em Sc em Sc em S c em CONN@ c
kS he
okSch okSch okSch
1 2 0_0402_5% HPR, HPL, 15mil Keep 30mil JHP

Sc ookSc
INT_MIC INT_MIC_R
o o o
RA21 1 @ 2 0_0402_5% 3
k k k
HP_OUTL HP_OUTL_R

eboo b b b
RA22 1 @ 2 0_0402_5% 1
e oo e oo e o
ot t t ot 5 o
RA28 1 2 0_0402_5%
o o
N teb b b N te6 b
PLUG_IN#
N te N te
1 2 o o o o
CA40 @EMI@
.1U_0402_16V7K
N N HP_OUTR
RA23 1 @
N
2 0_0402_5%
HP_OUTR_R N 2

4
100P_0402_50V8J
CA35
7

10P_0402_50V8J
CA37
10P_0402_50V8J
CA36
1 2 1 1 1
1

CA38 @EMI@
m m om om
A YUQIU_PJ733-F07J1BE-A~D A
.1U_0402_16V7K RA24

co co
@EMI@

@EMI@
@EMI@
.c m .c m c
22K_0402_5% DC23000DV0L

s. om s. om s.
2 2 2

c
1 2
c c s o c s o
GNDA
i c i c i c i c tics.c
2

at cs. at cs. at cs. at cs.

CA39 @EMI@
.1U_0402_16V7K Pin6 and Pin5
a
2 i i m ti GNDA m ti m tic
Normal OPEN

h em 1 t
CA29 aEMI@
h emat hema
GNDA GNDA GNDA
hema hema
c
S he m
.1U_0402_16V7K c m c c c
kS he kS he Security Classification Compal Secret DatakS he Compal Electronics, Inc. kS he
Sc ookSc ookSc oo c 2015/01/04 ookSc
1 2
2013/01/04 Date S Title
CA30 EMI@
b b
Issued Date
b
Deciphered
k b
.1U_0402_16V7K
e oo e oo e o INC. AND CONTAINS CONFIDENTIAL AUDIO e oo
ALC3227-CG
ot ot otFROMTHIS THEo ot
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,

N teb N teb DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHERb

N teb
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
GNDA
NPRIOR t e CONSENTSHEET NOR THE INFORMATION IT CONTAINS C
CKL50 v1.0

o o o Thursday, March 09, 2017o

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT WRITTEN OF COMPAL ELECTRONICS, INC.

N N N N
Date: Sheet 24 of 59
5 4 3 2 1
 ot o ot o ot o ot o
A B C D E

N teb N teb N teb N teb

o o o o
WIN 7 Debug N
Solution N N N

Option 1 : For Closed Chassis Platforms

m m m m
co co co co c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
emat
i
emat
i
emat
i m tic
h h h h hema
1 c
S he
m Sc em Sc em Sc em c
kS he
1

Sc o okSch o okSch o okSch ookSc

k k k
eboo eboo eboo b
e oo
ot ot ot ot
N teb N teb N teb N teb
o o o o
N N N N

m m m m
co co co co c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i i i m ti
h emat h emat h emat hemat hema
c
S he m c m c m c m c
kS he kS he kS he kS he
Sc ookSc ookSc ookSc ookSc
b
e oo b
e oo b
e oo b
e oo
ot ot ot ot
N teb N teb N teb N teb
o o o o
N N N N
2 2

om om om om
s.c m s .c m s .c m s .c m s.
c
ic c o ic c o ic c o ic c o ic c
at s. at s. at s. at s. at cs.
em tic e m tic e m tic e m tic emat
i
h a a a a
Schem ch m ch m ch m chem
c o kSche okSche o kSche S
okSch
S o kS o kS o kS
eb o eb o eb o e book
ot bo ot bo ot bo ot o
N te N te N te N teb
o o o o
N N N N

m m m m
co co co co c
c s. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at s. at s. at s. at s. at cs.
e m tic e m tic e m tic e m tic emat
i
a a a a
chem ch m ch m ch m chem
S h kSche kSche kSche S
okSch
Sc o o o
3 3
o k S o k S o k S
eboo eboo eboo e book
ot ot ot ot o
N teb N teb N teb N teb
o o o o
N N N N

m m m m
co co co co c
c s. om cs. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
emat
i
emat
i
emat
i m tic
h h h h hema
Schem Sc em Sc em Sc em c
kS he
Sc o okSch o okSch o okSch ookSc
k k k
eboo eboo eboo b
e oo
ot ot ot ot
N teb N teb N teb N teb
o o o o
N N N N

4 4
m m m m
co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i i m ti m ti
h emat h emat emat
hClassification hema hema
c m c m c
Security
m Compal Secret Data c Compal Electronics, Inc. c
S he kS he heDate
kScIssued 2011/06/29 Deciphered Date k he
S 2011/06/29 Title
kS he
Sc ookSc ookSTHIS ook Sc DC InterfaceookSc
b
e oo b
e oo b
CUSTODYo
eSHEET
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
eb o Rev
ot ot otTHIS b o CKL50 ot bo
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE OF THE COMPETENT DIVISION OF R&D

N teb N teb
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER NOR THE INFORMATION IT CONTAINS Custom v1.0
N tCONSENT
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN
e OF COMPAL ELECTRONICS, INC. N t e
o o o Date:
o
Thursday, March 09, 2017 Sheet 25 of 59
A
N B
N C
N D
N E
 ot o ot bo ot o ot o
5 4 3 2 1

N teb N e N teb N teb

o +3VL ot
+3VALW_EC o EC Board ID (UMA, Dis, ocontrol
phase) table
N +3VS
5,6,7,9,10,11,13,17,18,19,20,21,22,23,24,28,32,33,34,35,36,37,38,52,56 +3VS N LK1 N+3VALW_EC N
S SUPPRE_ TAI-TECH HCB1005KF-221T15 0402

0.1U_0402_16V7K

0.1U_0402_16V7K
1 2 +3VALW_EC 1 2 +EC_VCCA
45 +3VALW_EC +3VALW_EC RK4 DB SI PV MV Note

2
CK1

CK2
RK1 0_0603_5% 1 1 1
RK2
13,33,46,47,48 +3VL +3VL UMA 15Kohm 27Kohm 43Kohm 75Kohm
m m om
CK3
100K_0402_1%
m
co co 2 co56Kohm 100Kohm

ECAGND
.c m DIS 20Kohm 33Kohm c
0.1U_0402_16V7K

s. om s. om s. om s.
2 2
s

1
i c c i c c i c c o i c c ic .c
at cs. at cs. t . t . t
BOARD_ID
a
+3V_EC_VDD ic
s a 15Kc s a cs
i i S RES 1/16Wi i
emat ESD@ CK4 emat m t m
at20K +-1% 0402 emat
DB_UMA_15kohm:SD034150280, +-1% 0402

hema 1 RK3 2 hem

2
h h h
DB_DIS_20kohm:SD034200280, S RES 1/16W
Reserve EC_CLR_CMOS for clear CMOS
Schem Sc em c c c m
PX@ UMA@ SI_UMA_27kohm:SD034270280, S RES 1/16W 27K +-1% 0402
S e S e S e
D +3VL D
SI_DIS_33kohm:SD034330280, S RES 1/16W 33K +-1% 0402

okSch okSch k ch okSch

2 1 PLT_RST# RK4 RK4 (2016-03-04 : Confirm intel platform not support EC
Sc oPV_UMA_43kohm:SD034430280,
0_0402_5% 100K_0402_1% S RES 116W 43K +-1% 0402 Clear CMOS function)
o k o k o S
PV_DIS_56kohm:SD034560280,
k
S RES 1/16W 56K +-1% 0402
o
0_0402_5% k
SD034100380 75K_0402_1%
eboo eboo ebooMV_UMA_75kohm:SD034750280, 2 b

1
0.1U_0402_16V7K SD034750280 S RES 1/16W 75K +-1% 0402 RK106 1
@ e
o
ot UK1t ot ot bo
CLR_CMOS# 9

111
125
MV_DIS_100kohm:SD034100380, S RES 1/16W 100K +-1% 0402
o
N teb N teb N teb

22
33

67
96
9
N e
ot

1
Board ID control @
o o o

VCC_LPC
VCC
VCC

AVCC
VCC
VCC0
VCC
D
@ N N N EC_CLR_CMOS N 2 Q51
RK7 2 1 330K_0402_5% EC_RST# G 2N7002K_SOT23-3
+3VALW_EC

2
1 21 EC_VCCST_PG_R S
20TOUCH_ON GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_VCCST_PG_R 9,35
@ 1 2 EC_KBRST# 2 23 2014-11-13: R483
7EC_KBRST# EC_BEEP# 24

3
SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 EC_FAN_PWM1 Pin64 from BOARD_ID to X no support KBL
@
CK5 0.1U_0402_16V7K 7,28 SERIRQ EC_FAN_PWM1 34 Pin66 from X to BOARD_ID 10K_0402_5%
SERIRQ EC_FAN_PWM/GPIO12
m m
7,28 LPC_FRAME#
LPC_FRAME# 4 PWM Output m 27 EC_CLR_CMOS
m Pin76 Pin97 swap

co co com co
LPC_AD3 5 LPC_FRAME# AC_OFF/GPIO13 Pin84 from PM_SLP_S4# to USB_ON#

c
s. om s. om s.63 oB/I# s. om s.
7,28 LPC_AD3 Pin68 from +1.05V_VS_PG_PWR to MINI1_LED#

1
LPC_AD2 7 LPC_AD3 Pin70 NC , no support
7,28 LPC_AD2 LPC_AD2
c c c c ic c
LPC_AD1 Pin72 NC , no support
i i i i
8
c c 7,28 LPC_AD1
c c
at cs. at cs. CLK_PCI_LPC at cs.65 ADP_I at cs. at cs.
LPC_AD0 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38
VGA_AC_BATT B/I# 46 Pin86 NC , no suppout
7,28 LPC_AD0 10 LPC & MISC 64
LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 VGA_AC_BATT 37
i ti i i m ti
emat e7m emat emat
ADP_I/AD2/GPIO3A
BOARD_ID ADP_I 45,47

hema
12 AD Input 66
9,23,28,32,36 a
CLK_PCI_LPC
13 CLK_PCI_EC AD_BID/AD3/GPIO3B
c h m c h m
PLT_RST#
PLT_RST#
EC_RST# PCIRST#/GPIO05
c h m
75 ADP_ID
AD4/GPIO42
EC_PME#_EC_R 2 0_0201_5%c
h m
ADP_ID 45
c
S he e kS he kS he kS he PROCHOT# 5
37 76
SEC_SCI#
R5178 1 EC_PME# 23
EC_RST# AD5/GPIO43
k h
EC_SCI# 20 VR_HOT# 1 2 0_0402_5%
5,10
Sc c o kSc ookSc ookSc
52 VR_HOT#
o 1 @ 2 PM_CLKRUN#_R
CLKRUN#/GPIO1D o
38 EC_SCI#/GPIO0E RK8
o kS
7 PM_CLKRUN#
RK10 1 2 0_0402_5%
eboo b b b
@
9,32 EC_PCIE_WAKE#
te oo DA Output EN_DFAN1/DA1/GPIO3D oo 27 <DB> Add KBL_ON#
e KBL_ON# e o
RK6 0_0402_5% 68

o t DA0/GPIO3C 70 NMI_DBG#
ot ot bo D
55 o
N teb b N teb
27 KSI[0..7]

1
N te N e 2
KSI0 71 VR_PWRGD

ot
VR_PWRGD 52
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 EC_MUTE# H_PROCHOT#_EC
o KSI2 57 o
KSI1/GPIO31 DA3/GPIO3F o EC_MUTE# 24
N N N N
G
KSI3 58 KSI2/GPIO32 83 EC_SMB_CK3
EC_SMB_CK3 37
@ QK1 S

3
KSI4 KSI3/GPIO33
59 EC_MUTE#/PSCLK1/GPIO4A 84 EC_SMB_DA3 2N7002_SOT23-3
C
KSI5 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B VR_ON EC_SMB_DA3 37 C
60 85 VR_ON 35,52
VCIN1_ACOK_R KSI6 61 KSI5/GPIO35 PSCLK2/GPIO4C 86
47 VCIN1_ACOK 1 @ 2
KSI7 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D TP_CLK LAN_PWR_EN 23
R4958 0_0402_5% 27 KSO[0..17] 62 87 TP_CLK 27

om om om om
KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA
KSO1 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 27

.c m .c m .97c ENBKL .c high c

40 RK91 2 0_0402_5%
s.
KSO1/GPIO21
s o s o
KSO2 41
s o m c .c m-> low
s o
ic c R5094 1 ic c ic .98 tics.c
VCIN1_AC_IN_R KSO3 KSO2/GPIO22 <DB> WLAN_PWREN_EC# active
i
42 +3VALW
c ME_Flash_EN
2

at cs. at s. t t
KSO4 KSO3/GPIO23 ENBKL 5
ENKBL/GPXIOA00
a cs 99 VCIN0_PH s
43
a a
0_0402_5% WL_PWREN_EC# 32
m tic ic ic
KSO5 KSO4/GPIO24 WOL_EN/GPXIOA01 TP_CLK
i i
44 RK12 1 2 4.7K_0402_5%
m KSO5/GPIO25 Int. K/B
emat emat emat
ME_Flash_EN 8
at
KSO6 ME_EN/GPXIOA02

he e 45 109
a KSO6/GPIO26 Matrix VCIN0_PH 45

ch m chem chem chem

KSO7 46 VCIN0_PH1/GPXIOD00 TP_DATA RK13 1 2 4.7K_0402_5%
Schem
KSO8 KSO7/GPIO27

kSche S S S
47 SPI Device Interface
KSO8/GPIO28
okSch
EC_SPI_SO k
o7 Sch okSch +3VL
VCIN1_AC_IN 1 @ 2 VCIN1_AC_IN_R KSO9 48 119

Sc For Solve tPCH04(Min 9ms) Sequence Timing o KSO10 KSO9/GPIO29 MISO/GPIO5B 7

o kS
R4960 0_0402_5% 49 120
book book7 book
KSO11 KSO10/GPIO2A EC_SPI_CLK EC_SPI_SI
MOSI/GPIO5C

eb o
50 126 SPI Flash ROM SPICLK/GPIO58
e e e
KSO12 51 KSO11/GPIO2B

ot bo ot ot ot bo
128
KSO13 o KSO12/GPIO2C
o
EC_SPI_CS0#
SPICS#/GPIO5A

N teb N teb TS_GPIO_EC 20

52
KSO13/GPIO2D
N te 8 te 1
NRP12
KSO14 53
KSO15 KSO14/GPIO2E
o KSO16 o 54
KSO15/GPIO2F
73
SYS_PWROK o
EC_CIR_RX/AD6/GPIO40 PLT_RST# o
N KSO17 N 81
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
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B v1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CKL50
m m m m Date: Thursday, March 09, 2017 Sheet 27 of 59
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
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m m
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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b b Issued Date
b k Date 2014/07/01 Title
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e oo e o e oPROPERTY o OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL e oo
ot ot bo tPROPRIETARY ot Number
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NBY COMPAL
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o o MAY BE USED BY OR DISCLOSED TO ANY THIRD
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5
N 4
N 3
N 2
N Thursday, March 09, 2017
Date:
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N NIssued Date DecipheredN
Date N
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B v1.0
m m
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CKL50
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co com co Date: coThursday, March 09, 2017 Sheet 30 of 59 c
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A B C D E

N teb1 CS2 N teb N teb +5VALW N teb

o o o o
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11 USB3_TX1_N 2 1 @ 2
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N USB3.0 need support 3.5A N N

2
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SINGA_2UB2309-000111F
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o o o o
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N N DFN ESD
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NPRIOR t e CONSENTSHEET NOR THE INFORMATION IT CONTAINS C v1.0

o o o Thursday, March 09, 2017o

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT WRITTEN OF COMPAL ELECTRONICS, INC.

N N N N
Date: Sheet 31 of 59
A B C D E
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m m m m
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT WRITTEN OF COMPAL ELECTRONICS, INC.

N N N N
Date: Sheet 32 of 59
5 4 3 2 1
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N NIssued Date DecipheredN
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B v1.0
m m
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. m CKL50
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B v1.0
m m
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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co com co Date: coThursday, March 09, 2017 Sheet 34 of 59 c
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ot otTHEb ot bo
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e Sheet
o o o Date: Thursday, March 09,
o 35 of 59
A
N B
N C
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PCI EXPRESS INTERFACE

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AL23
m m M30 P24 m m
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+1.0VS_VGA

ot bo o b Y22 ot ot
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CALIBRATION
N te e
N PCIE_CALR_TX
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R5159 1 PX@ 2 1.69K_0402_1%
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N R1400 1 PX@ 2 1K_0402_5% N10
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GPU_RST# AL27
PERSTB

m om A0 SUN PRO S3 m m
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SA000098V10
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o Y
4
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N NSCS00003500 N N
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9,23,26,28,32 PLT_RST# A
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1

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3

R1631 R70@
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i i i i m ti
h emat h emat h ematSecurity Classification Compal Secret Data h emat Compal Electronics, hema Inc.
c
S he m c m c m c m c
kS he kS he S h e kSche
Title
Issued Date 2013/01/11 kDeciphered Date 2013/12/31
Sc ookSc ookSc oo k S c SUN_PCIE/DP
Size Document Number o
o S
b b b b ok
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CONFIDENTIAL
Rev
e oo e o e PRIOR INC. o
te o
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION
DIVISION OF
OF R&D
R&D

ot ot bo MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTYt o Custom v1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,
o WITHOUT
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
o CKL50
N teb b b
WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
N te N te Date: eMarch 09, 2017 5
NThursday,
t
Sheet 36 o f 59
1
o 2
o 3
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o
N N N N
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1 2 3 4 5

N te+3VS_VGA N teb N teb N teb

o o o o:
N N N N
+1.8VS_VGA
EC_SMB_DA2 1 @ 2 VGA_SMB_DA3
PS_0[3:1]=001 Strap Name
R162 0_0402_5% PS_0[5:4]=11

1
U666B @ U? PS_0[1] ROM_CONFIG[0]

1
EC_SMB_CK2 1 @ 2 VGA_SMB_CK3 PX@
R164 0_0402_5% PX@R327 R328
Resistor Divider Lookup Lable R5165
10K_0402_5% PX@ 10K_0402_5% 8.45K_0402_1%
PS_0[2] ROM_CONFIG[1]

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AF2 R_pu (ohm) R_pd (ohm) Bitd [3:1] PS_0[3] ROM_CONFIG[2]
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c

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1 27MHZ_10PF_XRCGB27M000F2P18R0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Rev

N teb N teb N teb

1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom v1.0
N te
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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o o o Date:
o 09, 2017
Thursday, March Sheet 37 of 59

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co co co
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N N N N N21
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0.1U_0402_16V7K

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i i i i m ti
h emat h emat h ematSecurity Classification Compal Secret Data h emat Compal Electronics, hema Inc.
c
S he m c m c m c m c
kS he kS he S h e kSche
Title
Issued Date 2013/01/11 kDeciphered Date 2013/12/31
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o S
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Rev
e oo e oo e o INC. o
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

ot ot MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTYt

ot March
Custom v1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,
o WITHOUT PRIOR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CONTAINS
CKL50
N teb N teb N teb b
WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
N te
Thursday, 09, 2017 Sheet 38 o f 59
1
o 2
o 3
o 4
o 5

N N N N
 ot o ot o ot o ot o
1 2 3 4 5

N teb N teb N teb N teb

o o o o
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10U_0603_6.3V6M

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2.2U_0402_6.3V5M
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2.2U_0402_6.3V5M
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0.1U_0402_10V6K
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1U_0402_6.3V4Z
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cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i i i m ti
h emat h emat h ematSecurity Classification Compal Secret Data h emat Compal Electronics, hema Inc.
c
S he m c m c m c m c
kS he kS he S h e kSche
Title
Issued Date 2013/01/11 kDeciphered Date 2013/12/31
Sc ookSc ookSc oo k S c SUN_Power
Size Document Number o
o S
b b b ebo ok
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Rev
e oo e oo e o INC. o
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

ot ot MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTYt

ot March
Custom v1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,
o WITHOUT PRIOR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
CKL50
N teb N teb N teb b
WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
N te
Thursday, 09, 2017 Sheet 39 o f 59
1
o 2
o 3
o 4
o 5

N N N N
 ot o ot o ot o ot o
1 2 3 4 5

N teb N teb N teb N teb

o o o o
N N N N

m m m m
com co co co
M_DA[63..0]
c
41,42 M_DA[63..0]

c s. M_MA[15..0]
o
M_MA[15..0]
c s. om c s. om c s. om s.
i i i i ic .c
41,42

at cs .c M_DQM[7..0]
at cs.
c
at cs.
c
at cs.
c
a t s
m tic
41,42 M_DQM[7..0]
i 41,42 M_DQS[7..0] i i i
emat emat emat emat hema
M_DQS[7..0]

h h h h
Schem Sc em Sc em Sc em c
M_DQS#[7..0]

kS he
A 41,42 M_DQS#[7..0] A

Sc o okSch @
o okSch o okSch ookSc
k k k
eboo eb o eboo b
e oo
U666C U?

ot ot bo ot ot
N teb N teb N teb
GDDR5/DDR3 GDDR5/DDR3
M_DA0
NJ29 t
K27
e
DQA0_0
K17
MAA0_0/MAA_0 J20
M_MA0

o oDQA0_1 o o
M_DA1 M_MA1
MAA0_1/MAA_1 H23
N NH30 N N
M_DA2 M_MA2
M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
M_DA4 DQA0_3
G29 MAA0_3/MAA_3 M_MA4 G24
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M_MA6
+1.5VS_VGA +1.5VS_VGA M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13

om m m m
M_DA9 DQA0_8 MAA0_8/MAA_13 M_MA15

co co co
F27 L17
DQA0_9 MAA0_9/MAA_15
.c m c
M_DA10 A28

s. om s. om s. om s.
DQA0_10
PX@s 1
1

M_DA11 C28 J14 M_MA8

i c co PX@
i c c
M_DA12 E27 DQA0_11
i c c
MAA1_0/MAA_8 K14 M_MA9
i c c ic c
a t s.R363 R365
at cs.
M_DA13 G26 DQA0_12
DQA0_13
at cs.
MAA1_1/MAA_9
MAA1_2/MAA_10
J11
at cs.
M_MA10
at cs.
ic
M_DA14 D26 J13 M_MA11
i i i m ti
40.2_0402_1% 40.2_0402_1%

emat emat emat emat

M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12

hema
DQA0_15 MAA1_4/MAA_12
2
2

M_DA16 M_BA2
h h h h
A25 M_BA2 41,42 G11
c m c m c m c m c
+MVREFDA +MVREFSA M_DA17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 M_BA0
S he kSche kS he kS he kSche
M_DA18 DQA0_17 M_BA0 41,42MAA1_6/MAA_BA0 M_BA1
E25 M_BA1 41,42 L15
M_DA19 DQA0_18 MAA1_7/MAA_BA1 M_MA14
c ookSc ookSc
D24
1 o
ook+1.5VS_VGA
G14
DQA0_19
1

MAA1_8/MAA_14
1

S o S S
M_DA20 E23 L16

MEMORY INTERFACE
1
k
DQA0_20 MAA1_9/RSVD
R457 b C514 b b b
PX@ PX@ PX@ PX@ M_DA21 F23
R364
e o M_DA22
e ooWCKA0_0/DQMA0_0 E30
DQA0_21 M_DQM0
e oo e o
ot bo ot ot ot bo
C467 D22 E32
100_0402_1% M_DA23 DQA0_22 M_DQM1

N teb N teb
1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z F21
DQA0_23
WCKA0B_0/DQMA0_1 A21
N te N te
2 2 M_DA24 E21 M_DQM2
2

DQA0_24
2

M_DA25 D20 WCKA0_1/DQMA0_2 C21 M_DQM3

o M_DA26 o F19 DQA0_25
WCKA0B_1/DQMA0_3 E13 M_DQM4 o 100_0402_1%1 PX@ 2 RV136 M_MA0 o 1 PX@
100_0402_1% PX@ 2 RV137
N M_DA27
M_DA28
N A19
D18
DQA0_26
WCKA1_0/DQMA1_0 D12
DQA0_27
WCKA1B_0/DQMA1_1 E3
M_DQM5
M_DQM6
N 100_0402_1%1
100_0402_1%1
PX@ 2 RV138
PX@ 2 RV140
M_MA1
M_MA2
N
100_0402_1%1
100_0402_1%1
2 RV139
PX@ 2 RV141
M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7 100_0402_1%1 PX@ 2 RV142 M_MA3 100_0402_1%1 PX@ 2 RV143
M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3 M_MA4
100_0402_1%1 PX@ 2 RV144 100_0402_1%1 PX@ 2 RV145
B M_DA31 C17 DQA0_30 H28 M_DQS0 100_0402_1%1 PX@ 2 RV146 M_MA5 B
100_0402_1%1 PX@ 2 RV147
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1 M_MA6 100_0402_1%1 PX@ 2 RV149
100_0402_1%1 PX@ 2 RV148

om om om om
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2 M_MA7
100_0402_1%1 PX@ 2 RV150 100_0402_1%1 PX@ 2 RV151
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 M_DQS3 100_0402_1%1 PX@ 2 RV152 M_MA8
.c m .c m .c m .c m c
E19 100_0402_1%1 PX@ 2 RV153

s.
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 M_DQS4 M_MA9
s s
E15
s s
100_0402_1%1 PX@ 2 RV154 100_0402_1%1 PX@ 2 RV155
DQA1_3
o o o o
EDCA1_0/QSA1_0
ic c PX@ ic c ic c ic c ic c
M_DA36 D14 D10 M_DQS5 100_0402_1%1 PX@ 2 RV156 M_MA10 100_0402_1%1 PX@ 2 RV157
DQA1_4

at s. at cs.
EDCA1_1/QSA1_1

at cs. at cs. at cs.

PX@ M_DA37 F13 D6 M_DQS6 100_0402_1%1 PX@ 2 RV158 M_MA11 100_0402_1%1 PX@ 2 RV159
M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7 M_MA12 100_0402_1%1 PX@ 2 RV161

m tic
R5160 R455 100_0402_1%1 PX@ 2 RV160

ti i i i
DQA1_6
DRAM_RST m m t emat emat
M_DA39 C13 EDCA1_3/QSA1_3 100_0402_1%1 PX@ 2 RV162 M_MA13 100_0402_1%1 PX@ 2 RV163
49.9_0402_1% 10_0402_1%

h e a 1 2 2 1 e a
M_DA40 E11
DDBIA0_0/QSA0_0B e
DQA1_7 H27
a M_DQS#2
M_DQS#0 100_0402_1%1 PX@ 2 RV164 M_MA14 100_0402_1%1 PX@ 2 RV165

ch m cheC23m M_DQS#3 che100_0402_1% chem

41,42 DRAM_RST# M_DA41 DQA1_8 M_DQS#1 M_MA15

Schem m 1 PX@ 2 RV168

A11 A27 100_0402_1%1 PX@ 2 RV166 100_0402_1%1 PX@ 2 RV167
DQA1_9
DDBIA0_1/QSA0_1B

kSche S S S
M_DA42 C11
k ch C19 okSch 100_0402_1% ok ch
M_DA43 DQA1_10
DDBIA0_2/QSA0_2B
1

F11 M_BA0 100_0402_1%1 PX@ 2 RV169

Sc o oDDBIA0_3/QSA0_3B
1 M_DA44 DQA1_11 M_DQS#4 M_BA1
A9 C15 100_0402_1%1 PX@ 2 RV171

kS kS
PX@ 2 RV173 S
PX@ 1 PX@ 2 RV170
R5161o
booDDBIA1_1/QSA1_1B book book
PX@ DQA1_12
M_DA45 C9 DDBIA1_0/QSA1_0B M_DQS#5 M_BA2 100_0402_1%1

eb o
C469 E9 100_0402_1%1 PX@ 2 RV172
M_DA46 DQA1_13 M_DQS#6
120P_0402_50V8J 5.1K_0402_1%
eF9 C5
e e
ot bo ot o DDBIA1_3/QSA1_3B ot o ot 1 b o2 RV175
2 M_DA47 D8 DQA1_14
DDBIA1_2/QSA1_2B H4 M_DQS#7 100_0402_1%1 PX@ 2 RV174 VRAM_ODT0 100_0402_1% 1 PX@

N teb N teb
DQA1_15
2

M_DA48 E7 VRAM_ODT1 100_0402_1%

N te te
100_0402_1%1 PX@ 2 RV176 PX@ 2 RV177
M_DA49 A7 DQA1_16 L18 VRAM_ODT0 41,42 N
o o o o
M_DA50 C7 ADBIA0/ODTA0 K16
DQA1_17 M_RAS#0 100_0402_1% 1 PX@ 2 RV179
VRAM_ODT1 41,42 100_0402_1%1 PX@ 2 RV178
N N N N
M_DA51 F7 ADBIA1/ODTA1
DQA1_18 100_0402_1%1 PX@ 2 RV180 M_RAS#1 100_0402_1%1 PX@ 2 RV181
M_DA52 A5 DQA1_19 H26
M_DA53 DQA1_20 CLKA0 M_CLK0 41,42 M_CAS#0
E5 H25 M_CLK#0 41,42 100_0402_1%1 PX@ 2 RV182 100_0402_1%1 PX@ 2 RV183
M_DA54 DQA1_21 CLKA0B 100_0402_1%1 PX@ 2 RV184 M_CAS#1
C3 100_0402_1%1 PX@ 2 RV185
M_DA55 DQA1_22
Place close to GPU (within 25mm) M_DA56
E1
DQA1_23 CLKA1
G9 M_CLK1 41,42 M_CS0B#0
G7 H9
and place componment close to each other M_DA57 DQA1_24 CLKA1B M_CLK#1 41,42 100_0402_1%1 PX@ 2 RV186
M_CS0B#1
100_0402_1%1 PX@ 2 RV187
m m m 41,42 mM_CS1B#0
G6 100_0402_1%1 PX@ 2 RV188 100_0402_1%1 PX@ 2 RV189
DQA1_25

co co coM_RAS#1 co M_CS1B#1
M_DA58 G22
G1 M_RAS#0
RASA0B G17 DQA1_26
c
s. om s. om s. oM_CAS#0 2.RV192 m s.
M_DA59 G3 100_0402_1%1 PX@ 2 RV191
m 41,42
100_0402_1%1 PX@ 2 RV190

c c
M_DA60 RASA1B
J6 DQA1_27
c c s o
100_0402_1%1 PX@ 2 RV193

tics.c
100_0402_1%1 PX@
i i i i PX@ 2.c
DQA1_28
c c c
M_DA61 G19

at s. t . t . t
J1 41,42
CASA0B G16 DQA1_29
a cs a cs s
M_DA62
a1 PX@ a
J3 100_0402_1% 1 RV194 M_CKE0 100_0402_1%1 PX@ 2 RV195
M_CAS#1 41,42
m tic m tic ic
M_DA63 CASA1B DQA1_30
i m ti
100_0402_1% 2 RV196 M_CKE1

emat emat
J5 100_0402_1% 1 PX@ 2 RV197
DQA1_31

h e a CSA0B_0 e
H22
a M_CS0B#0 41
e100_0402_1%
a 1 PX@ 2 RV198
chem cheG13m che100_0402_1% chem
+MVREFDA K26 J22 M_WE#0 100_0402_1%1 PX@ 2 RV199

Schem m 1 PX@ 2 RV200

M_CS0B#1 42
+MVREFSA J26 MVREFDA CSA0B_1 M_WE#1 100_0402_1%1 PX@ 2 RV201
S MVREFSA
S S S
okSch ch K13
okSCSA1B_1 okSch okSch
CSA1B_0 M_CS1B#0 41

Sc
C J25 M_CS1B#1 42 C

book
MEM_CALRP0o
book book
R5162 1 PX@ 2 120_0402_1% K25 NC#J25

e e b ok K20
CKEA0 J17 M_CKE0 41,42
e e
ot o ot bo ot bo ot o
CKEA1 M_CKE1 41,42

N teb e
NL10 DRAM_RST G25 M_WE#0 41,42 N e N teb
ot ot
DRAM_RST WEA0B H10
o WEA1B M_WE#1 41,42
o
N R460 1 @ 2 51.1_0402_1% C542 @1 2 0.1U_0402_16V4Z NK8
CLKTESTA
N N
R373 1 @ 2 51.1_0402_1% C541 @1 2 L7
CLKTESTB
0.1U_0402_16V4Z

Route 50ohms single-ended/100ohm dif f and keep s hort 216-0841018 A0 SUN PRO S3
?
debug only, for clock observat i on,if not need, DNI.
m m m m
co co co co c
c s. om cs. om c s. om c s. om s.
i c i c i c i c ic .c
at cs. at cs. at cs. at cs. a t s
emat
i
emat
i
emat
i
emat
i m tic
h h h h hema
Schem Sc em Sc em Sc em c
kS he
Sc o okSch o okSch o okSch ookSc
k k k
eboo eboo eboo b
e oo
ot ot ot ot
N teb N teb N teb N teb
o o o o
N N N N

m m m m
D D

co co co co c
cs. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at cs. at cs. at cs. at cs. at cs.
i i m ti m ti m ti
h emat h emat hema hema hema
c
S he m c m c c c
kS he kS he Security Classification Compal Secret DatakS he Compal Electronics, S he
kInc.
Sc ookSc ookSc 2013/01/11 oo Date S
k
c
2013/12/31 Title ookSc
b
e oo b
e oo
Issued Date
e b
Deciphered
o SUN_MEM te oo b
ot ot ot FROMb
COMPALo
o
N teb N teb eb
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
e THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED THE CUSTODY OF THE COMPETENT DIVISION OF R&D
NPRIORt N
ot Sheet 40 o f 59
C 0.1

o o
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT
o WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-706P
1 N 2 N N3 4
Date:
N
Thursday, March 09, 2017
5
 ot bo ot o ot o ot o
1 2 3 4 5

N te A - Upper 32 bits
Memory Partition N teb N teb N teb
o o o o
N N N N
UV3 UV4 UV5 UV6
M_DA[63..0]
40,42 M_DA[63..0] M_DA41 M_DA58
VREFCA_UV3 M8 E3 M_DA19 VREFCA_UV4 M8 E3 M_DA14 VREFCA_UV5 M8 E3 VREFCA_UV6 M8 E3
M_MA[15..0] VREFDQ_UV3 H1 VREFCA DQL0 F7 M_DA21 VREFDQ_UV4 H1 VREFCA DQL0 F7 M_DA9 VREFDQ_UV5 H1 VREFCA DQL0 F7 M_DA46 VREFDQ_UV6 H1 VREFCA DQL0 F7 M_DA63

om m m m
40,42 M_MA[15..0] VREFDQ DQL1 VREFDQ DQL1 VREFDQ DQL1 VREFDQ DQL1

co M_MA1 co co M_MA0
F2 M_DA18 F2 M_DA15 F2 M_DA43 F2 M_DA59

.c m c
M_DQM[7..0] DQL2 DQL2 DQL2 DQL2

s. om s. om s. om s.
M_MA0 N3 F8 M_MA0
M_DA22 N3 F8 M_DA10 M_MA0 N3 F8 M_DA44 N3 F8 M_DA61
sM_DQS[7..0]
40,42 M_DQM[7..0] A0 DQL3 A0 DQL3 M_DA12 M_MA1 A0 M_MA1 DQL3 M_DA40 A0 DQL3 M_DA57
M_MA1 M_DA17 P7 H3 H3
o
P7 H3 P7 P7 H3
i c c
A1
M_MA2
i c
DQL4
c M_MA2
M_DA23 A1 DQL4
i c
M_DA11
c M_MA2 A1
i c c M_MA2 DQL4 M_DA45 A1
ic .c DQL4 M_DA62
at cs.M_DQS#[7..0] t . at cs. at cs. t
P3 H8 P3 H8 P3 H8 P3 H8
40,42 M_DQS[7..0] A2 DQL5
s s
A2 DQL5 A2 DQL5 A2 DQL5
M_MA3 N2
a G2 M_MA3
M_DA16 N2 G2 M_DA13 M_MA3 N2 M_MA3 G2 M_DA42 N2
a G2 M_DA56

m tic m tic
A3 DQL6
i i i
A3 DQL6 A3 DQL6 A3 DQL6

emat emat m
M_MA4 P8 H7 M_MA4
M_DA20 P8 H7 M_DA8 M_MA4 P8 M_MA4 H7 M_DA47 P8 H7 M_DA60
40,42 M_DQS#[7..0]
t
hD7em e he
A4 DQL7 A4 DQL7 A4 DQL7 A4 DQL7
a a a
M_MA5 P2 M_MA5 P2 M_MA5 P2 M_MA5 P2

A c
h m
A5
M_MA6
A6
R8
c
M_MA6 A5
R8
A6 c h m
M_MA6 A5
A6
R8
c h D7 m
M_MA6
D7 c
R8
M_DA55 m
A5
A6
S he S e DQU0 C3 SM_DA28 e
kSc DQU0 e DQU0 S
he
M_MA7 R2 M_DA4 M_MA7 R2 D7 M_DA26 M_MA7 R2 M_DA39 M_MA7 R2 A
A7
M_MA8
kT8 h
DQU0 C3 M_DA2 M_MA8 A7
T8
ch
oC2kSM_DA31
M_MA8 A7 T8 h C3 M_DA35 M_MA8
kC3 T8M_DA52 A7

Sc ookSDQU2 c A9 o o C8 c
A8 DQU1 A8 DQU1 C8 M_MA9 A8 DQU1 DQU1 A8
S DQU2 S
M_MA9 M_DA7 M_MA9 M_DA27 M_DA38 M_MA9 M_DA51
o o o
R3 C8 R3 R3 C8 R3
k M_DA25 A10/AP k k A7 M_DA53
A9 A9 DQU2 DQU2 C2 A9
ebA10/AP bDQU3 b eboo
M_MA10 L7 C2 M_DA0 M_MA10 L7 M_MA10 L7 M_DA32 M_MA10 C2L7M_DA50
A11 o A11 te oA7 e oA11o
M_MA11 DQU3 A7 M_DA5 M_MA11 A10/AP M_MA11 DQU3 A7 M_DA37 M_MA11 DQU3 A10/AP

ot bo ot ot
R7 R7 R7 R7
M_MA12 DQU4 A2 M_DA1 M_MA12
o o
DQU4 M_DA29 M_MA12 DQU4 A2 M_DA33 M_MA12 DQU4 A2 M_DA49 A11

NA13 teb DQU6 B8 N teb A13 N teb DQU6 B8

N7 N7 A2 N7 N7
A12 DQU5
N te A13
A12
M_MA13 T3DQU5 B8 M_DA6 M_MA13 T3 M_DA24 M_MA13 A12 T3 DQU5 B8 M_DA36 M_MA13 DQU5 M_DA54 A12
T3
DQU6 A3 M_MA14 DQU6 A3 M_DA34 M_MA14 M_DA48 A13
o o o o
M_MA14 T7 M_DA3 M_MA14 T7 A3 M_DA30 T7 A3T7
A14 DQU7 A14 DQU7 A14 DQU7 DQU7 A14
N N N N
M_MA15 M7 M_MA15 M7 M_MA15 M7 M_MA15 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA +1.5VS_VGA A15/BA3

M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2

40,42 M_BA0 BA0 VDD M_BA1 BA0 VDD M_BA1 BA0 VDD M_BA1 BA0 VDD
N8 D9 N8 D9 N8 D9 N8 D9
40,42 M_BA1 BA1 VDD M_BA2 BA1 VDD M_BA2 BA1 VDD M_BA2 BA1 VDD
40,42 M_BA2 M3 G7 M3 G7 M3 G7 M3 G7
BA2 VDD BA2 VDD BA2 VDD BA2 VDD
om m om m
K2 K2 K2 K2

co M_CLK0 co M_CLK1
VDD VDD K8 VDD K8 VDD
K8 K8
.c m
s40,42
VDD
s. om
N1
s .c m VDD
VDD
N1
s. om
VDD N1
s.
c VDD N1
o o
VDD VDD
c c c c
VDD

tics.c
M_CLK0 J7 J7 N9 M_CLK1 J7 N9
i i i i
N9 J7 N9
c c c c
M_CLK0 40,42 M_CLK1
K7 CK
at cs40,42 t s. t s t s.
VDD
. M_CKE0 . M_CLK#1
CK VDD CK VDD
M_CLK#0 K7 R1 M_CLK#0 R1 M_CLK#1 K7 M_CLK#1 K7 CK R1 VDD R1
a+1.5VS_VGA +1.5VS_VGA a a+1.5VS_VGA a
40,42 M_CLK#0 40,42
M_CKE0 CK VDD M_CKE0 K9 CK VDD M_CKE1 CK M_CKE1 K9 CK
VDD VDD
ic ic 40,42 M_CKE1 ic ic
K9 R9 R9 K9 R9 R9
i
emat emat emat emat emat
CKE/CKE0 VDD CKE/CKE0 VDD CKE/CKE0 CKE/CKE0 VDD +1.5VS_VGA VDD

h h h chA1 A1 ch
Schem c A8em c m m m
K1 A1 VRAM_ODT0 K1 A1 K1 VRAM_ODT1 K1

k che
SVDDQ L2 ODT/ODT0 SVDDQ e S he
VDDQ C1 S
40,42 VRAM_ODT0 VDDQ A8 40,42 VRAM_ODT1
L2 ODT/ODT0 M_CS0B#0 L2 ODT/ODT0 A8 M_CS1B#0 ODT/ODT0 VDDQ
J3 CS/CS0 k
chC1 J3 CS/CS0 k h C1 okS
40 M_CS0B#0 40 M_CS1B#0 L2 A8
VDDQ J3 CS/CS0 VDDQ

Sc Sc C9 c
M_RAS#0 M_RAS#1 J3 CS/CS0 VDDQ
K3 RAS o
40,42 M_RAS#0 VDDQoC9 40,42 M_RAS#1
K3 RASo
C1
o k SVDDQ C9 M_CAS#0 K3 RAS
o k S L3 o
VDDQ C9 M_CAS#1 K3 RAS oVDDQ
b b b WE ok b k
40,42 M_CAS#0 CAS VDDQ CAS VDDQ 40,42 M_CAS#1 CAS VDDQ D2
M_WE#0 L3 M_WE#1 L3 CAS VDDQ
o e VDDQoE9 o E9
L3 D2
e e o e
40,42 M_WE#0 D2 WE 40,42 M_WE#1 D2

ot bo ot bo ot b ot bo VDDQ
WE VDDQ VDDQ VDDQ E9 WE VDDQ
E9
VDDQ F1 F1 VDDQ F1
F1
M_DQS2 eF3 e VDDQ e C7 e
N VDDQ H2
N N VDDQ H2
NC7
ot C7 DQSL C7 DQSLt
M_DQS5
t t
M_DQS1 F3 H2 F3 M_DQS7 F3 VDDQ H2
o o o
M_DQS0 VDDQ H9 M_DQS3 VDDQ H9 M_DQS4 DQSL VDDQ H9 M_DQS6 DQSL VDDQ H9
N N N N DQSU
DQSU VDDQ DQSU VDDQ DQSU VDDQ VDDQ

M_DQM2 E7 A9 M_DQM1 E7 A9 M_DQM5 E7 A9 M_DQM7

DML VSS E7 A9
M_DQM0 DML VSS M_DQM3 D3 B3 M_DQM4 D3 DML VSS B3 M_DQM6 DML VSS
B D3 B3 D3 B3 B
DMU VSS DMU VSS E1 DMU VSS DMU VSS
E1 E1 E1
VSS VSS G8 VSS VSS
G8 G8 G8

om om om om
M_DQS#2 VSS M_DQS#1 G3 VSS J2 M_DQS#5 M_DQS#7 VSS VSS
G3 J2 G3 G3 J2 J2
M_DQS#0 DQSL VSS M_DQS#3 B7 DQSL VSS M_DQS#4 DQSL M_DQS#6 VSS
.c m .c m .c m .c m c
J8 B7 B7 DQSL J8 VSS

s.
B7 J8 DQSU J8
DQSU VSS DQSU VSS
s s s s
VSS M1 M1 DQSU M1 VSS M1
ic c o ic c o ic c o ic .c o
tics.c
VSS VSS M9 VSS VSS
M9 M9

at s. at s. at s. t
VSS M9
VSS VSS VSS
P1 P1
a s a P1 P1

m tic 40,42 DRAM_RST# m tic m tic ic ic

VSS DRAM_RST# T2 VSS P9 DRAM_RST# DRAM_RST# VSS VSS
T2
emat emat
T2 P9 T2 P9 P9
RESET VSS RESET VSS RESET VSS
e e e T1 RESET VSS
a a a
T1 T1 T1
h ch m ch m chem chem
VSS L8 VSS T9 VSS VSS
L8 T9 L8 T9

Schem
ZQ/ZQ0 VSS ZQ/ZQ0 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS VSS
kSchB1e kSche S S

1
1
c o 1
o okSc h B1
oo
kB1 ch
1

J1 B1 J1
S SVSSQ B9 B9 S VSSQ S
J1
o o D1 L1 o
NC/ODT1 VSSQ NC/ODT1 VSSQ B9 J1
NC/ODT1 VSSQ
NC/CS1 k k J9 NC/CS1 k k D1
RV68 L1 PX@ RV69 PX@ RV70 L1 NC/ODT1
eJ9bo bVSSQ b J9 NC/CS1 b
RV67 L1 B9
J9 NC/CS1 VSSQ
o oD8 o o
VSSQ D1
te o e e
PX@ 240_0402_1% D1 PX@ 240_0402_1% 240_0402_1% 240_0402_1% VSSQ

ot L9 ot bo t o VSSQ
NC/CE1 VSSQ D8 L9 NC/CE1 NC/CE1 VSSQ
L9 NC/CE1
o oNCZQ1
L9 D8
b b b
D8

2
2
M_CLK0 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 VSSQ E2
N te N te VSSQ E8 N te N te
2

M_CLK#0 VSSQ VSSQ

2

VSSQ E8 E8 VSSQ E8
o VSSQ F9 o F9 M_CLK1
o VSSQ F9 o VSSQ F9
N VSSQ G1 N VSSQ G1
VSSQ
M_CLK#1
N VSSQ G1 N VSSQ G1
1

VSSQ G9 VSSQ VSSQ

1

G9 G9 G9
PX@ VSSQ VSSQ VSSQ VSSQ
PX@

1
1
RV71 RV72 96-BALL 96-BALL 96-BALL 96-BALL
80.6_0402_1% SDRAM DDR3 SDRAM DDR3 PX@ PX@ SDRAM DDR3 SDRAM DDR3
80.6_0402_1%
H5TC2G63FFR-11C_FBGA96 RV75 RV76
m m m m
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
2

co co co co
80.6_0402_1% 80.6_0402_1%
2

X76@ X76@ X76@ X76@

c
s. om s. om s. om s. om s.

2
2
1i
c .c i c c i c c i c c ic c
atPX@cs at s. at cs. at s. at cs.
m tiCV143 m tic i m tic i
+1.5VS_VGA +1.5VS_VGA

e e e m 1tPX@ e emat
a a a a
chem 2 ch m ch m CV166 ch m chem
0.01U_0402_25V7K

S h kSche kSche kSche S

ok ch
C 0.01U_0402_25V7K C

Sc o o o
2

CV139
S S S

CV137
1 o1 kS

CV136
CV131
CV127

CV142
CV126

CV135
o k o k 1o 1 k 1

CV132
CV129

CV133
CV128

CV138

CV141
CV134
CV130

CV140
eboo b eboo b
1 1 1 1 1
o o
1 1 1 1
e 1 1
e 1

ot ot bo ot ot bo
+1.5VS_VGA N teb+1.5VS_VGA +1.5VS_VGA N t e
+1.5VS_VGA N teb2 2 2 2 2 2 2 2 2 2 N t2e 2

10U_0603_6.3V6M
2
o o o o

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10U_0603_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K
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.1U_0402_16V7K

.1U_0402_16V7K
2

.1U_0402_16V7K
.1U_0402_16V7K

.1U_0402_16V7K
.1U_0402_16V7K

.1U_0402_16V7K

10U_0603_6.3V6M
2 2 2

10U_0603_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K

PX@

PX@
@
@
@
@
N N N N

@
@
@

@
@

PX@

PX@
@
@
1
1
1

PX@ PX@
PX@ PX@
RV74 RV210
RV73 RV212
4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 4.99K_0402_1%
m m m m
2

co co co co
2

VREFCA_UV3 VREFCA_UV4 VREFCA_UV5 VREFCA_UV6

2

c
c s. om c s. om c s. om c s. om s.
i .c i c i c i c ic .c
1

at csPX@ atPX@ s. PX@ at cs. at cs. t

1
1

1 1
1 1
a s +1.5VS_VGA
ic m tic
PX@ PX@ PX@
i PX@
i i
emat 4.99K_0402_1% CV144
PX@
m4.99K_0402_1% emat emat
at
RV77 RV78 CV145 RV211 CV224 RV213
0.1U_0402_10V6Ke
hema
CV225
0.1U_0402_10V6K
h h h h
4.99K_0402_1% 4.99K_0402_1%
0.1U_0402_10V6K 0.1U_0402_10V6K
c m c m Sc em Schem c
2 2
2 2
S he S e kSche
2

2
2

c k h okSch okS
ookSc c1 1

CV154
CV153
CV149
1 oo

CV164
CV161
CV160
CV146

CV159
CV147
CV156

CV148

CV152
CV151

CV158
CV155

CV165
CV163
CV157

CV162
CV150
S o k 1o 1
k
1 1 1 1 1
1 kS
1

eboo eb o eboo b
1 1 1 1 1 1 1 1

o t ot bo o t o te oo
N teb+1.5VS_VGA N t e b
N te 2 2 2 2 2 2
N 2
e
2 b2 2

ot

1U_0402_6.3V6K
2

1U_0402_6.3V6K
1U_0402_6.3V6K
2 2

1U_0402_6.3V6K
2 2

1U_0402_6.3V6K
2

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K
2 2

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
2 2

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K
o o +1.5VS_VGA o

PX@
PX@
PX@
+1.5VS_VGA +1.5VS_VGA

PX@
PX@
PX@
PX@

PX@
PX@
PX@

PX@

PX@
PX@

PX@
PX@

PX@
PX@
PX@

PX@
PX@
N N N N
1
1

PX@ PX@ PX@ PX@

D RV214 RV217 RV219 RV221 D
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
m m m m
co co co co
2
2

VREFDQ_UV3 VREFDQ_UV4 VREFDQ_UV5 VREFDQ_UV6

2

c
2

c s. om c s. om c s. om c s. om s.
i c i c i c i c ic c
at csPX@ . atPX@ .1 at cs. at cs. at cs.
1
1

cs PX@
1

1
1

PX@ 1 1
i tiRV218 i i m ti
PX@

emat 4.99K_0402_1% ema ematSecurity Classification emat

PX@ PX@
PX@

hema
RV215 CV226 RV216 CV227 CV228 CV229
h 0.1U_0402_10V6K 4.99K_0402_1%
h
0.1U_0402_10V6K 0.1U_0402_10V6K RV220
h Compal Secret Data h Compal Electronics, Inc.
Schem Schem c m c m c
2 2 4.99K_0402_1% 2 4.99K_0402_1% 2 0.1U_0402_10V6K

kS he S hDate e S he
2
2

k 2013/01/11 k 2013/12/31 Title

oAkUpper
2

Issued Date Deciphered

2

S c o kSo c ookSc oo Sc SUN_VRAM o S c

k k
eb o b AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE b
eboo
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
e oo e o INC.o
TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

ot bo ot otWITHOUT PRIOR ot March

Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-706P
N teb N teb eb 09, 2017 5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
N te Date:N Thursday,
t Sheet 41 of 59
1
o 2
o 3
o 4
o
N N N N
 ot o ot o ot o ot o
1 2 3 4 5

N teb N teb N teb N teb

o o o o
Memory Partition A - Lower 32 bits N N N N

UV7 UV8 UV9 UV10

M_DA[63..0]
40,41 M_DA[63..0]
m m m m VREFCA_UV10
co co VREFDQ_UV8 H1 VREFCA co co
VREFCA_UV7 M8 VREFCA_UV8
E3 M_DA21
M8 E3 M_DA9 VREFCA_UV9 M8 M8 E3 M_DA63E3 M_DA44
c
M_MA[15..0] VREFCA DQL0 DQL0 F7 VREFCA DQL0
H1 VREFCA DQL0 F7

s. o s. om M_MA0 s. om s. om M_MA0 s.
VREFDQ_UV7 H1 F7 M_DA19 M_DA14 VREFDQ_UV9 H1 VREFDQ_UV10 M_DA58F7 M_DA41
40,41 M_MA[15..0]
c m VREFDQ
c
DQL1 F2 VREFDQ
M_DA22 DQL1 F2 M_DA10
c
VREFDQ
c
DQL1
VREFDQ DQL1 F2 M_DA61F2 M_DA45
i c M_DQM[7..0] M_MA0
i DQL2
c M_DA18 DQL2 F8 M_DA15
i c M_MA0
i c
DQL2 DQL2 F8 M_DA59
ic .c M_DA43
at cs. M_DQS[7..0] at cs. at cs. t t
F8
.
N3 F8 N3 N3 N3
40,41 M_DQM[7..0] DQL3
DQL3 P7 A0
P7 A0
s s
P7 A0 DQL3 H3 P7 A0 DQL3 H3
M_MA1 M_MA1
H3 M_DA20 M_DA11 M_MA1
a M_MA1 M_DA60
a
H3 M_DA47

m tic m tic
P3 A1 DQL4
i i ti
P3 A1 DQL4 P3 A1 DQL4 H8 P3 A1 DQL4 H8

emat emat M_DA8 m

M_MA2 M_MA2
H8 M_DA16 M_DA12 M_MA2 M_MA2 M_DA56H8 M_DA42
40,41 M_DQS[7..0]
e N2 A2
hema e
N2 A2 DQL5 DQL5
N2 A2 DQL5 G2
N2 A2 DQL5 G2
a a
M_MA3 M_MA3
G2 M_DA23 M_MA3 M_MA3 M_DA62G2 M_DA46

A c
h m
40,41 M_DQS#[7..0]
M_DQS#[7..0] M_MA4 P8 A3
P2 A4
h
c em
DQL6
DQL7
M_MA4
H7 P8 A3
M_DA17 DQL6 H7
h
M_DA13
c em
M_MA4 P8 A3
P2 A4 c
M_MA4 DQL6
P8 A3
DQL7
P2 A4 DQL7 ch
DQL6 H7 M_DA57
m
H7 M_DA40

he
P2 A4 DQL7
S M_MA5
R8 A5 kS
M_MA5
kSD7ch
M_MA5
S he M_MA5
S he A

ch A6k
ok
M_MA6 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5

S c M_MA7
o
R2 o
A6
S D7 M_DA2 M_MA7 R2 A6
o oDQU0S
M_DA28 M_MA7
o
R2 o
S c DQU0 D7 M_DA35 M_MA7 R2 A6
o S cD7 M_DA52
M_MA9 b R3 A8k k C8 M_DA26 k okDQU1
T8 A7 DQU0 C3
T8 A7 T8 A7 T8 A7 DQU0
b oDQU1 b R3oA8 A8b
M_MA8 M_DA4 M_MA8 C3 M_MA8 C3 M_DA37 M_MA8 C3 M_DA55

t e o o DQU1 C8 M_DA0 M_MA9 R3 A8

t e M_DA31
te o
M_MA9 DQU1 C8 M_DA32 M_MA9 R3e M_DA50

ot
C8

bo DQU3 bo
L7 A9 DQU2 C2 A9 DQU2 L7 A9 DQU2 C2
L7 A9 DQU2 C2
o o o
M_MA10 M_DA7 M_MA10 M_DA27 M_MA10 M_DA39 M_MA10 M_DA51
e
N M_MA11b R7 A10/AP DQU3 A7 M_DA3 M_MA11
N
L7
e
R7 A10/AP
C2
A7 M_DA30 M_MA11 b R7 A10/AP
e
N M_MA12
DQU3 A7 M_DA34 M_MA11
N e
R7 A10/AP DQU3 A7 M_DA48
t
M_MA12
oM_MA13 N7 A11 DQU4 A2 M_DA6 M_MA12 N7t
o
A11 DQU4 A2 M_DA24
o t N7 A11
A12
DQU4
DQU5
A2 M_DA38 M_MA12
o t
N7 A11 DQU4 A2 M_DA54
T3 A12 DQU5 B8 M_MA13 T3 A12 DQU5 B8 A12 DQU5
N M_MA14 M_MA14N T7 A13 N M_MA14 N T3
M_DA1 M_DA29 M_MA13 T3 B8 M_DA33 M_MA13 B8 M_DA49
T7 A13 DQU6 A3 M_DA5 DQU6 A3 M_DA25 T7 A13 DQU6 A3 M_DA36 M_MA14 T7 A13 DQU6 A3 M_DA53
A14
M_MA15 M7DQU7 M_MA15 A14 DQU7 M_MA15 A14 M7 DQU7 A14 DQU7 M_MA15
M7 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA

M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2

40,41 M_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
m m m m
N8 D9 M_BA1 N8 D9 M_BA1 N8 D9 M_BA1 N8 D9
40,41 M_BA1
co co co co
BA1 VDD M_BA2 BA1 VDD M_BA2 M3 BA1 VDD G7 M_BA2 BA1 VDD
M3 G7 M3 G7 M3 G7
40,41 M_BA2
c
s. om s. om s. om s. om s.
BA2 VDD K2 BA2 VDD BA2 VDD K2 BA2 VDD
K2 K2
VDD VDD VDD
c c
VDD
i c i c
K8 K8
i c c i c c VDD
K8
tics.c
K8

at cs. 40,41 M_CLK0 at cs. at s. 40,41 M_CLK1 at cs.

VDD N1 VDD N1 VDD
N1 N1
VDD M_CLK0 VDD VDD M_CLK1
a VDD
m tic m tic
J7 N9 J7 N9 J7 N9 J7 N9
i i i
emat emat +1.5VS_VGA emat +1.5VS_VGA
K7 CK VDD R1 M_CLK#0 K7 CK VDD K7 CK VDD R1 M_CLK#1 CK K7 VDD R1
e+1.5VS_VGA hem
40,41 M_CLK#0 R1 40,41 M_CLK#1
h 40,41 M_CKE0 K9 CK
h
VDD R9 M_CKE0 K9 CK
h
VDD R9a 40,41 M_CKE1
K9 CK
CKE/CKE0 h
VDD R9 M_CKE1 CK
a K9 VDD R9
c m c m c m c c
VDD
m
CKE/CKE0 VDD CKE/CKE0 VDD CKE/CKE0 +1.5VS_VGA VDD
S he kS he A1 kSA1che kS he A1 k S A1he
Sc ODT/ODT0 c VDDQ A8 ODT/ODT0c VDDQ A8 c
VRAM_ODT0 K1
L2 o L2 ODT/ODT0oo L2 o o
K1 K1 VRAM_ODT1 K1
40,41 VRAM_ODT0 40,41 VRAM_ODT1
o S VDDQ C1 SC1 o S S A8
book
M_CS0B#1 VDDQ A8 M_CS1B#1 L2 ODT/ODT0 VDDQ
40 M_CS0B#1
b k
J3 CS/CS0 M_RAS#0
b
J3 CS/CS0 k
VDDQ 40 M_CS1B#1
b k
J3 CS/CS0 VDDQ C1 M_RAS#1 J3 CS/CS0 VDDQ
e K3 o oVDDQ C9 o C1
K3 te te o K3 e
40,41 M_RAS#0 40,41 M_RAS#1 RAS VDDQ C9

ot bo ot
RAS VDDQ C9 RAS VDDQ C9
L3 CAS bo o
M_CAS#0 RAS VDDQ K3 M_CAS#1
o o
40,41 M_CAS#0 40,41 M_CAS#1
b L3 CAS
b
L3 CAS VDDQ D2 VDDQ D2
M_WE#0
D2 M_WE#1 L3 CAS VDDQ D2
N te N te N te N te
40,41 M_WE#0 WE VDDQ E9 WE VDDQ 40,41 M_WE#1 WE VDDQ E9 WE VDDQ E9
E9
oM_DQS2 F3 o o o F3
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
N M_DQS0 C7 DQSL N N N C7
VDDQ H2 M_DQS1 VDDQ H2 M_DQS5 F3 VDDQ H2 M_DQS7 VDDQ H2
VDDQ H9 F3 DQSL VDDQ
M_DQS3 M_DQS4 DQSL VDDQ H9
DQSU VDDQ C7 DQSL VDDQ H9 C7 H9
DQSU VDDQ
M_DQS6
DQSU VDDQ DQSU VDDQ
B B
M_DQM2 E7 A9 M_DQM1 M_DQM5 E7 A9 M_DQM7 E7 A9
DML VSS E7 A9 DML VSS
M_DQM0 D3 B3 M_DQM3 DML VSS M_DQM4 D3 B3 M_DQM6 D3 DML VSS B3
D3 B3

om om M_DQS#1 om om
DMU VSS DMU VSS DMU VSS E1 DMU VSS
E1 E1 E1
VSS VSS VSS
.c m .c m M_DQS#3 .c m .c m c
G8 VSS G8
s.
G8 VSS G8
M_DQS#2 VSS
s s s s
G3 J2 VSS M_DQS#5 G3 J2 M_DQS#7 G3 VSS J2
G3 J2
ic c o M_DQS#0 B7 DQSL
ic c
VSS
o J8 B7 DQSL
ic c o VSS M_DQS#4 B7 DQSL
ic c o VSS J8 M_DQS#6
ic c B7 DQSL VSS J8
at s. at s. at s. at s. at cs.
DQSU VSS J8 DQSU VSS
M1 DQSU VSS M1 DQSU VSS M1
M1
m tic m tic m tic m tic
VSS VSS VSS VSS
i
M9 M9

emat
M9 VSS M9
VSS VSS
e e e e
P1 VSS P1
a a a a
P1 P1
h ch m ch m ch m chem
VSS DRAM_RST# VSS DRAM_RST# T2 VSS P9 DRAM_RST# VSS
T2 P9 T2 P9

Schem
40,41 DRAM_RST# RESET VSS T2 P9 RESET VSS
RESET VSS RESET VSS

kSche kSche kSche

T1
S
T1 T1 T1
VSS VSS

okSch
L8 T9 VSS L8 T9 L8 VSS T9
L8 T9

S c o
ZQ/ZQ0 VSS ZQ/ZQ0
o VSS
o
ZQ/ZQ0 VSS ZQ/ZQ0 VSS

bo kS VSSQ B1 o kS o kS bookVSSQ B1

1
1
L1 o eb oVSSQ B1
1
RV81 b J1o
1

te o te o e
J1 B1 RV82 J1
L1 tNC/ODT1o 240_0402_1% t
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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
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N N Security Classification N Compal Secret Data N Compal Electronics, Inc.
Issued Date 2016/09/01 Deciphered Date 2019/09/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

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Date: Thursday, March 09, 2017 Sheet 48 of 59

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kS he kS he Security Classification Compal Secret DatakS he Compal Electronics, Inc. kS he
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e oo e oo e o INC. AND CONTAINS CONFIDENTIAL CPU_CORE
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,

N teb N teb DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHERb

N teb
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
NPRIOR t e CONSENTSHEET NOR THE INFORMATION IT CONTAINS 1.0
o o o Thursday, March 09, 2017o
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT WRITTEN OF COMPAL ELECTRONICS, INC.

N N N N
Date: Sheet 52 of 59
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